SU1019451A1 - Device for checking computer - Google Patents

Abstract

DEVICE FOR THE CONTROL OF THE ELECTRONIC COMPUTING MACHINE, containing bpok counters, yes-. encoder, two triggers, two OR elements, two AND elements, the AND-HED element, the OR-NOT element, two impediments and a delay element, the input of which is connected to the output of the first element of the OR element, and the output of the element is connected to the control input- the device’s output, the nespBOMy input of the second OR input, the control input of the drive (| tory and the group of counting inputs of the counter block, the input is connected to the device’s address input-output, and the decoder's output is connected to the input of the first OR terminal, the second input of the second OR element the entrance of the first f pulse | pulse and pulse and information input of the meter block information input, count inhibit input, the first to the second information receiving inputs, information inputs, a group of outputs of the outputs and the outputs of the meter block, are connected respectively to the outputs of the NAND element, the second and first pulse shapers, additional informational input-output of the device, informational input-output of the device and the inputs of the element ILINE, the output of which is CONNECTED to the first input of the first element AND and info (the input of the first trigger, the output of the second el And is connected to the second {lm input of the first E and E and synchronous input of the first trigger, the installation input and inverse of which are connected respectively to the output of the encoder and the first input of the IEE element, the first and second inputs and the output of the second trigger are connected to the outputs of the decoder and The second element OR and the second input 4 elements AND-NOT, the output of the first element AND 1Y "is connected to the input of the second fordvatel impulses, and the output of the element AND-NOT soy I is dinene with the first input of the second email. And the output of the device, characterized by, 4To, fc; The whole step is the reliability of the counterflash, it contains the third, fourth and fifth triggers, the third element And the second delay element, two registers and the Comparison circuit, the first and second inputs of which are connected to the outputs corresponding to the first and second registers, informational Bxo {ui of the first and second pe-CO 4 SL of the gist are connected respectively with the additional information on the code output and info | The first 1M input-output of the device, the first and second registers, the third and fourth triggers, and the third, fourth, and fifth trigger inputs are connected to the control input of the device, the information inputs of the third and fourth triggers are connected to the common bus of the device, the first and the second inputs and output of the third element And, respectively, to the outputs of the third and fourth triggers and

Description

the input of the SECOND eaperzh epement, while the information input, the synchronous input and the output of the fifth trigger are connected to the syote “

vetvestino with the outputs of the comparison circuit to the second delay epec and the second input of the second epemen I.

The invention relates to digital computing technology and can also be applied to computing devices based on the principle of a common master pi.

It is known a device dp kontrop electronic computing machines, (computers), containing interconnected coarse unidirectional and bidirectional, communications interface unit, information analysis unit, test signal output unit and control unit l

In the course of computer operation, this device periodically checks its operability and, if possible, calibrates and logically isolates the failed unit. At the same time, the time between the appearance of a failure and its detection can be quite long (equal to the time between checks), which is unacceptable in some cases. On the other hand, an increase in the frequency of inspections reduces the performance of a computer, since all the greater part of the computer time is spent on performing control, rather than pepeznyh operations.

The closest in technical essence to the predgate is a computer control device dp, containing a block of counters, a decoder, two triggers, two OR elements, two AND elements, an AND-NOT element, an OR-NOT element, two pulse pulses, and a delay element, address inputs The device is connected through a decoder to the inputs of the first OR element, to the first input of the second OR epimete, to the installation inputs of the first and second triggers, to the input of the first form.4 pulser, and to the information output input of the counter block, These device inputs are connected to the group of inputs of the outputs of the counter counters, the group of control inputs of the outputs of the device are connected to the group of counting inputs of the block of meters, with the control input of the decoder, with the input of the aa element, the holder and the second input of the BTOpojO element OR,

the group of additional inputs of the device is connected to the information inputs of the meter counter whose outputs through the element OR NOT are connected to the information input of the first trigger and to the first input of the first element AND whose output is connected to the first input of the information block through the second pulse driver, the second input of the first element And it is connected to the output of the second epemen And and to the synchronizing input of the first trigger, well, which is connected to the first input of the NAND element, whose second input is connected with the output of the second trigger, the reset input of which is connected to the output of the second OR element, the output of the NAND element is the output of the device and connected to the first input of the second E and E and to the input of the counters prohibitance counter, the output of the nepBiOro of the pulse generator is connected to the second input receiving information block counters, the output of the first element OR is connected to the input of the delay element.

In the course of the computer operation, simultaneously with the selection of the next command from the memory

: programs from the additional memory is retrieved constant, different from zero or equal to zero. The first case corresponds to the output processor on the next

; linear segment of the program LIy, the second choice of the subsequent given linear segment. The constant extracted from the memory is a set of matrix-sized reference numbers that predict the number of expected signals on the control pins of the interface interfaced by the processor of this linear portion of the program.

A disadvantage of this device is the inability to detect some errors. For example, if as a result of losing a bit in a memory, a link is broken in a line, or in a matching key, etc. In the processor of the command for adding a post to the command of subtraction, this error will not be detected, since both commands are accompanied by the same control signals on the interface pins. The chain of the invention is to increase the apostasy of the controp. The delivery is achieved by a Kto device dp counter of an electronic computer machine containing a bpok counter, a decoder, two triggers. Two OR elements, two AND elements, NAND element, OR OR NOT element, two impedance formers and a delay element, whose input is connected to b1 with the first element OR, and the output of the delay element is connected to the control input of the device, the first input the second element OR, the control input of the decoder and the group of counting inputs of the counter block, the input of the decoder is connected to the address input-output of the device, and the output of the decoder is connected to the input of the first OR element, the second input of the second OR element, the first driver pulses and the input of calculating the information of the block of counters, the input of the prohibition of the account, the first and second inputs of receiving information, information inputs, a group of inputs-outputs and outputs of the block of meters are connected respectively to the outputs of the AND-NES element, the second and the first impressors, and additional information input -the device output, information input-output device and inputs of the element OR NOT, the output of which is connected to the first input of the first AND element and information input of the first trigger, the output of the second element AND n with the second input of the first element AND and the sync input of the first trigger, the setup input and the inverse stroke of which are connected respectively to the output of the decoder and the first input of the NAND element, the first and second inputs and the output of the second trigger are respectively connected to the output of the encoder and the second OR element and the second input element AND-NOT, the output of the first element AND is connected to the input of the second pulse shaper, and the output of the element AND-NOT is connected to the first input of the second element AND and the device output, entering the third, fourth and fifth three heres, the third E and the second delay element, two registers and a comparison circuit, the first and second inputs of which are connected to the outputs of the first and second registers respectively, the information inputs of the first and second registers are connected respectively to the information input output and information input device of the device, sync inputs of the first second registers, the third and fourth triggers, and the setup inputs of the retego, the fourth and fifth triggers are connected to the control input of the device, information the inputs of the third and fourth triggers are connected to the common bus of the device, the first and second inputs and No. 1 of the third element I are connected respectively to the outputs of the third and fourth triggers and the input of the second delay element, while the information input, the synchronous input and the output of the fifth trigger are respectively connected The cpu & n circuit and the second delay element and the second input of the second element i. In FIG. 1 shows a functional computer explaining the purpose of the proposed control device; in fig. 2 - functional diagram of the device dp control; in fig. 3 - the block meter circuit is functional; in fig. 4 - the counter is functional; in fig. 5 is a functional diagram of an address translation unit; in fig. 6 - functional scheme of the interface block; in fig. 7 is a temporary diagram of the operation of the device. The electronic computational machine (Fig. 1) comprises a processor 1, a control device 2, an interface unit 3, a memory unit 4 including a data memory 5 and a program memory 6, an address conversion unit 7 and an additional memory unit 8. Blocks 3,5,7 and 8 are connected via a group of buses 9, including address 10, information 11 and control buses 12. Outputs 13 of block 8 are connected to inputs 14 of block 3 by means of information chic 15. Processor 1 is connected to a device 2 and block 3 via a group of 16 buses, including address 17, informational 18 and control buses 19, Device 2 and block 3 are also connected via a group of additional information buses 20. The output of device 2 is connected to the interrupt input of processor 1 via line 21 The outputs of block 7 are connected to the address by the inputs of block 8 through a group of tires 22, the device 2 for control (FIG. 2) contains a block 23 of counters, a decoder 24, triggers 25-29, elements 510 OR 30 and 31, epemngs AND 32-34, AND-HE 35 , forming 36 and 37 pulses, delay elements 38 and 39, registers 40 and 41, comparison circuit 42 AND element OR NOT 43. The address buses 17 of device 2 are connected via a decoder 24 from the input element 1 of element OR 30 to the first input element OR 31, the installation inputs of the trigger 25, and 26, with the input of the imaging unit 36 and with the input 44 of the issuance of information block 23 counters. The information buses 18 of the device 2 are connected to the group 45 of inputs to the E-outputs 23 and to the inputs of the register 41. The control buses 19 of the device 2 are connected to the group 46 of the counting inputs | of the block 23, to the control input of the decoder 24, to the output of the element 38, with the second input of the element OR 31, the synchronous inputs of the registers 4O and 41, with the installation inputs of the flip-flops 27 and 28, with the sync dyme of these triggers and with the reset input of the flip-flop 29. The inputs of the device 2 connected to the bus 20 are connected with the information inputs 47 block 23 and with the inputs of the register 40. The outputs 48 of the block 23 are connected to the inputs element 43, the output of which is connected to the information input of the trigger 25 and the first input of the element 32. The output of the element 32 through the imaging unit 37 is connected to the input 49 of receiving information block 23. The second input of the element 32 is connected to the output. 25, the zero output of which is connected to the first input of the NAND 35, the second input of which is connected to the output of the trigger 26. The reset input of the trigger 26 is connected to the output of the 51ENT element OR 31. The output of the NAND 35 is output 21 of the device and connected to the first input element And 33 and with block 50 blocking house 50. The output of the imaging unit 36 is connected to the input 51 of receiving the information block 23. The output of the OR element 20 is connected to the input of the element 38. The outputs of the registers 40 and 41 are connected to the inputs of the circuit 42, the output of which is connected to the information input of the trigger 29, the output of which is connected to the second input element And 33. The outputs of the trigger 27 and 28 are connected to the inputs of the element 34, the output of which through the element 39 is connected to the synchronous input of the trigger 29. Information

the inputs of the trigger 27 and 28 are connected to a common bus 52.

element IN-NOT (inverter) 69 - with the input of element 67. S16 The meter block 23 (Fig. 3) contains a group of 53 counters and a group of 54 epemings I. The first inputs of the And 54 sequences are combined and are the input 50 of the counting section, the second inputs of the emitters of the group 46 of the counting inputs of the block 23. The outputs of the elements 54 and schehediena with the counting inputs of the 55 corresponding counters 53, the group 47 of the information inputs of the block 23 are connected to the information inputs of the counters 53, the input 49 of the reception of the information of the block 23 53. The outputs of the counters 53 are group of outputs 48 of block 23, inputs-outputs of counters 53 - group of input & output 45 of block 23, Input 51 of receiving information of block 23 is connected to inputs of receiving information of counters 53, input 44 of issuing information of block 23 - with inputs of issuing information of counters 53. Counter 53 (FIG. 4) contains serially connected single-bit cells 56 and transmitting elements 57. The output of the cells 56 is connected to the information inputs 58 of the elements 57 and are information outputs of the counter. The control elements 57 are combined and connected to the output 44 of the dispenser. The outputs of the elements 57 are connected to the inputs 59 of the respective cells and are a group of INPUT & OUTPUTS 45. The inputs for receiving information from line 45. all cells 56 are merged and connected. OL "- B-" 6O cells 56 are a group of 47 inputs. The inputs for receiving information from line 47 of the cell are 56gb “dinene and are connected to the input 49 of the array. Cell 56 contains a trigger 61,., Ft, - .V "L 1G g JI f elements OR 62 and 63, elements AND 6467, and AND-NOT elements 68 and 69. The sync input of the trigger 61 low-order cells is counting input 55 counter 53, the single output of the trigger 61 - the output of the cell. The zero output of the flip-flop 61 is connected to the information input of the same flip-flop, the inputs of the set AND reset flip-flop 61 are connected respectively to the outputs of the OR 62 and 63 elements whose inputs are connected to the outputs of the AND 6467 elements. Input 49 is connected to the inputs of E 64 and 64. 66, input 51 - with the inputs of elements And 65 and 67. The input 60 is connected to the input of element And 64 and through element 68 - to the input of element 66. Input 59 is connected to the input of element And 65 and the address converter 7 (figure 5 contains the decoder 70, OR elements 71 and 72, trigger 73 and an EXCLUSIVE OR element 74. The address inputs of the decoder 7O are connected to the bus 10. Control input 75 of the decoder 70, the first input 76 of the element OR 71 and the output of the element OR 72 are connected to the bus 12. Output 77 of the decoder 7O is connected to the input of the trigger setup 73 with the first input of the OR 72 element. Output 78 of the decoder 70 Connected to the second input element OR 72 and to the second input element OR 71. The output, element OR 71 is connected to the reset input of the trigger 73, the zero output of which is connected to the first input 79 of the element 74, the second input 80 of which is connected to the address input of the higher digit of the 7O decoder The output 81 of the element 74, as well as all the address inputs of the decoder 70, except for the input connected to the input 8O of the element 74, is a group of outputs 22 of the address conversion unit 7.

Interface unit 3 (FIG. 6) contains transceiver elements. To transfer the address from bus 17 to bus 10, the following elements are used: 82 control inputs KOTOF IX are combined and connected to line 83, which is part of bus 19 Depending on the value of the signal at the control input of element 82, it is either closed (high output), Dibo broadcasts a signal from input to output Dp of bidirectional data transmission between buses 11 and 18, pairwise connected 82 are used, the control inputs of which are connected to lines 84 and 85 included in part 19. Depending on the values of the sipnals on Inputs 84 and 85 are selected then or other direction of data transmission. For interfacing bus 12 with bus 19, various types of elements are used: cable amplifiers 86 (unmanaged), elements 82 controlled by lines 87 and 88, as well as asynchronous self-driving bidirectional transceivers 89, made on standard logic elements ( Wew E6ecii OHiC5. 1 979, hfe 16, p. 52). Data is transferred from bus 14 to bus 2O using cable amplifiers 8.6.

The time diagram of the operation of the device (Fig. 7) shows the diagrams 9O-92 of the stone contents of the three counters 53. The y axis shows the decimal numbers accumulated in the counters. The time points 93-95 correspond to the time when the computer exits on the basis of certain linear program sections. Plot 96 displays the signals at. trigger input trigger 25. Plot 97 corresponds to the signal at the output 21 of the device. Consider the construction of a computer control system.

Any program recorded in machine codes in the computer memory can be represented as a set of linear sections connected with each other by j transition commands. The transition command is the final command of the linear section if it is not the last linear section of the program — in this case, the linear section can be completed, for example, with the Stop command. The initial command of a linear section can be either a command that is an external input to the program, or a command to which control transfer of one of the transition commands is made. If a certain linear section of the program contains several initial commands (entry points), then it can be considered as a chain of several linear sections, each of which has one initial command. In this case, the final command of 71 Any chain link, except the last one, is the command preceding the start command of the next link.

Thus, any program can be divided into separate linear sections where the behavior of a computer is strictly: deterministic, in the sense that the control board passes the computer and through a given linear section of programs on the interface control lines a strictly defined number of pulses must be registered. ; It is known for each linear section even before the start of the computer work on the program.  This statement remains valid even when the process of passing a given linear segment is temporarily suspended due to the reaction and external program-independent events (preliminaries).  In these cases, as usual, the stack mechanism of remembering and recovering the necessary information is used.  The set of interface control signals that accompany the execution of conditional jump instructions does not depend on whether or not the test condition is fulfilled (Klingman E.  Designing microprocessor systems.  M. World, 1980, p.  155-158).  The main idea of the system kontrop computer can be expressed in the following way.  one .  After the translation of the original program into the language of machine commands (or in the process of translation), the work program is analyzed with the detection circuit of all linear sections.  The list of addresses of the initial commands of the linear sections is memorized.  2  The number of pulses on one or another interface control line is predicted for each linear section by successive arithmetic addition of some constants, each of which corresponds to its own command and depends on the design features of a specific computer.  In the counting result, for example, it is determined that with a complete and error-free passing of the linear section A, the interface control lines x, X2 and x must have 50, 20 and 11 pulses, respectively.  This information is stored and subsequently used to control the passage of section A when it reaches its beginning.  3  The start of the work program.  The correctness of its execution is controlled by special hardware.  Simultaneously with the selection from the main memory of the initial command of a certain linear section, the service information is retrieved from the additional memory, which determines the expected HHO number of pulses on the interface control lines.  This information is placed in the counters, the contents of which are further reduced as this section of the program is processed, t. e.  as the interface control lines transmit pulse signals.  By the moment of transition to the beginning of the new linear section, the contents of all the counters are checked for equality to zero and, if this condition is met, the counters are loaded with new information corresponding to the new linear section of the program.  four.  If the one selected from the main memory is not the initial command of the linear section, then a copy of this command is selected from the additional memory and checked for a match with the command from the main memory.  five.  When the computer is working properly, the exit to the beginning of the next linear segment is accompanied by a discrepancy in information selected from the main and additional memory, since its main memory is a biraeg command, and from the additional memory - the new contents of the counters.  If during the formation of the auxiliary information array it appears that the command code exactly coincided with the service constant (new counter contents), then in this linear section, an extra hypo command can be entered. There is no operation, processing of which is accompanied by the appearance of excess pulses on the interface lines that will see a change in the service co-office.  An alternative possibility of recognizing the initial commands of linear sections is provided, for example, by inserting an extra bit into the word memory format.  6, If by the time you overturn the counters, their contents are not zero, then an interrupt signal is sent to the processor to prevent further execution of the work program and causing the transition to the previously scheduled control mode of the object connected to the computer.  Thus, the likelihood of emergency situations that can occur in a controlled object as a result of a computer walks through the work program as a result of a crash or failure.  The time between the occurrence of a failure (failure) and its detection does not exceed the time of passage of the linear section of the maximum length and, since the latter can be artificially divided into sufficiently short links: 1 It can be, for example, several seconds.  The device works as follows.  The computer is reset by supplying a logical unit to the line General reset, which is part of tires 12 and 19.  A wall on this line is formed automatically after power is turned on, or, for example, it appears as a result of pressing the corresponding button on the control panel.  The Common Gray signal initializes the processor 1, the forerunner part of the memory 5, 6 and 8, respectively, and also prohibits the issuance of the interrupt signal from the device 2 to the processor 1 on pin 21 and configures the block 7 so that the memory addresses 6 and memory 8 do not match.  The prohibition of interrupting a signal is performed in the following manner.  The signaling overlap comes from the bus 19 (FIG.  . 2) to the input of the OR OR 31, a. from his start - to the trigger reset input 26.  A zero signal from the output of the trigger 26 blocks the NAND element 35, as a result of which the signal at the output 21 of this element takes on a single value.  This gap corresponds to no interrupt.  The setting of block 7 for the separation of the addresses of memory 6 and memory 8 is carried out upon signal arrival. A general reset from bus 12 (FIG. 5) on line 76 to the input of the element OR 71, and from its output to the reset input of the trigger 73.  A single signal from the zero input of this trigger, via line 79, goes to the first input element 74, which can be considered as an inverter connected between pin 80 and 81.  Thus, the address codes that come later from the bus 10 are fed to the bus 22 with the higher bit inverted.  This leads to the separation of addresses, as shown in the following example.  Let the number of lines of address buses 17 10 be 16.  In this case, the address space of the computer is 64K, where K is 1024.  Let further the zones of proprietary addresses of memory 6 and memory 8 coincide and lie within the LLC.  O37777d (16K).  If processor 1 addresses any address within the specified range, then this address is from bus 17 (FIG.).  transmitted through the interface 3 to the pgana 10.  From this bus, the address is stored in memory 6, which perceives it as its own and performs a read operation or write one of the cells.  At the same time, the address, the passage from bus 10 through block 7 to bus 22, is distorted due to inversion. 8 consider it as a stranger, lying in the range 10OOOO-137777g.  Therefore, exchange with memory 8 is not performed.  The address & 8 memory 8 processor 1 generates on bus 17 an address containing the code 10.2 in the two high-order bits.  In this case, memory 6 does not perform an exchange operation (the address lies in a foreign range), and memory 8 regards it as its own, since in the higher bits of the address code on bus 22 there is a combination of OO defining the zone OOOOOO037777g.  10 3112 When a computer is running, the need arises. -Disc alignment of the address spaces covered by memory blocks 6 and 8.  For this, trigger 73 (FIG.  5) switches over the circuit 1O-7O-77 to the opposite state, as a result of which the element 74 transmits the higher address bit to the bus 22 without distortion.  In this case, the addresses of memory 6 and memory 8 are the same, and exchange operations are executed in them synchronously.  The memory 6, as well as the memory 8, can be performed in the form of a permanent, special or operative memory, or a combination thereof.  We will assume that memory 6 and memory 8 contain both the permanent and operational parts; After the termination of the signal General reset, the processor automatically or at the initiative of the operator proceeds to the execution of one of the programs recorded in the fixed part of the memory 6.  Such a program may be a zagruechik program, under which the information is entered into the computer and placed in the operational part of the memory 6.  The input procedure is determined by the composition of the peripheral devices connected to the computer, the interface, the command system and other characteristics of the specific computer.  This procedure is carried out in one of the most known ways.  The input data is stored in memory 5.  The program entered into memory 6 is represented as a sequence of machine codes, m. e.  the input can be accompanied by the input of a previously prepared array of auxiliary information into the additional memory 8 (the address spaces occupied by memory blocks 6 and 8 do not match at the input stage).  If the auxiliary information is absent, it is formed by the computer itself during the piaboTB special program for allocating linear sections.  If a program 6 is entered into memory, written in a language other than the language of machine codes, then it is translated into this language as a result of the translation program.  After that, to ensure the self-control of the computer, it is also necessary to form in the memory Into an array of auxiliary information, the dp of which is used to select the linear sections.  The linear allocation program is implemented as follows.  In all cells (lOOOOO-137777g} of memory 8, processor 1 sequentially writes copies of the codes located in memory 6.  Consistently analyzing the work program recorded in memory 6 in machine codes, processor 1 is determined by the address of the beginning of the AN and the address of the end AJ of the next (lth) peak part KQ of the working program and calculates the number of points nx I PUs that are generated. on pini x, xs.   X tires 19 while continuously running.  Computer on the i-th pinny site.  Koy P. ,, jj, is stored in memory 8 at (address mixed with the Address at 32K.  The components of this code (, 2, vi) are loaded into and counters 53 (FIG.  3) -; at the exit of the computer at the head of the i-th pnice section.  Thus, after the end of the work program of ejection of the pinewoods in the memory 8, the following information is formed: If the address of the memory cell is equal to the address of the beginning of some linear section of the work program that was increased to 32K, then this code stores the code for subsequent loading of 53 at the exit of the computer at the beginning of this area; if the address of the memory cell does not satisfy the specified condition, then this cell contains a copy of the code located in the corresponding cell of par. 6.  Further, when combining the address spaces occupied by blocks 6 and 8, the program and auxiliary information is extracted from these blocks. synchronously, therefore, a sign of the beginning of the next linear section of the work program is the appearance of mismatching information at the outputs of blocks 6 and 8 when accessing them.  After the array of information in the additional memory 8 has been formed, the control is transferred to the beginning of the work program by executing the next transition program (n.   one.  Combine addressing is simple, covered by blocks 6 and 8.  This command is a normal command to transfer data from the processor register to the memory. Data can be any, since they are not used, and the address to which the decoder 70 is specified as the memory address (FIG. 5 reacts by issuing a signal to exit 77.  The strobe signal of the decoder 70, received on the pin 25 of the bus 12, is an interface signal confirming the validity of the address set on the bus 10, and is generated by the processor.  Under the action of the signal from the output 77 of the decoder 7O, firstly, a response signal is generated at the output of the element OR 72 to notify processor 1 of the completion of the write operation (processor 1, upon receipt of this signal, releases buses 16 and 9), and, secondly, the trigger 73 is switched to a state where the logical zero signal is maintained at the input 79 of the constant element 74, as a result of which the high-order bit of the address from the line 80 enters the line 81 without inverting.  Starting from this point in time, from the point of view of processor 1, the addresses of memory blocks 6 and 8 coincide and lie within the LLC LLC 037777g, and the information on the expected number of pulses on the interface lines (block 8) is exactly docked to the addresses of the corresponding initial linear commands sections of the work program (block 6).  2  Download counters 53 from the data bus.  This, as well as the previous f, is supplied by the transfer command to the specified address of the contents of one of the processor registers, in KOTopq. M pre-prepared code for loading counters.  This code is chosen so that by the time the command 3 is selected from the memory 6 of the command 3, the contents of the counters 53 operating in the subtraction mode (counting the signals on the bus lines 19) are zero.  The write address is recognized by the decoder 24 when the control input is verified by an address confirmation signal, as a result of which the driver 36 is triggered and the information from the bus 18 is written to the counters 53.  A response signal about the end of the operation is sent to the processor via circuit 30-38-19-1.  Information is received in the counter even if there is a pulse at its counting input (t. e.  unconditionally), since the control over the RS inputs of the D flip-flop 61 is more priority than the control over the synchronization input C.  .  3 Set trigger 26 to a state that allows the output of the pre-piny 21 signal.  This command is marked in memory 8 as the initial one, hence the selection of the command itself from memory 6 on circuit 6g11-3-18-1 is accompanied by the selection of some (not coinciding with it) information from memory 8 on circuit 8-13-15-14 -3-20-2 (FIG.  one).  The information from memory 6 in memory 8, with corresponding tracking signals, is stored in registers 41 and 40.  In the presence of readiness of blocks 6 and 8, the triggers 28 and 27 are placed in the single state, previously cleared at the beginning of the interface signal, by the master pi.  The signals from the flip-flops 28 and 27 are received through the element 34 and the element 39 of the delay on the synchronous trigger 29.  At this point in time, the logical unit is formed at the output of the comparison unit, since the codes in registers 40 and 41 do not match.  The trigger 29 is set to one state, and since, in the initial state, the signal on line 21 is equal, AND 33 is triggered.  At this point in time, as indicated in p. 2, the content of the counters 53 is O, therefore, the signal at the output of the element OR NOT 43 has a single value.  In the replay, the element 32 is triggered, the driver 37 and info Yau {aci from the bus 20 is loaded into the counters 53.  At the same time, the trigger 25 is set to the state corresponding to the absence of an interrupt (O on the inverse output), which ensures that the dogmatic unit at the output 21 is maintained regardless of whether or not the trigger 26.  Command 3, like the preceding ones, is a standard Register-Memory command and is similarly snapped out.  The address is determined by the decoder 24.  The signal from the output of the decoder is fed to the setup input of the trigger 26 and, passing through the circuit of the DA 38-19-1, is returned to the processor 1 as a response signal that the operation is completed.  The signal on pin 21 saves a single value.  4, Transfer control to the beginning of the work program.  The control is transferred to the first command of the working program, which is n (I have been recorded in memory 8 as nachaphg on.  Thus, the transition program ensures the synchronization of the mechanism for executing the working programs with the countertracking mechanism.  In the absence of external interruptions, the considered cycle of operation of device 2 is periodically repeated.  When choosing the initial xsmandy of the next linear section, the trigger 29 is set to unit, the AND 33 element is triggered, the trigger 26 receives information about the correct operation of the computer in the previous linear section, and the signal through circuit 32-37-49-23 selects the reference reference information from the bus 2O to counters 53, predetermined computer operation at the next linear section of the work program, and so on. d.  When a signal arrives on an external transponder on one of the bus lines 19, processor 1 terminates the execution of the current command and proceeds to perform the standard procedure for switching to a multimedia program.  This procedure is usually performed at the microprogram level and provides, in particular, forcing into memory (for example, in a hardware implemented stack) all the information necessary for the subsequent resumption of work on programs e from an interrupted place.  This information, in particular, includes the contents of the counters 53.   The counters 53 are programmed.  The reading from the counters is performed by accessing a certain address, which is determined by the decoder 24.  The signal from its output is fed to the input 44 of the block 23 and opens the transmitting elements 57 (FIG.  4), as a result of which information from the outputs 58 of the cells 56 enters the bus 18 and then into the processor 1.  The response to the completion of the operation is generated in a circuit; ZO-3819-1.  When the interrupting program is running, the same control hardware is used as when executing the original (working) program.  The exit from the interrupt program, as usual, is accompanied by the recovery of all necessary information, in particular the contents of the counters 53.  Information is written to the counters from the bus 18 when the control circuit 17-24-36-51 is triggered (FIG.  2) and further chains 67-63-61 or 65-62-61 (FIG.  4) depending on the value of the information bit on the corresponding line 59 of the bus 18.  Further control is transferred to the interrupted program.  When performing the standard procedures of the reduction-recovery, bus 19 appears to have extra pulses that are not taken into account by the reference code previously retrieved from memory 8 and placed in the counters 53.  However, it is in principle possible to introduce appropriate corrections when transferring code from the stack to counters 53, using ari ({the processor’s traditional device).  These corrections depend on the specific implementation of the computer and are inserted into the microprogram of the exit from the bank during its development.  When an error is detected, the trigger 25 is set to a state in which a natural unit is formed at its inverse output.  If this is the case, trigger 26 is in resolving, t. e.  in the unit state, then at the output of the NAND 35 element a logical nup signal is formed, the third front signal from this element enters processor 1 through line 21 and is perceived by it as a transmission signal from device 2, at the same time Well, the left signal on line 21 locks the element And 33 and block 23 (elements 54).  Therefore, the counters 53 store information on the state at the time of the unsuccessful test, which can be read on bus 18 and used to analyze the cause of the error.  Upon receiving the interrupt signal from device 2, processor 1 proceeds with the appropriate program.  This program may include, for example, invoking and executing diagnostic programs, attempting to re-execute a program section where an error has been registered, issuing messages to the controller, restarting the computer, or any other actions.  In the process of executing these programs, it is possible, if necessary, to divide the address spaces of blocks 6 and 8 again by switching trigger 73 along circuit 10-70-79-71-73, set the inhibit mask by switching trigger 26 along circuit 17-24- 31-26, or set the trigger 25 to the state corresponding to the absence of error by switching it along the circuit 17-24-25.  A return to an interrupted (due to an error) program may be performed starting at a certain repetition point marked as the beginning in memory 8.  The date of entry into this program can be used by a transition program.  The capacity of the counter 53 may be less than that which is necessary to register the total number of pulses.  Suppose, for example, the expected number of pulses is 10,1002 -2, and the size of the corresponding counter is four (and not five).  In this case, code 01002 4 is loaded into the counter (the older bit with weight 16 is lost).  After a 20-fold subtraction operation, the contents of the counter are 0000, while the Cttrwan loan is lost.  However, this does not lead to a significant reduction in the reliability of the test.  No errors are detected which result in the appearance on the corresponding interface line 3,36,52,63 and so on. d.  impulses instead of the expected 20, which is unlikely.  Operation of the device is explained in time.  Noah diagram (FIG.  7), on which plots 90-92 display the loading process (times 93 and 94) and the gradual reduction of the contents of the three counters 53. At times 93 and 94, the contents of all three counters 53 are zero, which corresponds to the correct operation of the computer.  In the time interval 93-94, one of the counters (plot 92) overflows twice, however, the source code loaded into it at time 93 is chosen so that by time 94 the content of this counter would be zero (modulo count).  Pulses 96 are generated on the synchronization trigger of trigger 25 at instants 93-95 of the output of the computer at the beginning of the linear sections, but after detecting an error (time 95) the formation of these pulses is stopped and the values are recorded in the counters at the time of the test.  When an error is detected, the signal on output 21 of device 2 (plot 97) takes a zero value.  From this it follows that during the time interval 94-95, the number of registered impunces on one of the control pins of the interface turned out to be different than predicted in the preliminary analysis of the programs (plot 9O does not touch the horizontal axis at time 95).  The use of the invention allows control of computer control buses as well as information address buses; provide a quick response to the error that has occurred (failure or failure; the response time does not exceed the machine’s execution time. diney part of the program); prevent the possibility of a controlled object crash due to the elimination of an uncontrolled computer wandering through the program as a result of an error (failure or failure).

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Claims (1)

DEVICE FOR CONTROL OF ELECTRONIC COMPUTER MACHINE, containing a block of counters, de. encoder, two triggers, two OR elements, two AND elements, AND element, OR HE element, two impulse drivers and a delay element whose input is connected to the output of the first OR element, and the output of the delay element is connected to the control input — the output of the device , the first input of the second OR element, the control input of the decoder and the group of counting inputs of the counter block, the input of the decoder is connected to. address input-output of the device, and the output of the decoder is connected to the input of the first OR element, the second input of the second OR element, the input of the first pulse shaper and the input of the output of information of the counter unit, the input of the prohibition of counting, the first and second inputs of receiving information, information inputs, a group of inputs outputs and outputs of the account block. cells are connected respectively with the outputs of the AND-NOT element, the second and first pulse shapers, the additional information input-output of the device, the information input-output-j of the device and the inputs of the ORILE element, the output of which is connected to the first input of the first AND element and the information input of the first trigger , the output of the second element And is connected to the second input of the first element And and the sync input of the first trigger, the installation input and inverse output of which are connected respectively to the output of the decoder and the first input for the INE element, the first and second inputs and the output of the second trigger are connected respectively to the outputs of the Decoder and the second OR element and the second input of the NAND element, the output of the first AND element is connected to the input of the second pulse shaper, and the output of the NAND element is connected to the first input the second element AND and the output of the device, characterized in that, with a chain for increasing the reliability of control, it contains the third, fourth and fifth triggers, the third element AND, the second delay element, two registers and a comparison circuit, the first and second inputs of which connected to the outputs of the first and second registers, respectively, info {> * the inputs of the first and second registers are connected respectively to the additional information input and output information input and output of the device, the sync inputs of the first and second registers, the third and fourth triggers and the installation inputs of the third , the fourth and fifth triggers are connected to the control input-output of the device, the information inputs of the third and fourth triggers are connected to the common bus of the device, the first and second inputs and outputs d and the third element are connected respectively to the outputs of the third and fourth flip-flops and s SU ... 1019451 101ύ4δι to the input of the second delay element, while the information ’· input, clock input and output of the fifth trigger are connected respectively to the outputs of the comparison circuit and the second delay element and the second input of the second element I.