SU1315981A1 - Versions of device for monitoring program execution - Google Patents

Abstract

The invention relates to digital computing and can be used to monitor the execution of programs in digital cleaning machines. The purpose of the invention is to increase the reliability of controls in ltg .15. . .. the progress of the programs. The device (variant 1) contains a block 23 of registers, a comparison circuit 24, a block 25 for extracting maximum and minimum number of pulses, a microprogram control block 26, a register 27, a fixed memory block 28, an AND 29 element, an OR 30 element, a trigger 31. Device (II c) contains registers, comparisons, block counters. microprogram control unit, permanent memory block, NAND element, OR elements, triggers, AND elements, NAND element, pulse formers, switch. The use of the invention makes it possible to control the control buses of a microcomputer or a programmable controller, as well as information and address buses, to provide a quick response to the error that has occurred, to prevent the possibility of an accident of the controlled object. 2 sec. f-ly, 18 silt. 4 tab. (L with: 4W

Description

The invention relates to digital computing technology and can be used to control the execution of programs in digital computers and programmable controllers, built on the principle of a common highway.

The purpose of the invention is to increase the reliability of control over the execution of programs.

Fig. 1 shows a functional diagram of the microcomputer, explaining the position of the proposed device in the structure of the microcomputer; 2 and 3, functional diagrams of the device for monitoring the execution of the programs in the first and second variants, respectively; Figures 4-6 are functional diagrams of blocks, respectively, of registers, firmware control, and allocation of the maximum and minimum number of pulses of the proposed device (option 1); Figures 7–9 are functional diagrams of blocks, respectively, of the firmware control of the counters and the switch of the device for monitoring the execution of programs (option 2); Fig. 10 is a functional diagram of the interface of the microcomputer; FIG. 11 is an example of the allocation of linear program sections; Fig. 12 is a timing diagram explaining the operation of a known device in the absence of failure; Fig. 13 is a timing diagram explaining the operation of a known device in the event of a malfunction of the microcomputer program counter; Fig. 14 is a fragment of a program illustrating a procedure for forming arrays of service information; 15-18 are timing diagrams explaining the operation of the proposed device.

The microcomputer (FIG. 1) contains a processor 1, a monitoring device 2, an interface unit 3, a memory unit 4 including memory data 5 and program memory 6. Blocks 3 and 4 are combined by the ping 7 group, which includes address .8, information 9, and control 10 tires. The processor 1 is connected to the interface 3 via a group of 11 buses, including address 12, information 13 and control 14, and also with device 2 for monitoring program execution through address 12 and control 14

five

0 5

five

bus, the address bus 12 is connected to the information input 15 of the device, and the control bus 14 includes recording and setup control lines connected respectively to the recording and setup 17 inputs of the device 2 to monitor the execution of programs, as well as the synchronization line connected to the input 18 of the device 2 synchronization (in the first embodiment), an interrupt acknowledgment line connected to the transition sign input 19, a group of mode setting lines connected to the group 20 of the settings of the mode 2 device 2 ( th embodiment) for controlling the execution of the program 21 whose output is connected to the input error interrupt processor 1 and the clock input 22 of the device 2 connected to the output clock signal of the processor 1.

The device 2 for monitoring the execution of programs in the first embodiment (FIG. 2) comprises a register unit 23, a comparison circuit 24, a maximum and a minimum number of pulses allocation unit 25, a firmware control unit 26, a register 27, a fixed memory unit 28, AND 29 , element ШШ 30 and trigger 31. The output 32 of the register unit 23 is connected to the first information input of the comparison circuit 24, the equality output of which is connected to the first 33 address input of the microprogram control unit 26, the input 16 of the device 2 is connected to the first input 34 of the block and 23 registers, information input 15 of device 2 is connected to information input 35 of register block 23, input 17 of initial installation of device 2 is connected to input of initial setting of register 27, block 28 of permanent memory, access input 36 of block 26 of microprogram control, input 37 of initial installation unit 25 of the allocation of the maximum and minimum number of pulses and the installation input to the O trigger 31, the inverse output of which is the output 21 of the error device 2, the synchronous input 18 of the device 2 is connected to the trigger synchronization input and 31, an information input of which is connected to zero potential bus, the output unit 28, the ROM connected to data vho3

register house 27, information input 38 of the block 25 for allocating the maximum and minimum number of pulses and the second information input of the comparison circuit 24, the output group of the minimum 39 and the maximum 40 number of clock pulses of the block

25 of the maximum and minimum number of pulses are connected respectively to the input groups of the element OR 30 and the element AND 29, the outputs of which are connected respectively to the second address input 41 of the program control block 26

and a single input of the trigger 31, the output of the OR element 30 is connected to the inlet 42 of the prohibition of the block 25 for allocating the maximum and minimum number of pulses, the clock input 22 of the device 2 is connected to the clock input 43 and 44 respectively of the block

26 microprogram control and block 25 for allocating maximum and minimum pulses, the output of register 27 is connected to the input of the higher bits of the address of block 28 of the permanent memory, the first 45, second 46, third 47 and quarter 48 of the microprogram control block 26 are connected respectively to the first 49 and the second 50 inputs of the record of block 25 for the maximum and minimum number of pulses, the record input for register a 27 and the low-order bit for the address of block 28 constant, the second record input 51 of register 23 is connected to m adshim discharge data output 48 the control unit 26 firmware.

The device 2 for monitoring the execution of programs in the second embodiment (FIG. 3) contains registers 52-54, a comparison circuit 55, a counter block 56, a firmware control block 57, a fixed memory block 58, an OR-NOT 59 element, OR elements 60-62 , triggers 63-65, elements AND 66-68, element I-HE 69, drivers 70 and 71 pulses and switch 72. Groups of outputs of registers 52 and 54 are connected respectively with the first and second groups of information inputs of the comparison circuit 55, input 16 of the device record 2 is connected to the input of the register entry 52, the information input 15 of the device 2 with single with information entry register

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52, the group of inputs 20 of the device mode 2 is connected to the group of counting inputs 73. block 56 meters, the input 17 of the initial installation of the device 2 is connected to the input of the installation O of the first trigger 64, the first input of the first element OR 61, the input 74 of the address unit 57 of the microprogram control and the input of the initial setting of register 53, the output of the first trigger 64 is connected to the first input of the first element AND 66 whose output is connected to the clock input of the second trigger 63, the output of the first

15 pulse generator 70 is connected to the record input 75 of the counter block 56, the output of the NAND element 68 is the output 21 of the device 2, the inverse and the direct outputs of the second 63 20 and the third 65 flip-flops are connected

respectively, the first and second inputs of the element AND-NOT 69, the output of the first element OR 61 is connected to the zero input of the second 63 and the single input

25 of the third 65 flip-flops, the first 76, the second 77, the third 78, the fourth 79, the fifth 80 and the sixth 81 outputs of the microprogram control block 57 are connected respectively to the input of the first

30 pulse generator 70, the information input of the second trigger 63, the record input of the second register 54, the first input of the second element AND 67, the control input 82 of the switch

35 72 and the input of the least significant bits of the address of the block 58 of the permanent memory, the output of the second element OR 60 is connected to the information input of the first 64 trigger, the input 83 of the prohibition of the account

40 of the counter block 56 and the first address input 84 of the microprogram control unit 57, the equality output of the comparison circuit 55 is connected to the second address input 85 of the microprogram 57 microprogram 45 and via the second pulse shaper 71 to the second input of the first And 66 element, clock. The input input 22 of the device 2 is connected to clock inputs 86 and 87, respectively, of the counter block 56 and the microprogram control block 57, the output of the third register 53 is connected to the input of the higher bits of the address of the fixed memory block 58, the output group

55 of which is connected to the group of information inputs 88 of the block 56 meters, the group of information inputs of the second register 54, the first 89 and the second 90 group 513

The information inputs of the switch 7, the output 91 of which is connected to the information input of the third register 53, the fourth output 79 of the microprogram control unit 57 is connected to the recording input of the third register 53, the inverse output of the third trigger 65 and the output of the first driver 70 of the pulses are connected respectively to the first and second inputs of the third element AND 68, the output of which is connected to the second input of the first element OR 61, input 19 of the transition flag of device 2 is connected to the zero input of the third trigger 65, the group of outputs 92 is minimal of the number of clock pulses, the group of outputs 93 of the difference between the maximum and minimum numbers of clock pulses and the group of informational outputs 94 of the block 56 of meters are connected respectively to the groups of inputs of the element WIT-NOT 59, the second 60 and third 62 elements OR, the output of the OR-NOT 59 is connected to clock input of the first 64 trigger, the output of the second element And 67 is connected to the single input of the second trigger 63.

The register block 23 (FIG. 4) of the device 2 for monitoring the execution of programs in the first embodiment (FIG. 2) contains registers 95 and 96, the information inputs of which are combined and are information input 35 of register 23, the recording entries of registers 95 and 96 are connected and are the first input 34 of the register 23, the outputs of registers 95 and 96 are combined and are the information output 32 of the register 23, and the inverse of the input of the register 95 is connected to the forward input of the register 96 and is the second input 51 of the block 23 registers.

The firmware control unit 26 (FIG. 5) of the device 2 in the first embodiment for monitoring the execution of the programs (FIG. 2) contains a register 97 and a permanent memory unit 98, the first, second and third outputs of which are connected respectively to the first, second and third information the inputs of the register 97, as well as are combined and are the fourth output 48 of the control control unit 26, the fourth information input and the synchronous input of the register 97 are the first address input 33 and the clock, respectively

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the input 43 of the firmware control block 26, the first, second, third and fourth outputs of the register. 97 are connected respectively to the first, second, third and fourth address inputs of the storage unit 98, the fifth address input and the access input of which are the second address input respectively.

: 41 and the inversion input 36 of the firmware control unit 26, and the fourth, fifth and sixth outputs of the storage unit 98 are respectively the first 45, the second 46 and

the third 47 outputs of the firmware control block 26.

Block 25 selection of the maximum and minimum number of pulses

(Fig. 6) devices 2 (option 1) for monitoring the execution of programs (Fig. 2) contain the first 99 and second 100 counters, the first 101 and the second 102 And elements, and the inverter 103. The first inputs

dy elements And 101 and 102 are connected

and are the clock input 44 of the block 25 for allocating the maximum and minimum number of pulses, the second input of the first element AND 101 is the input 42 of the prohibition of the block 25 for allocating the maximum and minimum number of pulses and connected through the inverter 103 to the second input of the second element AND 102, the outputs of the first

101 and second 102 elements And are connected to the counting inputs of the first 99 and second 100 counters, respectively, the information inputs of which are combined and are a group of information inputs 38 of the maximum and minimum pulses block 25, the control inputs of the parallel recording of the first 99 and second 100 counters respectively, the first 49 and second 50 inputs of the recording block 25 for allocating the maximum and minimum number of pulses, the installation inputs in the first 99 and second 100 counters are connected and are the input 37 of the initial installation of the allocation unit 25 of the maximum and minimum number of pulses, and the outputs of the first 99 and second 100 counters are respectively the output group 39 of the minimum number of clock pulses and the output group 40 of the maximum number of clock pulses

.7. 13

a maximum and minimum pulse allocation unit 25.

The firmware control block 57 (Fig. 7) of the device 2 for monitoring the execution of the programs in the second embodiment (Fig. 3) contains a register 104, a fixed memory block 105 and an AND element 106. The clock input 87 of the firmware control block 57 is connected to the synchronous input of the register 104 and the first input element And 106, - The first, second and third information inputs of the register 104 are connected respectively to the first, second and fourth outputs of the fixed memory unit 105, the third, fifth and seventh outputs of which are connected respectively to the third 78, second 77 and four volume 79 of the block 57 of the firmware control. The sixth output of the fixed memory unit 105 is connected to the second input of the AND element 106, the output of which is connected to the first output 76 of the microprogram control unit 57. The first and second outputs of register 104 are combined and connected to the sixth output 81 of the firmware control unit 57 and, respectively, the first and second address inputs of the permanent memory unit 105, the third and fourth address inputs and the access input of which are connected respectively to the second address input 85 of the block 57 of the firmware control, the fourth output of the register 104 and the access input of the firmware control block 57. The fourth information entry. and the third output of register 104 is connected respectively to the first address input 84 and to the fifth output 80 of the firmware control unit 57.

The counter block 56 (Fig. 8) of the device 2 for monitoring the execution of programs in the second embodiment (Fig. 3) contains a group of counters 107, elements 108 and 109 and inverter 110. first inputs of the first and second elements 108 and 109 are connected to a clock input 86 of the block 56 counters, the second input element And 108 is connected to the input 83 prohibiting the counting of the block 56 meters and through an inverter 110 with a second input element And 109. The outputs of the elements 108 and 109 are connected to the counting inputs of the first and second counters 107, the counting inputs of the third and subsequent counters 107 combined s and are

18

a group of counting inputs 73 of a block 56 counters; information inputs of counters 107 are combined and are a group of information inputs 88 of a block

56 counters. Recording input 75 of block 56 counters is connected to counter recording inputs 107. The outputs of the first and second counters 107 are, respectively, output groups of the difference between the maximum and minimum number of clock pulses 93 and the minimum number of clock pulses 92 of counter block 56, and the outputs of the third and subsequent counters 107 are combined and are a group of information outputs 94 of a block 56 of counters.

Switch 72 (FIG. 9) of device 2 for monitoring program execution

according to the second variant (fig. 3) it contains the first 111 and second 112 groups of elements AND, the element NAND (inverter) 113 and the group of elements OR 114. The first inputs of the elements 111 and 111 first

the groups are combined and are the first group 89 of information inputs switch 72, the second inputs of the elements 111 of the first group are connected to the control input 82 of the switch

72 and through an inverter 113 with the first inputs of elements AND 112 of the second group, the second inputs of which are combined and are the second group of information inputs 90 of the switch 72.

The outputs of the elements And 112 are connected respectively to the first, the inputs of the group of elements OR 114, the second inputs of which are connected respectively to the outputs of the elements And 111 of the first group. The outputs of the OR elements 114 are combined and are the output 91 of the switch 72.

The interface unit 3 (FIG. 10) of the microcomputer comprises transceivers.

.ments. D1THa bus address transfer

12 to bus B, elements 115 are used, the control inputs of which are combined and connected to line 116, which is part of bus 14. Depending on the value of the signal at the control input of element 115, it is either closed (high-impedance output state) or transmits a signal from the entrance to the exit. For bidirectional

data transfer between tires 9 and

13 are used in pairs the combined elements 115, the control inputs of which are connected to the inputs 117 and 118, which are part of the bus 14.

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Depending on the values of the signals at inputs 117 and 118, one direction of data transfer is chosen. For interfacing bus 10 with bus 14, elements of different types are used: cable amplifiers 119 (without control), elements 115, which are controlled via lines 120 and 121, as well as asynchronous self-controlled bidirectional elements 122, made on standard logic elements.

Any program recorded in machine codes in the microcomputer memory can be represented as a set of linear sections interconnected by conditional control transfer commands. The transition command is the terminating command of the linear section if it is not the last linear section of the program — in this case, the linear section can be completed, for example, the Stop command The initial command of the linear section can be either the command that is the external input of the program or the command to which control transfer of one of the transition command is performed by condition. If some program fragment (Fig. 11a) contains a linear section (t - I ,,, where 1 is conditional transition commands; t is other microcomputer commands) with several entry points (A and B), it can be represented as linear plots, each of which has one initial command (t, t., t), includes common fragment branch commands (t ,,, t.) and a common final

/

conditional jump command (Ij) (Fig.116).

Thus, any program can be divided into separate linear sections where the behavior of a computer is strictly determined in the sense that when the microcomputer is correctly passed through a given linear section of the program, a certain number (in a given interval T - T) of clock pulses and a strictly defined number of Tj, pulses on the interface control lines, which is known for each linear section even before the microcomputer begins its work on the program.

The presence of the interval T - T is explained by the wide use of the Waiting 110 mode in control micro computers.

The combination of interface control signals that accompany the execution of conditional jump instructions does not depend on whether the condition being checked is fulfilled or not.

Each linear section of the program has its own transition vector B {A |, A-J - a pair of addresses Aj, A: the initial commands of the linear sections to which control of the final command of the conditional transition of the linear section is transferred.

The basic idea of the operation of the device for monitoring the execution of microcomputer programs or a programmable controller can be expressed as follows.

After (or in the process of) translating the source program into machine command language, the work program is analyzed to identify all linear sections. The list of addresses of the initial commands of the linear sections is memorized.

For each linear section, the following is predicted): minimum T and maximum T numbers of clock pulses characterizing the passage of a given linear program section; the number of TO pulses on one or another control line, which is found by successively arithmetically adding some constants, each of which corresponds to its own command and depends on the design features of a particular microcomputer (for the second variant); the transition vector of this section, defining a pair of addresses A ,, A-, the appearance of which is expected at the moment of termination of the passage of this linear section of the Program.

This information is entered into a block of permanent memory, and later in the process of operation of the device, it is used to control the passage of the linear section upon reaching its beginning.

In addition, the work program was launched. The correctness of its implementation is controlled by special hardware. Simultaneously with the selection from the main memory of the initial command of a certain linear portion of the program, the service information is retrieved from the block of the permanent memory of the control unit for execution of the microcomputer program, which determines the expected minimum number T,

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pulses of pulses, the difference jT T of T between the maximum and minimum numbers of clock pulses, the number of 1d pulses on the interface control lines (for the second variant) and the vector B {A, AZ transition of this linear segment. Set T {t ,, 4Т; (T T, LT, Tr) will be called the characteristic set of the linear segment. This information is placed in counters, the contents of which are further reduced as you progress through this section of the program, i.e. as the transmission of pulse signals of clock and interface lines, mi. Upon the arrival of T clock pulses, the control device starts counting LT and checking for equality

the contents of the counters are zero. If this condition is fulfilled, i.e. the microcomputer reached the initial command of the new linear section, the transition vector and the current address A of the program are compared, and if the current address of the AI is equal to one of the expected addresses of A. or A, the vector B, the counters are loaded with new information corresponding to the new linear section of the program.

Then, the device 2 for monitoring the execution of the programs in the first embodiment (FIG. 2) sends an interrupt signal to the processor if, when receiving Tj clock pulses, the processor did not proceed to the execution of one of the linear sections whose starting addresses are specified in the transition vector of this section. The interrupt signal is analyzed by the processor and causes the transition to the previously scheduled control mode of the object connected to the microcomputer, after which the device 2 is reset and the microcomputer starts the program from the zero address.

In this case, the device 2 for monitoring the execution of programs (second variant, FIG. 3) sprinkles the interrupt signal into the processor if the following conditions are fulfilled: if, as a result of a failure or malfunction, the processor proceeds to the execution of the command whose address is specified in the transition vector of the linear section before receiving T pulses; if when receiving T. clock pulses processor

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did not proceed to the implementation of the next linear program section; if in the interval between T. and T pulses, the address of the initial command of the next linear program section was received and the contents of the counters TD did not reset.

The interrupt signal is analyzed by the processor and either causes a transition.

10 to a previously scheduled control mode of an object connected to the microcomputer, or the processor allows further operation and the self-synchronization of the monitoring device and

15 micro computers.

 Thus, the probability of emergency situations that may arise in the controlled object as a result of a random microcomputer wandering through the work program is significantly reduced, and conditional transfer control operators (erroneous transitions) may fail due to a crash,

5 The operation of the known device in the absence and with the occurrence of the indicated failures is explained by the timing diagrams (Figs 12 and 13, respectively).

0 Plots 123-125 (Fig. 12) show the loading process (time 126) and the gradual reduction of the contents of the three counters. The impulse 127 is formed at the time when the contents of the program memory cell and the additional memory unit cell are not coincidental.

When an error is detected, the signal at the output of the device takes a zero

0 value (plot 128).

Plots 123-125 (Fig. 13) also show the loading process (time 126) and the gradual reduction of the contents of the three counters. Before Pred5, we assume that at times 129, the unexpected program changed its course twice and performed erroneous Transitions to the subsequent linear sections, the initial mine the commands of these sections due to interference (plot 130). In this case, no pulses 127 are formed in the known device (shown by dotted lines) at times 131 of the expected completion of the linear sections. During the time interval 126-132, one of the counters (plot 123) overflows three times, and the other two (schedules 124 and 125) twice.

131

A mismatch pulse 127 and an interrupt signal (plot 133) are generated only at time 132 when the computer arrives at the beginning of the fourth (since time 126) line segment. From this. It follows that the time between the occurrence of a fault leading to the initial vertex of the next linear section and its detection in a known device may exceed the time of the linear section in the event of the accumulation of such faults associated with industrial disturbances. large (commensurate with the time of the operation of the executive mechanism for controlling an object).

As a result of failures in the software counter, the communication line, the matching unit, etc. the processor instead of the next command of the linear section of the program can proceed to the execution of the erroneous stop command. In this case, in the known device, the formation of pulses 127 is stopped and the interrupt signal is not received by the processor in the future, which is unacceptable in a number of cases.

The time between the occurrence of a fault and its detection in the proposed device does not exceed the duration of the passage of the linear section of the program, which allows you to organize a timely response of the control device in case of an emergency.

Memory 6 of a microcomputer program is usually executed in the form of a permanent or semi-permanent memory device. The program entered into memory 6 is represented as a sequence of machine codes. Its entry into the memory 6 must be accompanied by the input of a previously prepared array of auxiliary information in block 28 (58) of the permanent memory of the device 2 to monitor the execution of micro-computer programs.

The procedure for preparing the auxiliary information array is performed as follows.

The work program listed in memory 6 of the microcomputer is converted, the linear sections are selected, as shown in Fig. 11 a, b, and the characteristic sets T fT, LT, (T T, LT, T) are determined for each linear section obtained. FIG. 14 shows an example of a fragment of pro598114

grams divided into linear sections of L ..

In this case, it is necessary to enter in the block 28 of the permanent memory of the device 2 for

5, the program execution control (the first version, FIG. 2) auxiliary information about the linear section of the work program, information about any linear section L. to be placed in eight cells of the permanent memory block 28 (Table 1), and in the cells with addresses in and in + 1 enter the first address A, - the transition vector, i.e. respectively junior AJ and senior

15 addresses A; the initial command of the first of the two linear sections to which control of the final command J of the linear section is transferred. In cells with addresses in + 2 and

0 B + 3 introduces the second address A. of the transition vector, i.e. respectively, the younger A and the older A j of address A; the initial command of the second of the two linear sections to which

5, control of the terminating command J of the linear portion is transferred. The cells with addresses B + 3 and B ° + 5 are entered, respectively, with the addresses of two cells of the fixed memory block 28, in which the first elements of the auxiliary information of the linear information are stored: the sections to which command J is transmitted (B

  Cd B °; AT; In °; AT

AT

f

35 V B-,; °, etc.). The expected minimum number T of clock impulses is entered into the cell with address B + 6, and the difference between 4T T - T between the maximum and minimum numbers of clock pulses for a given linear section Lj is entered into the cell with address B + 7.

In the first eight cells of the block 28 of the permanent memory, the service

5 information serving to reset the device 2 to monitor the execution of programs. In the first and second pairs of cells, the starting address A of the program is entered so that

0 that in the first cell of each pair it is possible to arrange the younger part of A, and in the second - the older part of A. starting address A of the program. In the fifth and sixth cells enter the address

5 The cells 28 of the permanent memory storing the first element of the auxiliary information array of the initial linear portion of the program. In the seventh and eighth cells of the block 28 to 15131

The storable memory is inputted respectively by the set numbers of the pulses T, p 0 and 4 Tr O. This is necessary to ensure the initial synchronization of the control device 2 with the operation of the microcomputer.

The block 98 of the permanent memory of the microprogram control unit 26 is programmed in accordance with Table 2.

In addition, auxiliary information about linear sections of the work program is inputted into block 58 of the permanent memory of device 2 for monitoring microcomputers (second variant, FIG. 3). Information about any linear section is located in the four cells of the fixed memory block 58 (Table 3), while the transition vector is entered into the cells with the addresses B ° and in + 1, i.e. respectively, the addresses of the two initial commands of the linear sections to which control of the terminating command J of the linear section is transferred. In the cell with the address B ° + 2, the addresses of the two cells of the fixed memory block 58 are inserted, in which the first elements of the auxiliary information arrays of the linear sections to which the command J is transmitted are stored (BP, B in | B, etc.) ). In the cell with the address B + 3, the characteristic set T {T, LT, Te J of this linear section L is entered.

In the first cells of the cell of the fixed memory unit 58, the service information is entered, which serves to reset the device 2 to monitor the execution of the micro-computer programs. The first and second cells are entered with the start address of program A, the third cell is the double address of the cell (Bj,) that stores the first element of the auxiliary information array of the initial linear section LJ of the program, and the fourth cell is the installation characteristic set T {T, 0; LT, F 0; Tgj, 0} This is necessary to ensure the initial synchronization of the device 2 of the control of program execution with the operation of the microcomputer.

The block 105 of the permanent memory of the block 57 of the firmware control is programmed in accordance with Table 4.

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The device 2 for monitoring the execution of the programs in the first embodiment (FIG. 2) works as follows. Microcomputer is given in the original

state by filing a logic. 1 in line A general reset included in tires 10 and 14. A signal on this line is generated automatically after power is turned on or, for example,

appears as a result of pressing the corresponding button on the control panel.

Signal master reset returns to the initial state the processor 1 and the control part of the memory 5 and 6, and

also arrives at the input 17 of the initial installation of the device 2, prepares the interrupt signal from the device 2 to the processor 1 via the line

21 in the event of a failure, sets up device 2 so that the first address of the first linear section of the program corresponds to the cell address of the fixed memory unit 28,

storing service information about the first linear segment.

An interrupt signal is prepared as follows. Signal General Reset Received

bus 14 (figure 2) to the input 17 of the initial installation of the device 2 and further to the input of the installation in the On trigger 31. The signal at the inverse output of the trigger 31 takes the value of logic 1 and arrives at the output 21

device 2 for monitoring program execution. This state corresponds to no interrupt.

Configuring device 2 to monitor the execution of programs for matching the addresses of memory 6 of the microcomputer and block 28 of the permanent memory is performed when a signal is received General reset from bus 14 to input 17 to start the installation of device 2 and then to the input of the initial installation register 27, as a result of which the signals at the outputs of this register take on zero values. These signals are input to the higher bits of the address of block 28 of the permanent memory. At the same time, the signal General reset goes from input 17 of device 2 to input 36 of the initial installation of the firmware control block 26 and then to the input of the access of the permanent memory block 98 (Fig. 5) As a result of the signal of a general reset on all the outputs of the permanent memory block 98 set to high impedance state. This condition on the output lines of block 98 is perceived at the inputs of the associated elements as a logical 1 signal.

On the information input 15 of device 2, processor 1 sets the starting address of the work program. If there is a tracking signal along the 16-ZA circuit to the synchronous inputs of registers 95 and 96, the younger A. and the older A parts of the current address are stored in these registers, respectively. The high impedance state of the control input 51 of register register 23 is perceived at the forward input of register 96 as a logical 1 signal (Fig. 4), and the older part A of the initial address of the program comes from information output 32 of block 23 registers to the first input of the comparison circuit 24.

Signal General reset comes from bus 14 to input 17 of the initial installation of device 2 and further to the input of the initial installation of the fixed memory unit 28, and at its outputs a high-impedance state is set, which is perceived at the second input of the comparison circuit 24 as a number all units. In this case, the signal at the output of the comparison circuit 24 assumes the value of logical 1, since the codes at the inputs of the comparison circuit 24 do not match. This signal is fed to the input 33 of the firmware control unit 26 and then to the fourth input of the register 97. The initial state (1111) registers 97 with a processor .1 clock signal through circuit 22-43-26 (FIG. 2) and then register synchronous input 97 (FIG. 5), as a result of which the signals at the first, second, third and fourth outputs of this register accept a single value and arrive at the first, second, third and fourth address inputs of the permanent memory unit 98, respectively. At the same time, the high-impedance state of the first, second, and third outputs of the storage unit 98 (output 48 of the microprogram control unit 26) is perceived at the input of the lower bits of the address of the storage unit 28 as logical signals 1. The general reset signal comes from input 17 of the initial Installing device 2 at the input of block 28 of the permanent memory and prohibits the entry of the contents of the cell of block 28 of the permanent memory with address 00-0111 (BO + 7) (Table 1) to its output until the signal is complete. General reset.

In addition, the signal General reset comes from the input 17 of the initial installation to the input 37 of the initial installation of the block 25 for allocating the maximum and minimum number of pulses and then to the inputs of the installation in O of the first 99 and second 100 counters (Fig. 6). Counters 99 and 100 are set to zero and the signals at the outputs of output group 39 and 40 are zero. As a result, the effect of zero signals. Coming from the group of outputs 40 of the block 25 for allocating the maximum and minimum number of pulses, respectively, to the inputs of the group of inputs of the element AND 29, the signal on the code of this element also takes a zero value and is set at the input of the installation to 1 trigger 31 (FIG. 2)

As a result of zero signals from the outputs of the group of outputs 39 of the minimum and maximum number of pulses 25, respectively, to the inputs of the inputs of the element OR 30, the signal at the output of this element also takes a zero value. This signal is fed to the inhibitor input 42 of the minimum 25 and the maximum number of pulses and then to the second input of the AND 101 element (Fig. 6), prohibiting the passage of clock signals along the circuit 22-44-101- -99 to the counting input in the subtraction mode -1 counter 99. Simultaneously, si Logical O from input 42 of the Preta unit 25 for allocating the minimum and maximum number of pulses is fed through the inverter 103 to the second input of the element I 102, allowing the passage of clock signals through circuit 22-44-102-100 to the counting input in the summation mode +1 counter 100 .

The zero signal from the output of the element OR 30 is fed to the input 41 of the microprogram control unit 26 and then to the fifth address input of the permanent memory unit 98.

After termination of the signal General reset processor 1 automatically or at the initiative of the operator proceeds to

1913

In the highlight of the work program recorded in the permanent memory 6 microcomputers. At the same time, the counter 100 of the block 25, in which the minimum and maximum number of pulses are located, starts counting the clock pulses arriving along the circuit 22-44-102-100. Simultaneously, the removal of a signal. A general reset allows access to the permanent storage unit 98, and the contents of the cell with the address 01111 is set at its corresponding outputs (Table 2, line 32).

Zero signals from the first, second and third outputs of the storage unit 98 are fed to the output 48 of the microprogram control unit 26 and further along the low-order bits of the address bus to the inputs of the lower-order bits of the address of the fixed memory unit 28. Thus, at the address inputs of the fixed memory unit 28, an address of 00-000 is set (BP (table O. Together with signal removal) A general reset at the access input of the fixed memory unit 28 from its outputs to the second input of the comparison circuit 24 The lower part of the expected address word (Table 1). At the same time, the zero signal from the low-bit line of the information output 48 of the microprogram control block 26 goes to the control input S1 of the register block 23 and then to the reverse inversion input of the register 95, resulting in the lower part A nach the program's address from the outputs of register 95 enters output 32 of register block 23 and then to the first input of comparison circuit 24. As a result of coincidence of the expected A. and actual A. of the lower parts of the initial address of the program, the output of the comparison circuit 24 takes the value A. This signal is fed to the input 33 of the firmware control unit 26 and then to the fourth information input register E97, the first, second and third information inputs of which receive signals 000 from the first, second and third outputs of the unit 98 of the permanent memory (Table 2, line 32). The clock signal, the inputs from the circuit 22-43 to the clock input of the microprogram control unit 26 and further to the synchronous input of the register 97, records the information word 0000 in this pe120

gistr. Thus, on the first, second, third, and fourth address inputs of the storage unit 98, zero signals are set, and since there is a zero signal on the fifth address input, the signals on the outputs of the permanent storage unit 97 are set to line 17 of table 2 (the contents of the memory cell with the address 00000).

A single signal from the first and zero from the second and third outputs of the fixed memory block 97 is outputted to the output 48 of the microprogram control unit 26 and then to the input of the address bits of the fixed memory unit 28, resulting in the address 00- 001 (B + 1) and from its outputs, the second part of the expected address word A:,. (tab. 1). At the same time, a single signal from the low-bit line of the information output 48 of the microprogram control unit 26 is fed to the input 51 of the register block 23 and then to the direct input of register 96, resulting in the high-end AIJ. The initial address of the program from the outputs of register 96 is fed to the output 32 of the block 23 of registers and then to the first input of the comparison circuit 24. The zero signal of the comparison of the expected A and real A of the senior parts of the initial address of the program from the output of the comparison circuit 24 is fed to the input 33 of the microprogram control block 26 and then to the fourth information input of the register 97, the first, second and third information inputs of which receive signals 1, О O from the first, second and third outputs of the block 98 of the permanent memory (line 17, Table 2). The next clock signal arriving at the synchronous input of the register 97 records the information word 0001 in this register, the address input unit 98 constant memory address 00001 is set, whereby at the outputs of this block ustanavlivalyuts signal values corresponding to row 18 Table 2.

Zero signals from the first and second and single signals from the third outputs of the block 98 of the storage memory 211

are input to the lower bits of the address of the block 28 of the permanent memory - (address 00-100 (B + 4), from the outputs of which the information input of the register 27 receives the information word B, - the address in the block 28 is permanent memory of the service information array for the first linear section of the work program (Table 1). Simultaneously from the sixth output of the constant memory unit 98 (output 47 of the microprogram control unit 26) the input of the register entry 27 receives a single signal, the output of which; in this register. Address from the outputs of the register 27 post falls to the input of the higher bits of the address of the block 28 of the permanent memory.

In addition, a single signal from the first and zero from the second and third outputs of the storage unit 98 goes to the first, second, and third information inputs of register 97, respectively. The next clock signal arriving at the sync input records the information word 0100 into this a register, and address 00100 is set at the address inputs of the storage unit 98, with the result that the values of the signals corresponding to row 21 of table 2 are set at the outputs of this block. The zero signal from the first and single from the second and third outputs of the block 98 of the memory is fed to the input of the lower bits of the address of the block 28 of the permanent memory - the address (V ° 6), from the output of which to the information input 38 of the block 25 The maximum number of pulses is received by the code of the number T of pulses of the first linear section (Table 1). Simultaneously, from the fourth output of the block 98 of the permanent memory, a circuit 45–49 sends the first input to the record 99 of the block 25 and the minimum and maximum number of pulses, the zero signal arrives, and the code T is stored in the counter 99, from the outputs of which this code goes to the output group 39 of block 25 for allocating the minimum and maximum number of pulses and then to the input group of the element OR 30. The signal at the input of the element OR 30 takes a single value if T ,, O and saves the zero value to the opposite

598122

case. The next clock signal in the register 97 is recorded information word 0110.

If Tx | O, the value of the signal at the 5th input of the storage unit 98 and the prohibition input 42 of the counting unit 25 for the minimum and maximum number of pulses does not change. At the same time, address 00110 is set at the address inputs of the storage unit 98 and the signals at its outputs take the values in accordance with line 23 of Table 2, and the counter 100 of the unit 25 for the maximum and minimum number of pulses continues to count clock pulses.

At T, at address inputs

20, a fixed-memory block 98 sets address 10110 and signals to. its outputs take values in accordance with row 7 of Table 2, and the single value of the input signal

25 42 prohibitions of the block 25 for allocating the minimum and maximum number of pulses to the input of the AND 101 element and through the inverter 103 to the input of the AND 102 element, respectively

30 unlocking element AND 101 for passing the clock signals from input 44 of block 25 selecting the minimum and maximum number of pulses to the counting input in the subtraction mode of the counter 99 and locking the element AND 102 to passing the clock signals to the counting input in the adding mode of the counter 100 (FIG. 6).

Single values of signals with

40 of the first, second and third outputs of the storage unit 98 are input to the lower bits of the address of the storage unit 28 — an address (+ 7), from the outputs of which to the information input 38 of the minimum and maximum the number of pulses comes in the additional code the number T of pulses of the first linear section

50 (table 1). Simultaneously from the fifth output of the storage unit 98 via the circuit 46-50 to the second input of the record of the counter 100 of the unit 25 for allocating the minimum and maximum quantities

The 55 pulses receive a zero signal, and the dT code is stored in the counter 100. For the correct operation of the device 2 to monitor the execution of the programs (Fig. 2) the number of pulses for each

The second linear section is selected from the conditions T, where n is the width of the counter 100. The signal at the output of the element I 29 after setting the output 40 of the block 25 for separating the minimum and maximum number of pulses of the additional code of the number L T, the pulses remain zero, and trigger 31 is unchanged.

After loading in block 25 the allocation of the minimum and maximum number of pulses of the number LT, device 2 begins to compare the current addresses of program A with the transition vector of the linear section. The comparison is done as follows. When the next clock pulse arrives at the synchronous input of the register 97 of the microprogram control block 26, the information word X111 is stored in the register, and the address inputs of the fixed memory block 98 establish T O (the counter 99 of the block 25 for allocating the minimum and maximum number of pulses will be set to O by the arrival its counting input in T clock pulse subtraction mode). When T o from the output of the element OR 30, the input 41 of the microprogram control unit 26 and then the fifth address input of the permanent memory unit 98 receives a zero signal, and on the codes of this block, the values of the signals are set in accordance with line 17 of Table 2. At the same time, the zero signal from the output leads to the address ХХ111 of one of the four

its cells (Table 2, lines 8, 16, 24 ,, 25mentand OR 30 are fed to the input 42

32) depending on the state of the output-prohibition of the account of the block 25 of the blasts of minids of the comparison circuit 24 and the minimum and maximum amounts

OR 30. In this case, the zero values of the pulses and sets this block

signals from the output 48 of the block 26 micro-in LT counting mode (opens the element

30 and 103 for passing the clock signal-program control is fed to the input of the lower bits of the address of the block 28 of the permanent memory (the address BP, from the outputs of which to the second input of the comparison circuit 24 goes below

catch on the counting input in the mode of summing the counter 100 and closes the element And 101). After fulfilling the conditions, output 0c 48

part A

the first expected address 35 of the firmware control unit 26 of the linear section L. At the same time, a single signal from the first output of the storage unit 98 of the microprogram control unit 26 is fed to the control input 51 of the register block and then to the direct input of register 96, from the outputs of which to the output 32 of the register block and further to the first input of the comparison circuit 24 the younger part of A arrives, the exact way the value of A of the current address, recorded in this older part of the current address, arrives. The next control signal is received by the control signal from the input 16. write to input 34 of the record block 23 of registers.

If A {. A, - ", the signal at the output 50 at the address inputs of the block 98 of the constant-comparison circuit 24 receives a zero memory at A A, - set value. This signal is sent to address 00001 and the outputs 33 of block 26 of the microprogram block are set to control values and then to the fourth input of signals in accordance with the register line 97. The next clock signal is 55 18 table 2. On this cycle of control of the line, the information word 001 and the value of Aj (the most significant part of the first expected 40 address of the transition vector of the linear section L from the cell 28 of the permanent memory with the address B + 1 is fed to the second input of the comparison circuit 24, to the first input of which the analogue clock signal on the synchronization 43 of the register 97 writes the information word 0001 into this register,

the information word 0000 is entered into register 97, and the address of one of the two

- but

131598124

its cells XOOOO (Table 2, lines 1 and 17) depending on the state of the output of the element OR 30. If T, O, the address inputs of the permanent memory block 98 are address 10,000 and the outputs of the signals are set to with line 1 of table 2. Subsequently, the output states of the firmware control unit 26 are not changed until the execution of the operation.

five

0

catch T o (counter 99 of block 25 for allocating the minimum and maximum number of pulses will be set to 0 upon arrival at its counting input in the subtraction mode T clock pulses). At T o from the output of the element OR 30 to the input 41 of the microprogram control unit 26 and then to the fifth address input of the permanent memory unit 98 a zero signal is received, and the signals of this block are set to the values of the signals in accordance with line 17 of table 2. At the same time, the zero signal from the output of the cell to the counting input is in the mode of summing up the counter 100 and closes the element AND 101). After fulfilling the conditions, output 0c 48

35 of the firmware control block 26, the value A of the most significant part of the current address enters 45 in the most thorough way. Oche-

The information word 001 and the value Aj (the upper part of the first expected 40 address of the transition vector of the linear segment L from the cell 28 of the fixed memory 28 with the address B + 1) are fed to the input of the lower bits of the address of the block 28 of the permanent memory. the second input of the comparison circuit 24, at the first input of which the analog block of the firmware microprogrammed control path enters the value A of the highest part of the current address.

the red clock signal on the synchronization register 43 registers 97 writes into this register the information word 0001,

line segment L is terminated and B is loaded into register 27 to control the linear segment Li ..251

If A is A. or. A, -p, in a similar way, in accordance with Table 2, conditions A and A are checked (./s and P of these conditions are loaded into B ° in register 27 to control the linear portion L.

Thus, if the microcomputer program is correctly executed at the beginning of each successive linear section, block 25 is used to allocate the minimum and maximum number of pulses with corresponding values of T and L T and the counter 100 of the block 25 for selecting the minimum and maximum number of pulses will never be set to All Units . If, on receipt of Tj clock pulses, the conditions A A ,. and A A, (A. Aj.), i.e. as a result of a failure or malfunction, processor 1 proceeded to execute a command with an arbitrary address, mine address A- (And the signal at the output of element 29 takes a single value. This signal enters the input of the installation in 1 trigger 31, and it goes into one state. The zero signal from the inverse output of this trigger enters the output 21 of the program control unit 2 as a signal. Interrupt request. After processing the interrupt on the microcomputer, the control device 2 is reset to the initial state using the described method computer starts execution of the work program to address zero.

The operation of the device 2 (Fig. 2) is explained by the time diagram (Fig. 15) representing the loading process (time 134) and gradually reducing the contents of the counters T (plot 135) and lT (plot 136) and generating comparison signals 137 and interrupting signals 138 in case of a failure 139.

At time 140, the current address of program A and one of the expected addresses AJ (or A.) coincide. The coincidence pulses 137 are formed at the input 33 of the microprogram control unit 26 at the moments of the transition of the microcomputer to the beginning of the next linear section. The content of the counter zT remains non-zero and the signal at the input of the installation

126

in 1 flip-flop 31 saves zero value. If, as a result of a disturbance (conditionally represented by a pulse 139), leading to the execution of an erroneous transition within the linear section of the program (or to another linear section of the program), the current address A is compared. and one of the expected addresses A. will not occur at the planned time of 141 time, but at time 142 (not shown) until the counter is zeroed, i.e. at time 143 (not shown) after the AT counter overflows, at time 144 the pulse counter 100 overflows T, the output 21 of the device 2 (plot 138) takes a zero value.

The plots in Fig. 15 indicate that the time between the occurrence of a fault and its detection in the intended device does not exceed the duration

the passage of the linear section

program that allows you to organize a timely response of the control device in case of emergency. The device 2 for controlling the microcomputer according to the second variant (FIG. 3) is working

in the following way.

The computer is reset to its original state by supplying a logical 1 to the line General reset, which is part of the tires 10 and 14.

The signal on this line is formed automatically after the power is turned on or, for example, appears as a result of pressing the corresponding button on the control panel.

The master reset signal initializes processor 1 and the control part of memory 5 and 6, and also prepares the interrupt signal from device 2 to processor 1 via line 21 when a failure is detected, and sets up device 2 so that the first address of the first linear section the program corresponds to the cell address of the fixed memory block 58, which stores the characteristic set of this region.

An interrupt signal is prepared as follows.

The signal General reset comes from the bus 14 (fig.Z) to the input 17 of the initial installation of the device 2, and then to the input of the element OR 61, as you, 271315981

course - to the inputs of the installation in a single

the state of flip-flops 63 and 65. A single signal from the direct output of flip-flop 65 unlocks the IS-NE element 69, as a result of which the zero signal from the inverse output of flip-flop 63 is fed to the first input of the IS-NE 69 element, the output signal of which 21 takes . This state corresponds to no interrupt.

va T from information input 88 to counters 107. The values of T 0 AT (j 1 O and T 0 come from the outputs of the first, second and subsequent counters 107, respectively, to outputs 93, 92 and 94 and further to the groups of inputs of the elements OR 60, OR- NOT 59 and OR 62. At the output of the element OR 60, a zero value is set, which is present at the information input of the trigger 64, the inhibit input of the counter 83 of the counter block 56, and the First address input 84 of the firmware control 57

Configuring device 2 for monitoring the matching of memory addresses 6

microcomputer and block 58 of the permanent memory. At the exit of the element OR-NOT 59, this is done when the signal is received. The signal is set to zero. A general reset from the bus 14 to the input of the signal that goes to the counting

trigger input 64. At the output of the OR 62 element, a zero 20 value of the signal is set, which is present at the second input of the AND 67 element and

17 of the initial installation of the device 2 and further to the reset input of the register 53, as a result of which the signals at the outputs of this register assume zero values. These signals are input to the higher bits of the address of block 58 of the permanent memory. At the same time, the signal General reset is fed to the input 74 of the firmware control unit 57 and then to the access input of the permanent memory unit 105 (Fig. 7). As a result, Signal Exposure Signal

locks it to pass the reset signal of flip-flop 63 from the seventh output 79 of the fixed memory block 105 - 25 ti along the circuit 79-67-63 (FIG. 3). . After the termination of the signal General reset, the processor 1 automatically or at the initiative of the operator proceeds to the execution of the work program, recording the reset on all outputs of the block 105 in the permanent memory 6 of the microcomputer. . The high-impedance state is set to the memory. This state on the output lines of the storage unit 105 is sensed on

the inputs of the elements associated with them as p is stored in register 52 and the signal is logical 1. "Recording from its output to the first input of the initial state of the horn 104 is produced by the clock signal of processor 1 through circuit 22-87-57 (FIG. 3) and further on, the register 104 (Fig.7), as a result, the signals on the first and second inputs of this register take on a single value. These signals are received via line 81 to the input of the low-order bits of the address of block 58 of the permanent memory. The contents of the cell block 58 constant memory

At information input 15 of device 2, processor 1 sets the start address of the work program. If there is a tracking signal, this

comparison circuits 55. When the power is turned on, the register 54 is set to an arbitrary state and from its output to the first input of the comparison circuit 55 a random expected address is received. At the output of the comparison circuit 55, a single signal is set if the state of the register 54 coincides with the starting address and zero - otherwise. This corresponds to the undefined value of the signal at the second address input 85 of block 57 of the firmware

with the address 00-001 (B +2) (Table 3)

address At the output of the comparison circuit 55, a single signal is set if the state of the register 54 coincides with the starting address and zero - otherwise. This corresponds to the undefined value of the signal at the second address input 85 of block 57 of the firmware

arrives at information input 88

block 56 counters. The signal from the sixth control and at the third address input of the fixed memory unit 105 of the fixed memory unit 105. Thus (FIG. 7) is fed to the second input in an elec- tronic way, according to the initial mentor And 106, and opens it to by installing permanent memory at the address inputs of the signal walker along circuit 22-87-57 105

(fig.Z), 87-106-76 (fig.7), 76-70-7555 address 0X11. Disconnect Signal

(FIG. 3) to the input 75 of the recording of the block 56 of the counters and further to the inputs of the recording of the counters 107 (FIG. 8), which causes the recording of the characteristic reset corresponds to a reference to the permanent memory unit 105. The signals at its outputs take the values in accordance with rows 4 or 8 of table 4.

28

va T from information input 88 to counters 107. The values of T 0 AT (j 1 O and T 0 come from the outputs of the first, second and subsequent counters 107, respectively, to outputs 93, 92 and 94 and further to the groups of inputs of the elements OR 60, OR- NOT 59 and OR 62. At the output of the element OR 60, a zero value is set, which is present at the information input of the trigger 64, the inhibit input of the counter 83 of the counter block 56, and the First address input 84 of the firmware control 57

neither. at the output of the element or-NOT 59, the zero value of the signal is set, which goes to the counting

. After the termination of the signal General reset, processor 1 automatically or at the initiative of the operator proceeds to the execution of the work program recorded in the permanent memory 6 of the microcomputer.

At information input 15 of device 2, processor 1 sets the start address of the work program. If there is a tracking signal, this

p is stored in register 52 and from its output goes to the first input

comparison circuits 55. When the power is turned on, the register 54 is set to an arbitrary state, and from its output to the first input of the comparison circuit 55, an arbitrary expectation p is received and stored in the register 52 and from its output it goes to the first input

address At the output of the comparison circuit 55, a single signal is set if the state of the register 5-country 54 coincides with the starting address and zero - otherwise. This corresponds to the undefined value of the signal at the second address input 85 of block 57 of the firmware

address 0X11. Disconnect Signal

a reset corresponds to a reference to the permanent memory unit 105. The signals at its outputs take the values in accordance with rows 4 or 8 of table 4.

2913

A single signal from the sixth output of the ndCTOHHHofl memory unit 105 unlocks the AND element 106 and the clock signal is fed through the circuit 22-87-106-76-70-75 to the input 39 of the information recording unit 56 of the counters. The characteristic set T is repeated to be recorded in block 56 of the counters.

The first clock signal on the circuit 22-83-104 records in the register 10A information word 0X00. At the address inputs of the permanent memory unit 105, the address 0X00 is formed, and the signals at its outputs take on values in accordance with rows 1 or 5 of Table 4.

The information word 00 from the output 81 of the firmware control unit 57 is inputted to the low-order bits of the address of the fixed memory unit 58, and at its outputs the contents of the first (V °) cell A, the Awarded address A is fed to the information inputs of the register 54 and stored in when a single signal is received from the third output 78 of the block 105 of the permanent memory to the input of the record of this register. At the output of the comparison circuit 55, a zero value is set for the signal about the coincidence of the current address A, and the expected one. This signal goes through the circuit 55-85 to the second address input 8 of the microprogram control unit 57 and then to the third input of the permanent memory unit 105. Thus, regardless of the initial state of the register 54, before the arrival of the second clock signal, the address 0000 is set at the inputs of the permanent memory unit 105 and the signals at its outputs take the values corresponding to row 1. table, 4. A single signal from the output 77 of the microprogram control unit 57 is fed to the information input of the trigger 63 and, in the event of a change in the signal at its synchronization, confirms the single state of the absence of an interrupt.

Upon receipt of the second clock signal, the information word 0110 is stored in the register 104. The unit value of the signal from the third output 80 of the register 104 arrives at the control input 82 of the switch 72 and connects the first group of inputs 89 to its outputs 91, simultaneously the information word 10 from the output 81 of the block

130

The microprogram control is fed to the input of the lower bits of the address of the block 58 of the permanent memory, and the contents appear on its outputs

the third BS + 2 cells B,,, the first part of this information word comes from the outputs of the block

58 memory on the first group of 89 inputs of the switch 72 and its

the outputs to the information inputs of the register 53, At the inputs of the block 105 of the permanent memory of the block 57 of the firmware control, address 0010 is set, and the signals at its outputs take the values corresponding to row 3 of the tabl, 4. A single signal from the output 79 of the firmware control unit 57 is input to the register entry 53, and the information word B is stored in the register — the address of the service information array for the first linear section L of the programs,. Upon receipt of the third clock signal, the information word 0X11 is stored in the register 104, the address is set at the address inputs of the permanent memory block 105 of the microprogram control block 57

0011 and the signals at its outputs take the values indicated in line 4 of Table 4, as a result of which the contents of the T cell B + 3 blocks 58 of the permanent memory (tab. 3) are loaded into the block

56 counters.

The code of the T and Td elements of the characteristic set is knocked out so that by the moment of selecting the 6 micro-computers of the command with address A from the memory

or A, the contents of the first, third, and subsequent counters 107 operating in subtraction mode (counting the signals at the clock input 22 and the lines x 20 of the bus 14), was zero.

Code 4 T is selected from the ratio DT DT, where T "is the total number of clock cycles in the linear region during which processor 1 is in standby mode during operation

with external devices. As a pulse on the interface control lines, write control signals to a storage device (memory) can be used, reading from

Memory, input of information from external devices, output to external devices, as well as control signals for arithmetic logic unit

311

when performing a particular operation (or group of operations). The number of such signals depends only on the number of corresponding commands in the considered linear section of the program and is not related to the speed of external devices. Thus, the linear portion of the program is uniquely determined by the number of pulses on the interface control lines. As clock pulses, sample timing or command execution signals can be used. For example, for the KP580IK8 microprocessor, as a clock pulse, M command samples can be sent to the clock input of the device. At the same time, the number T of T. clock pulses is strictly deterministic and is determined by the number of commands in a given linear portion of the program. Similarly, a strictly defined number of clock pulses, equal to the total number of machine cycles for passing commands to a given linear program section, can be obtained using microprocessor SYNC pulses as signals at the clock input of the device.

As clock pulses, signals of a microcomputer clock generator can also be used (for K580IK80 microprocessor). In this case, the number of clock pulses on a given linear portion of the program is determined in the interval T f7. The use of the Standby mode is due to the fact that the control microcomputers may include special exchange processors (channels that work according to their program) and therefore are asynchronous with respect to central processor).

In many applications, the time spent waiting for an asynchronous response on the readiness of an external device to be exchanged can be limited from reasonable considerations to the maximum number TW. This is the minimum number of clock pulses T equal to the total number of clock cycles 1 /, the TTL command passing of this linear program section pulses

f WMCIKC

I

about

TI t +

T

H

132

where T is the microprocessor wait cycles.

If an external device participates in the exchange with the microcomputer, for which it is impossible to establish this time is obviously long (for example, when the microcomputer is operating in a multiprocessor system), the command providing such exchange can be

identified as an independent linear program section, for which one of the expected addresses A is the address of the next command, and another Ay is the address of the command, the number of clock ones

pulses T is equal to the number of cycles of this command. At the same time, the device performs this linear section in accordance with the description until the signal is ready

external device.

The reception of information into the counter 107 is also carried out in the presence of a pulse at its counting input (i.e. unconditionally), since the control is by.

The R, S-BXOAaM D-flip-flops that make up counter 107 take precedence over the control on the synchronization input C.

After loading T at the outlets

the elements OR 60 and 62 is set to a single value of the signals, and the output of the element OR NOT 59 is zero. A single signal from the output of the element OR 60 is fed to the inputs 83 of the block 56 of the counters and 84 of the block 57 mic-. software management. The unit value of the clock control signal from the input 83 (Fig. 8) is fed to the second input of the AND element 108 and is opened for passing the clock signals from the input 86 to the counting input of the first counter 107. At the same time, a single signal from the input 83 is fed to the input of the inverter 110, and

The zero signal from its output locks the AND 109 element, prohibiting the passage of clock signals from input 86 to the counting input of the second counter 107. A single signal from input 81 of the block

57 of the firmware control (Fig. 7) is fed to the fourth input of the register 104, the first and second inputs of which contain zero signals. The next clock signal information word 1X00 is recorded in the register 104. At the inputs of the block 105 of the permanent memory of the block 57 of the firmware control is set address 1100 and signals

33

at its outputs, they take the values indicated in line 13 of table 4. A single signal from the output 78 of the firmware control unit 57 is fed to the input of the register 54, to the information input of which the information word A is received from the output of the fixed memory unit 58, since the input of the lower-order address bits is received from the output 81 of the firmware control unit 57 word 00, in block 58 of the permanent memory, cell B is selected; in register 54, the expected address Aj is memorized; If the next current address A, which enters register 52 from information input 15, is not equal to the expected A, the output signal comparison circuit 55 saves a single value, and if the condition T f O (a single signal at the first address input 84 of the microprogram control unit 57), the address 1101 is formed at the inputs of the fixed memory unit 105, after which the comparison with the current address is repeated for the expected address A-. When condition A fA is satisfied, the cycle of comparing the current address and the transition vector is repeated for the addresses of the following commands of this linear portion of the work program.

The operation of the control signals by the storage unit 105 in accordance with Table 4 is provided as follows.

Each of the 16 sets of input variables on the four address buses of the permanent memory unit 105 corresponds to the values of the signals on the output lines of this block, presented in Table 4. After the signal is removed, a general reset at the inlet 74 of the block 105 of the permanent memory sets the signal value corresponding to the information reading mode from the block 105. Later in the process of operation of the device the block 105 of the permanent memory is constantly in this mode. Each change in the value of at least one signal at the address inputs of the fixed memory unit 105 leads to a change in its input signals in accordance with Table 4. For example, when the value of the signal at the third input 85 is changed, the unit 105 changes from zero to one at zero the values of the signals at the first, second and fourth inputs of the value of you

20 so

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The signals, setting up the pia before this change in accordance with the first row of Table 4, are set in accordance with the second row of Table 4, i.e. the value of the signal at the fourth output 79 of the block 105 goes from one to zero, and the signals at its other outputs retain the same values.

fO In the event of a failure or malfunction leading to the bypass of one or more commands, the process5

0 o

; 0 5

cop 1 can come to address A or

five

0

And before the expiration of the established minimum number T of clock pulses. In this case, the signal at the output of the comparison circuit 55 takes a zero value. This signal is fed to the second input 85 of the firmware control unit 57 and then to the third input of the permanent memory unit 105. At the address inputs of the constant unit 105, address 1000 is formed (condition A i A) or 1001 5 (condition fulfillment And Ay), and at its outputs the values of the signals are specified, indicated respectively in rows 9 or 10 of Table 4. The zero signal from the output 77 of the microprogram control unit 57 is fed to the information input of the trigger 63. The sync input of this trigger from the output of the comparison circuit 55 is supplied via the clock signal 55-71-66- -63, and the trigger 63 is set to the zero state. A single signal from the inverted output of the trigger 63 is fed to the input element AND IS NOT 69, and the signal at its output takes a zero value. This signal enters the process - .sor 1 as an interrupt request signal. The interrupt acknowledgment signal is fed through the control bus 14 to the input 19 of the indication of the transition of the device 2 and then to the installation input to the O flip-flop 65, setting it to the zero state. The zero signal from the direct output of the trigger 65 is fed to the second input of the element IS-HE 69 and prohibits the signal from being interrupted. At the same time, a single signal from the inverted trigger output 65 unlocks the AND 68 element to pass the control signal.

The processor 1 proceeds to process the interrupt associated with the signal from the device 2 for monitoring, and at the address input-output set-.

35-13, the interrupt program addresses are displayed. The expected addresses and A-continue to be alternately compared with the current addresses A and at the output of the circuit 55 a single value of the signal is set. Microprogram control unit 57 outputs control signals in accordance with rows 13 and 14 of Table 4, i.e. The device 2 for monitoring the execution of the programs is in the waiting state.

If, when processor 1 executes the linear section L of the program, condition T, 0 is reached, the signal at the output of the element OR 60 takes a zero value. This signal is fed to the input 83 of the block 56 of the counters and then to the second input of the AND element 108 and through the inverter 110 to the second input of the element AND 109. The AND element 108 is locked, and the first counter 107 is subsequently in the zero state. Element AND 109 is unlocked to pass the clock signals from input 86 of block 56 of counters to the counting input of second counter 107, where the CT is counted. At the same time, the zero signal from the output of the element OR 60 is fed to the first address input J34 of the firmware control block 57, the outputs of which set control signals in accordance with rows 5 or 6 of Table 4, i.e. it continues to remain in the pending state of address matching.

If the condition А А (А А-) is processed during the processing by the processor 1 of the linear section, the microprogram control block 57 sets the outputs at the outputs of the signals indicated in line 1 (2) of table 4. The next clock signal to the register 104 is the information word 0110 (0010), the address inputs of the permanent memory unit 105 is the address 0010, and the control signals are set at the outputs of the program control unit 57 in accordance with line 3 of table 4.

The information word 10 enters from output 81 to the input of the lower bits of the address of block 58 of the permanent memory. A single (zero) signal from the output 80 of the microprogram control unit 57 is fed to the control input 82 of the switch 72 and connects to the outputs of the first 89 or second 90 group

inputs. Information word B J from Constant 58

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With the address B + 3, the inputs of the switch 72 enter and, from its output, the information inputs of the register 53 receive the information word Bj (B |).

 Thus, there is a selection of the information array for monitoring the next linear segment L | (L-). A single signal from the output 79 of the block 57 of the firmware control is supplied to the first input element And 67 and

unlocks it for signaling. From the output of the OR 62 element to the reset input of the trigger 63. If the condition T, 0 is satisfied by the moment of transition to the next linear participant5 of the program, the zero signal from the output of the OR 62 element to the reset input of the trigger 63 is received and its state does not change. If the condition TO Oh is not

0 is executed, a single signal from the output of the element OR 62 resets the trigger 63 to the zero state and a logical signal 1 is set at its inverse output. The request signal

5 interrupts from the output 21 of the device 2 for monitoring the execution of the program are input to the interrupt of the processor 1. The interrupt request in the device 2 for monitoring the execution of the microprogram program is detected by a signal. The interruption of the processor 1 is confirmed in a similar order.

The next clock pulse loads register 104,

 The address inputs of the fixed memory unit 105 are set to the information word 0011 and the control signals are set to the outputs of the firmware control unit 57 in accordance with line 4 of Table 4. As a result of the effect of these signals on the elements of the device 2 to monitor the execution of the programs, the characteristic set of 5 T is loaded. (Tr into block 56 counters, after which the device is prepared to monitor the execution of the linear section L. (L-) of the microcomputer program.

If upon receipt tj clock

0 pulses the condition А А, - (А А j) is not fulfilled, i.e. as a result of a failure or malfunction, processor 1 proceeded to execute a command with an arbitrary address, mine address A (A;),

5 signal at the output of the circuit OR NOT 59 takes a single value. This signal is fed to the trigger trigger 64 and under the influence of the zero signal on the information input is

the first trigger coming from the output of the element OR 60, it goes to the zero state. The signal from the trigger output 64 is fed to the input of the element And 66, and from its output to the sync input of the trigger 63. The zero signal to the information input of the trigger 63 from the output 77 of the block 57 of the microprogram control (Table 4, lines 5 and 6), is stored in the trigger 63, a logical 1 signal is set at its inverse output, and an interrupt request signal arrives from the output of the AND-NE element 69 to the interrupt input of processor 1. Processor 1 processes this request in the order discussed earlier.

The removal of the interrupt inhibit signal in the device 2 for monitoring the execution of the microcomputer programs occurs either 20 kT while remaining non-zero and

by signal General reset by circuit 17-61-63 (65), or by signal recording information received in the load cycle of block 56 counters (Table 4, lines 4, 8,, 12 and 16) from the output 76 of block 57 of the firmware on the chain 76-70-68-61-63 (65) to the installation inputs of the trigger 63 and 65.

When the interrupt signal from the external device arrives at processor 1 at the scheduled time, 158 times.

the signal on the trigger sync trigger 64 retains a zero value (plot 156)

If, as a result, the interference (conditionally represented by a pulse 25,157), leading to the execution of an erroneous transition within the linear portion of the program, compares the current address A and one of the expected addresses A. (or A;) will not happen

The controls from the linear section are transferred to the interrupt program. The device 2 for monitoring the execution of the microcomputer programs detects the exit from the work program by interrupting after the expiration of Tj cycles from the moment of the beginning of the linear section and sets the trigger 63 to the zero state. At the moment of transferring control to the external interrupt processing program, the processor 1 triggers the Interrupt Acknowledgment signal, which prohibits the output of the interrupt signal from the device 2 to monitor program execution. After the processor 1 returns from the breakout processing program to the incomplete linear section, it reaches one of the expected addresses and the device 2 for monitoring and processor 1 self-synchronizes by loading the service information about the next linear section into the counter block 56 and register 53 and setting the triggers 63 and 65 single state.

The operation of device 2 according to the second variant (Fig. 3) is illustrated by time diagrams (Fig. 16, a, b, c), which reflect the loading process (moments 145 and 146 of time) and a gradual decrease in the contents of the counters T (Eyur 147), lT (plot 148) and three counters T ,, (plot 149-151). At time 152 (Fig. 16a), the contents of the counter T become zero (plot 147) and the zero value of the signal (plot 153) is set at the information input of the trigger 64. From this point in time, the content of the counter T decreases. At time 154, the current address of program A and one of the expected addresses A, (npi A, -), coincide. A coincidence pulse 155 is generated at the synchronization input of the trigger 63 at the moment the microcomputer goes to the beginning of the next linear section. The content is countable scheduled time 158 time

the signal on the trigger sync trigger 64 retains a zero value (plot 156).

If, as a result, the interference (conditionally represented by a pulse 157), leading to the execution of an erroneous transition within the linear portion of the program, compare the current address A and one of the expected addresses A. (or A;) will not happen

and at time 159 (before resetting the counter T, time 160), simultaneously with the appearance of a pulse 155, the average signal at output 21 of device 2 (plot 161) takes a zero value.

If, as a result of the interference, 157, leading to an erroneous transition to another line,

0, the program section (Fig. 16, b), the comparison of the current address A and one of the expected addresses A (or A :) will not occur and the pulse 155 does not appear at the output of the comparison circuit 55 before

5, the zeroing time 162 of the counter ST (plot 148), the signal at the synchronous input of the trigger 64 takes a single value (plot 156), the states of the flip-flops 64 and 63 change, and the signal at the output 21 of the device 2 takes a zero value (plot 161).

If as a result of the interference 157 at the expected time 154 (Fig. 18) on one of the controls

5 lines of interface, the number of registered impulses was less,. than what was predicted in the preliminary analysis of the work program (plot 151 does not touch the horizontal axis

0

at time 154), a comparison pulse 157 arrives at the synchronous input of the trigger 63, a change in the state of which leads to the appearance of a zero signal (plot 16 — interrogation request) at the output 21 of the device 2

The plots in Figures 16-18 indicate that the time between the occurrence of a failure and its detection in the proposed device does not exceed the duration of the linear section of the program, which allows you to organize a timely response of the control device in case of an emergency.

The use of the invention allows control of the microcomputer or programmable controller bus, as well as information address buses, to provide a quick response to an error (failure or failure; the response time does not exceed the time the machine passes the linear portion of the program), to prevent the possibility of an accident of the controlled object the uncontrolled wandering of the microcomputer according to the program as a result of an error (failure or failure).

Claims (2)

1. A device for controlling the execution of programs containing a block for selecting the maximum and minimum number of pulses, a trigger, a register block, a comparison circuit, an AND element, an OR element, and a microprogram control unit, the information output of the register block being connected to the first information input of the circuit comparison, the equality output of which is connected to the first address input of the microprogram control unit, the recording input of the connecting device with the first input of the recording of the register unit, characterized in that, in order to increase reliability of monitoring the implementation of programs entered into the device register, and 50 two registers, a firmware control unit and a comparison circuit, the output groups of the first and second registers are connected respectively to the first and second groups of the permanent memory information unit, the information input of the device connected to the information input of the register block, the input of the initial installation of the device connected to the inputs of the initial the installation inputs of the comparison circuit, the register input, the block of the permanent memory of the device are connected to the input of the tee, to the input of the micro block, the first register, and formational input device coupled to an information input of the first regist- software control, with the input of the initial installation of the block, the allocation of O five 0 five maximum and minimum number of pulses and the input of the set to the trigger, the inverse output of which is the output of the device error, the synchronous input of the device is connected to the trigger synchronization input, the information input of which is connected to the zero potential bus j the output of the fixed memory block , the block of selection of the maximum and minimum number of pulses and the second information input of the comparison circuit, the group of outputs of the minimum and maximum number of clock pulses of the block of maximum and minimum number of pulses are connected respectively to the input groups of the OR element and the AND element, the outputs of which are connected respectively to the second address input of the microprogram control unit and to the single trigger input, the output of the OR element is connected to the input of the third block of the output module 5 dividing the maximum and minimum pulses, the clock input of the device is connected to the clock inputs of the microprogram control unit and the block for allocating the maximum and minimum number of pulses, the register output is connected to the input of the higher bits of the address of the constant memory block, first, second, second, fourth the outputs of the micro5 software control unit are connected respectively to the first and second inputs of the recording block of the allocation of the maximum and minimum number of pulses, the register recording input and Odom 0 least significant bits of the address of the block of permanent memory, the second input of the record of the register block is connected to the lower bit of the information output of the microprogrammed control unit. 2. A device for monitoring the execution of programs containing a block, counters, three flip-flops, the first AND element, the first OR element, the NAND element, the first pulse shaper, 0 two registers, a firmware control unit and a comparison circuit, with the output groups of the first and second registers being connected respectively to the first and second groups of information inputs of the comparison circuit, the device's recording input is connected to the input the inputs of the comparison circuit, the recording input of the device is connected to the input records of the first register, the information input of the device is connected to the information input of the first register 41 pa, the group of inputs for the set mode. of the device is connected to the group of counting inputs of the counter block, the input of the initial installation of the device is connected to the input of the first trigger in О and the first input of the first element OR , the output of the first pulse shaper is connected to the write input of the block of counters, the output of the NAND element is the error output of the device, the inverse and direct outputs of the second and third flip-flops are connected respectively to the first second inputs of AND-NO element, first output elements. This OR is connected to the zero input of the second trigger, characterized in that in order to increase the reliability of control over the execution of the program, a third register, a permanent memory unit, a switch, a second pulse shaper, an OR element, and the second and third are entered into the device. the elements OR, the second and the third elements AND, the first, second, third, fourth, fifth and sixth outputs of the microprogram control unit are connected respectively to the input of the first pulse generator, to the information input of the second trigger, to the input recording a second register, the first input of the second AND gate, a control input of the switch and to the input of younger. the address bits of the block of permanent memory, the output of the second element OR is connected to the information input of the first. the first trigger, with the input of the prohibition of the account of the counter block and with the first address input of the microprogram control unit, the equality output of the comparison circuit is connected to the second address input 1M . . . 1598142 house of the firmware control unit. and through the second pulse shaper with the second input of the first element I, the clock input of the co5 device is unified with the clock inputs of the counter block and the microprogram control unit, the input of the initial installation of the device is connected to the inversion input of the microprogram control unit U and to the input of the initial installation of the third register, the output of which is connected to the address input of the higher bits of the permanent memory unit, the output group of which is connected to the group J5 information inputs of the counter block, a group of information inputs of the second register, the first and second groups of information inputs of the switch, the output of which is connected to 20 information input of the third register, the fourth output of the firmware control block is connected to the input of the recording of the third register, the inverse output of the third flip-flop and 25, the output of the first pulse generator is connected respectively to the first and second inputs of the third element AND, the output of which is connected to the second input of the first OR element, the output of which is connected to the single input of the third trigger, the input of the device transition sign is connected to the zero input of the third trigger, group of minimum outputs the number of clock pulses, the group of outputs of the difference between the maximum and minimum number of clock pulses and the group of information outputs of the block of counters are connected according to 40 groups with UQ element input NOR of the second and third element or elements IGSH output is coupled to the clock input of the first flip-flop, the output of the second AND element is connected to nule45 vym input of the second flip-flop. Table 1 n m 43 with about  one , 0 A b BI t. Dto ic Jm Ajc B at: 13.1598144 Continuation of table 1 i-nc n ° at one) t  sh table 2 Oh oh ABOUT Oh oh about oh oh 1 1 1 1 about o 1 1 oh oh oh oh oh eleven 1 1 about 1 1 о о 1 1 oh oh 1 1 1 about oh oh one 1. 1 about oh oh about about 1 about Table 3 49 AT 1315981 Continuation of table 3 50 L. eleven .one About About 1 1 ABOUT 1 about 1 Data O1 O1 0O eleven X x x x 1 1 About about about about 1 one about 1 FIG. e / yj "  G 7 SS J5 Sf f: f 9S zg FIG. FIG. five Phage.6 Fi9l 9 ten Fig. / 0 126I fa hb Phi. eleven Fig.12 f  / 27 j  iZ5  f3i m I l 1- -h I / 27 k7 3L, /%  .T / - {) "; lH, m iPtfaVjr Li-rHr, iiATi-JoL) LrT {Tn: AWof} Lj-lf {T, j; ATj; Toi) Phage. 7 - /, 47t 3f f39 f I Sw Fi.in.15 151 f48 I i 752 Fig: 17