SU1631542A1 - Multimicroprogram control system - Google Patents

Abstract

The invention relates to automation and digital computing and can be used as a control subsystem in multilevel control systems for collecting and processing information. The purpose of the invention is to increase the speed when implementing parallel asynchronous algorithms. The system contains microprogram control units 1.1-1.N., a group of 2 elements AND, a group of 3 elements OR, a block of 4 elements OR, a block for transmitting start addresses, a single vibrator 5, an element AND 6. The operation code performed by the system is given

Description

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at input 7, and the start-up signal at input 8. During operation, each of the 1.1-1.N blocks independently and in parallel with the operation of other blocks asynchronously executes the microprogram sections assigned to it. The micro-operation signals are output at outputs 11.1-11.N and the status of each of the microprogram control units is output at 12.1-12.N. The completion signals of the issued micro-operations are received at the inputs T0.1-10.N, and the logic conditions - at the inputs 9.1-9.N. Each unit of firmware

The invention relates to automation and digital computing and can be used as a control subsystem in multilevel control, acquisition and information systems.25

The purpose of the invention is to increase the speed of a multi-microprogramming control system when implementing parallel asynchronous algorithms, i.e. when there is a two-way communication between the control and the control device 30. Each such link is implemented as a line consisting of forward and reverse channels. On the forward channel, control unit 35 generates a micro-operation signal, and a reverse signal is received on the reverse channel — an event confirming the completion of the corresponding micro-operation .40

The implementation of parallel asynchronous firmware defined, for example, using asynchronous block diagrams or Petri nets, implies that the corresponding control device 45 contains technical means, in particular, when specifying parallel asynchronous algorithms using parallel asynchronous block diagrams, technical tools are needed for 5d microprogramming the following types of vertices: operator (issuance of a micro-operation); conditional transition; assembly; bifurcator; synchronizer.

A vertex of the assembly type — an n-transition to some microcommand of a parallel section can be performed from any other parallel section. Top bifurcator type - any

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The control can start parallel sections of the firmware in any other blocks by transferring the corresponding starting addresses through block 4 of the transfer of launch addresses. Synchronization of parallel firmware is performed by polling the signals of the bus 13 of the state of the firmware control blocks. A sign of the end of the system operation is generated at the output 14, provided that all the firmware control modules have completed their work. 1 hp f-ly, 10 ill.

0 5

0 5 0

5 d

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parallel section can run other parallel sections of the algorithm. The top of the synchronizer type corresponds to the merging of two or more parallel sections and the transition to a sequential section of the algorithm. Vertices of the synchronizer type can appear in any parallel branches of the asynchronous control algorithm.

The possibility of microprogramming asynchronous parallel algorithms, collecting and processing information through the implementation of algorithms with vertices such as assembly, bifurcator, synchronizer increases speed.

The system provides parallel and independent operation of the firmware control blocks, which allows the implementation of parallel control and information processing algorithms.

Fig. 1 shows a functional system diagram; 2 is a functional diagram of the 1st firmware control block; FIG. 3 is a functional diagram of the microcommand address generation unit; FIG. 4 is a functional diagram of the microoperations synchronizer unit of FIG. 5 — functional diagram of the synchronizer parallel microprogram unit of FIG. 6 is a functional diagram of a block of elements or transmission of launch addresses in FIG. 7 - microinstructions formats used by the multiprogrammed control system; FIG. 8 shows the timing diagrams of the operation of the device; FIG. 9 shows the algorithm of operation of the microprogram control unit; FIG. Fig. 10 illustrates an example of the operation of a multi-program control system.

The multiprogramming control system contains microprogram control units 1.1-1.N, a group of 2 elements AND, a group of 3 elements OR a block of 4 elements OR the transfer of start addresses, a single vibrator 5, a element JQ And 6, input 7 of the operation code, start 8, first inputs 9.1-9.N logical conditions, inputs 10.1-10.N completion of microoperations, outputs 11.1-11.Y and 12.1-12.N of microprogram control 15, bus 13 (second input of logical conditions) state of microprogram control and output 14 sign of the end of the work.

Survey logical conditions COLU. The microcommand information field of format B contains the start addresses A, AC, ..., A of parallel microprograms. The information field of the microcommand of format c is filled with zeros. The information field of the microcommand of format D contains microoperations supplied to the outputs 11.1 of the corresponding microprogram control unit. The information field of the micro command of the E format contains the code for determining the KOPM parallel microprograms

Figure 8 shows the time frames of operation of the device under the condition that the microprogram control unit sequentially executes micro commands of the format A (A), D (

Unit 1 firmware control 20 V (), E () and C ().

They form a micro-command memory node 15 with outputs 16 and 17 of the micro-command information field and a micro-command format field, respectively, a micro-command address generation unit 18, a micro-command address register 19, a micro-operation synchronizer unit 20, a parallel microprogram synchronizer unit 21, a micro-command decoder 22, delay element 23, trigger 24, the first group of 25 elements And the second group of 26 elements I.

The micro-command address generation node 18 contains a group of 27 OR elements, a multiplexer 28, an address counter 29, the first 30, the second 31 and the third 32 one-shot, the first 33, the second 34, the third 35, the fourth 36 and the fifth 37 elements OR, the first 38, and second 39 elements I.

The micro-operation synchronizer node 20 consists of a buffer register 40, the element OR 41, and a one-shot 42 o

The parallel firmware synchronizer node 21 contains a group of 43 OR elements, the AND 44 element, the one-shot 45 and the trigger 46.

Block 4 of the transfer of launch addresses is performed on groups 47.1-47.N of the elements OR.

Fig. 7 shows the formats of microcommands of the multiprogram control system. The identification of the format is carried out by the format field F. The information field of a microcommand of format A contains the address field of the next microcommand and the code field

Survey logical conditions COLU. The information field of a microcommand of format B contains the addresses A, AV, ..., AN-J of launching parallel firmware. The information field of the microcommand of format c is filled with zeros. The information field of a microcommand of format D contains microoperations supplied to the outputs 11.1 of the corresponding microprogram control unit. The information field of the E format microcommand contains the code for polling KOPM parallel microprograms.

Fig. 8 shows time diagrams of operation of the device, provided that the firmware control unit sequentially executes microcommands of the format A (), D (),

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The multi-microprogramming control system is designed to control parallel asynchronous processes.

The multi-microprogramming control system works as follows.

In the initial state, all the registers triggers and counters are set in the zero state (in Figures 1-6, the reset circuit is not conventionally shown). In this case, at the outputs of one-shot 5, 30,31,32,42 and 45 are set to zero, the gate input of the decoder 22 receives O and all the output signals of the decoder 22 are equal to O. Therefore, the address output. Each firmware control unit 1 receives a zero code and, accordingly, a zero code also enters through all outputs of the launch address transmission block 4.

Since the triggers 24 of all blocks 1 are reset to 0th, the value 1 is outputted to all outputs 12 and, accordingly, the output 14 of the end-of-operation sign indicates the value 1. The memory control units of the firmware control blocks 1 contain microprograms corresponding to parallel branches of the control algorithm asynchronous processes. At the same time, the microprograms corresponding to the initial vertices of the algorithm are contained in block 1 of the firmware control and are located at the addresses we love. The corresponding addresses are operation codes ,.

ten

Performed by multimicroprogram - governing system.

When a control signal is applied, the start-up to the input 8 of the device, the vibration isolator 5 generates a single impulse that permits the passage of the operation's operation from the input 7 of the device and the input of the group 3 of the OR elements (Figures 8 and 9).

From the output of the group of 3 elements OR the operation code goes to the address path of the microprogram control unit 1.1. From the specified input, the opcode is sent to the node 18 to form the address. Since the operation code differs from the zero code, signal 1 appears at the output of the first element 33 OR, and the one-shot 32 produces a single pulse (Figure 8). , 0 At the same time, the operation code through the group of 27 OR elements, the first input of which from the output of the address register 19 receives the zero code, goes to the information input of the address counter 29 25. When this pulse from the output of the one-shot 32 through the element OR 35 is supplied to the clock input of the counter 29 addresses, fixing in it the operation code. The same pulse through the OR element 37 arrives at the gate output of the address formation node 18, indicating that the microcommand's executive address is output at its information output (Fig. 8).

The address from the information output of the microcommand address generation node 18 is fed to the input of the memory node, and the micro - command sampling process starts there. At the same time, a pulse from the 40 gate output of the address generation unit 18 is fed to the input of the delay element 23 and to the setup input of the trigger 24. In this case, the trigger 24 is set to the & c state 1, indicating that the control unit is running a microprogram (FIG. eight). The zero value from the inverse output of the trigger 24 through the output 12 is fed to the corresponding bus 13-bit. At the same time, the output of the AND 6 element is set to O, indicating that the multi-microprogramming system has started performing the operation indicated on input 7 (block 2 of the algorithm in FIG. . 9) . The information field of the selected microcommand comes on exit 16, and the format field — I on exit 17 of the micro 15 memory node 15.

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, 5 o

- 0 from 5

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programs. The format field of the selected microcommand arrives at the information input of the decoder 20. At the same time, a single pulse delayed by delay element 23 at the time of forming the address in node 18 and sampling the microcommand from memory node 15 enters the gate input of the microcommand format decoder 20 (block 2 of the algorithm in FIG. .9). At the same time, depending on the format of microcommands on one of the outputs of the decoder 20,. a pulse appears from its gate input. Further, the operation of the microprogram control unit is completely determined by the format of the selected microcommand. ,

The following cases are possible:

1. A format A micro-command was selected from the memory node 15 (FIG. 7, blocks 4 and 5 of the algorithm in FIG. 9). The 00 field of the considered microcommand contains code 001, therefore the pulse from the gate input of the decoder 22 is transmitted to its first output. At the same time, in the register of the microcommand address 19, the corresponding fields of the ASD and COLU are recorded from the output of the microcommand information field, which are fed to the microcommand address formation node 18 (Fig. 8). In this case, the Asl field arrives at the first input of a group of 27 elements OR, the second input of which receives a zero code, since a group of 2 elements AND upon completion of a pulse from the output of the one-shot 5 logically disconnects input 7 of the operation code from the address input of the firmware control unit 1.1. From the output of the group of 27 elements OR field A Sd enters the information input of the counter 29 addresses.

The COLU field of the interrogation code of the logical conditions of the microcommands of format A is fed to the first input of the multiplexer 28, the output of which appears to be 1 if at least one of the analyzed logical conditions arriving at input 9 is true and O otherwise.

At the same time, the impulse from the first output of the decoder 22 of the microinstructions format is fed to the input of the one-shot 30, which generates a single impulse by the difference 1-0.

If the output value of the multiplexer 28 is O (all respondents

logical conditions are false), a single pulse from the output of the one-shot 30, through the element 38 and the element 35 is fed to the synchronous input of the address counter 29 (FIG. 8), the value of Asl is fixed in it as the executive address of the next microcommand.

If the output value of the multiplexer 28 is 1 (at least one polled logical condition is true), a single pulse from the output of the one-vibrator 30 through the AND 39 element and through the OR 36 element is received (returns to the +1 of the counter 29 addresses, increasing its content per unit.

Thus, if the logical conditions polled are false, the next executive address will be Asl; if at least one of the polled conditions is true, the current address from counter 29, incremented by one, is used as the execution address. If it is necessary to unconditionally go to the COLU field, A format microcommands write zeros. At the same time, the output of the multiplexer 28, regardless of the values of the logical conditions, is O, and as the executive address, the counter 29 records the address AtA.

The executive address from the output of node 18 is again fed to the input of node 15 of the memory of micro-commands and starts the process of sampling the next micro-command. At the same time, the impulse from the output of the one-shot 30 through the element OR 3 enters the gate output of the address forming unit 18, indicating that the process of selecting the next micro-instruction has started (Fig. 8).

At this point, the execution of format A microcommands is complete.

2.Il of the memory node 15 is selected by the microcommand of format B (FIG. 7, blocks 6, 7 and 15 of the algorithm in FIG. 9). In the F field of the considered microcommand contains the code 010, therefore the pulse from the building input of the decoder 22 is transmitted to its second output. In this case, the information field containing the addresses Aj, AU, ..., AN. from the output 16 through a group of 25 elements And is fed to the corresponding input of the block 4 transfer start address (Fig.8). Each of the fields A (, Aa, .. ,, AMN through the corresponding groups .N

ten

15

20

25

31542

the elements of OR of the block 4 of the transfer of start addresses are fed to the address inputs of identical microprogrammed control units.

Moreover, if a non-zero code is recorded in the A field, the corresponding firmware control unit, as described above, starts the execution of the firmware, the first command of which is stored at address A.

If, however, a zero code is recorded in field A, it arrives at the address input of the corresponding firmware control unit and has no effect on its state, since the output of the element OR 33 remains zero at zero start address.

Thus, by appropriately filling in the fields Aj, A, ..., A c, selective launching of parallel firmware stored in microprogrammed control units is ensured.

At the same time, the impulse from the second output of the decoder 22 arrives at the node 18 that forms the address, starts the process of generating the next executive address. In this case, by the difference 1–0 of the considered pulse, the one-shot 31 produces a single pulse, which through the elements AND 34 and OR 36 increases the contents of the counter 29 of the address. Thus, the transition to the next in order microcommand is performed.

At the same time, the pulse from the output of the one-shot 31 through the element OR 37, goes to the output of the node 18 to form the address, indicating that the process of sampling the next microcommand has begun (Fig. 8).

This completes the process of execution of format B microcommands.

3. From the memory node 15, a micro-command of format C was selected (FIG. 7d, blocks 8 and 9 of the algorithm in FIG. 9). The F field of the microcommand under consideration contains the code 011, therefore the pulse from the gate input of the decoder 22 is transmitted to its third output. In this case, the pulse from the third output of the decoder 22 resets the address register 19 to zero. At the same time, the front of 1–0 under consideration is directed along it, the pulse trigger 24 switches its state, i.e. is set to O (Figure 8).

thirty

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The zero (initial) state of the address register 19 does not interfere with possible re-starts of the considered firmware control unit, since the possible launch address through the group of 27 elements OR is transmitted to the information input of the address counter 29.

The zero state of trigger 24 indicates that the firmware control unit in question has completed the execution of the corresponding firmware. In this case, the value of 1 second from the inverse output of the trigger 24 through the output 12 goes to the corresponding bit of the bus 13 and from there to all blocks 1.1-1.N of the firmware and to the element 6.

4. From the memory node 15, a D format micro-command was selected (Fig. 7, blocks 10, 12, 13, and 15 of the algorithm in Fig. 9). In the F field of the considered microcommand contains code 100. Therefore, the pulse from the gate input of the decoder 22 is fed to its fourth output. At the same time, the considered impulse permits the issue through group 26 ele10

15

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25

the input of the node 18 of the formation of the address, the launch in it of the process of developing the next executive address. The impulse under consideration, through the elements OR 34 and 36, is fed to the input +1 of the counter 29 of the address, increasing its content (Fig. 8). Thus, the next executive address is obtained from the current one by increasing it by one. At the same time, the considered pulse through the OR element arrives at the gate output of the address formation nodes 18, indicating that the process of sampling an ordinary microinstruction has begun.

At this point, the execution of the D format mic command is completed.

5. A microcommand of format E was selected from the memory node 15 (FIG. 7, blocks and 15 of the algorithm in FIG. 9). In the F field of the considered microcommand contains code 101, therefore the pulse of the building input of the decoder 22 is sent to its fifth output. The impulse from the considered output enters the control input of the node 21 of the synchronizer of parallel microprograms (FIG. 2) and is set to a 1-0 difference

The field of micro-operations (MO) expands trigger 46 to state 1.

35

40

viewed microcommand. Corresponding microoperations from output 11 enter the controlled equipment. At the same time, the considered pulse arrives at the control input of the micro-operation synchronizer node 20 and writes into the register 40 the field MO of the format D microcommands. At the same time, the output of the OR element 41 is set to 1. As the micro-operations issued at the output 11 execute asynchronously, the controlled equipment produces signals confirming their execution, which are received at input 10 to the reset inputs of the corresponding triggers of register 40. At the time of completion of all the issued micro-operations, the contents of register 40 become zero evim The output of the OR element 41 is also set to .O. The 1-0 drop drops a one-shot 42, a single pulse from the output of which indicates the end of the process of asynchronous parallel execution of micro-operations specified in the field MO of a D-format micro-instruction. The pulse from the output of the micro-operation synchronizer node 20 goes to

At the same time, the field KOPM of microcommands of format E comes from the output 16 of the memory nodes to the first input of the group 43 of the elements OR. The second input of the group of elements OR from the bus 13 receives signals about the state of each of the blocks 1 of the firmware control. If block 1 executes some firmware, the corresponding trigger 24 is set to 1 and the signal on bus 13 is zero, i.e. If unit 1 has completed the execution of the firmware, the signal on bus 13 is equal to one.

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If necessary, the survey status. block 1.j,, N, bit d Z; The KOPM field of E format microcommands is set to O. Otherwise, the corresponding bit is set to 1.

If the polled unit 1 has not yet completed the execution of the appropriate firmware, the output of the element 4 is 4 After completion of the work for all the polled micro program control blocks from the bus 13, signals equal to one are received,

element output AND 44 becomes equal

and 11I i

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the input of the node 18 forming the address, launching in it the process of generating the next executive address. The considered pulse through the elements OR 34 and 36 is fed to the input +1 of the counter 29 addresses, increasing its content (Fig.8). Thus, the next executive address is obtained from the current one by increasing it by one. At the same time, the considered pulse through the element OR 37 enters the gate output of the address formation node 18, indicating that the process of selecting the next microcommand has begun.

This completes the execution of the D format microcommand.

5. A micro-command of format E was selected from the memory node 15 (FIG. 7, blocks 14 and 15 of the algorithm in FIG. 9). The 101 field in the F field of the considered microcommand contains code 101; therefore, the pulse from the gate input of the decoder 22 arrives at its fifth output. The impulse from the considered output enters the control input of the node 21 of the synchronizer of parallel firmware (Fig. 2) and, by means of a 1–1 drop, sets the trigger 46 to the state 1.

At the same time, the CPC field of the E format microcommand is supplied from the output of the 16th memory node to the first input of the group of 43 OR elements. The second input of a group of 43 OR elements from the bus 13 receives signals about the state of each of the blocks 1 of the firmware control. If block 1 executes some firmware, the corresponding trigger 24 is set to 1 and the signal on bus 13 is zero, i.e. if block 1 has completed execution of the firmware, the signal on bus 13 is equal to one.

with

0

If it is necessary to interrogate the state of the block 1.j, ..., N, bit z; the EOP field microcommands of format E are set to O. Otherwise, the corresponding bit is set to 1.

If the polled unit 1 has not yet completed the execution of the corresponding firmware, the output of the And 44 element is equal to After completion of work, for all the polled microprogram control blocks from the bus 13, signals equal to one are received, and

output of element AND 44 becomes equal

and 11I i

By the 0-1 drop from the output of the AND 44, the one-shot 45 triggers, a single pulse from the output of which goes to the output of the parallel microprogram synchronizer node 21, indicating the completion of all polled microprogram control units. At the same time, the pulse from the output of the one-shot 45 resets the trigger 46 to zero (initial ) state.

The impulse from the output of the parallel synchronizer firmware node 21 sinks down onto the control input of the address generation node 18, and starts the process of generating the next effective address. In this case, the considered pulse through the elements OR 34 and 36 is fed to the input +1 of the counter 29 of the address, increasing its content, and through the element OR 37 - to the gate output of the address forming unit 18 (Fig. 8). Then begins the process of sampling the next micro command.

This completes the execution of the E format microcommand.

Thus, after launching, the firmware control unit 1.1 can execute any of the microcommands of formats A, B, C, D.E. With the help of microcommands of format A, conditional and unconditional transitions are implemented; Format B - launching firmware from any other microprogrammed blocks (bi-fasteners and assembly) controls; Format C - shutdown of the firmware control unit; Format D - issuing micro-operations and waiting and completing asynchronous execution processes (operators); E format - waiting for the completion of asynchronous parallel firmware execution (synchronizers).

After starting, each of the blocks 1.2-1. You can also execute any microcommands of the formats under consideration. issue microoperations; launch and interrogate any microprogram control units, etc. In this case, the operation of each of the firmware control units is similar to that described, i.e. through block 4, the transfer of start addresses to the address inputs receives the corresponding addresses, begins the process of sampling micro-instructions, etc., and the state of each microprogrammed control unit

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It is transmitted to bus 13. Each of the firmware control blocks operates independently of each other and can start and interrogate the state of other identical blocks.

The sign of the end of the operation specified by the corresponding code at input 7 of the operation code is the value 1, outputted at output 14 of the sign of the end of work. The value 1 is generated by the And 6 element when all the triggers of the 24 blocks 1 have completed execution (using the C format microinstructions) of the microprogram sections assigned to them.

Figure 10 shows an example of the operation of a multiprogrammed control system containing four microprogrammed control units.

The system allows asynchronous issuing of micro-operations and waiting for their completion; run parallel sections of firmware for execution, each of which can launch other parallel sections; synchronize the work of any subset of parallel sections of firmware; to have in parallel multiple working firmware control blocks the required number of high and low level firmware about

The listed additional features of the system provide the firmware for any specific parallel asynchronous control algorithms (4,5). “Microprogramming of this type of algorithms in the prototype is impossible.

In particular, when developing microprogrammed control devices for multiprocessor simulation systems, the problem arises of controlling many similar computers. In addition, each of the specialized calculators implements the submodel assigned to it and, after calculating it, it becomes free for the implementation of other submodels. The end of each computer is unpredictable (asynchronously) and depends on the complexity of the corresponding sub- model.

The proposed system allows each calculator to be started asynchronously as it is released. At the same time, the speed of the modeling system increases by 5-6 times due to more

efficient management of parallel processes.

A similar task of managing parallel processes arises in multi-channel communication systems using decision or informational acknowledgment messages. In particular, the algorithms for the process of transmitting discrete information and others in-, are asynchronous and parallel due to the simultaneous operation of both forward and reverse channels. At the same time, the need for synchronization and phasing in the forward and reverse channels — jlamas, the implementation of the principle of reservation and confirmation requires asynchronous discipline of issuing microoperations, starting and synchronizing parallel processes (encoding, decoding, transmitting blocks, block reception, kidney errors, error correction , request transfer, confirmation transfer, etc.)

2

Claims (2)

Invention Formula 1. Multi-microprogramming control system containing N microprogram control units, where JN is the number of parallel algorithms, the AND group of elements, OR, the first groups of inputs of the logic conditions of the microprogram control units are the inputs of the system logical conditions, the outputs of micro-operations of microprogram control blocks are output by the micro-operations of the system, which means that, in order to improve speed when implementing parallel asynchronous algorithms, the block of OR elements, the one-shot, the element AND, the first output of the block of the elements of OR connected to the first inputs of the elements of the OR group, the outputs of which are connected to the input of the operation code of the first microprogram control unit, the i-th output (, N) of the block of elements OR The first inputs of the AND elements of the group are the inputs of the operation code of the system, the one-shot input is the start-up input of the system, the one-shot output is connected to the second inputs of the AND group, you moves which are connected to the second inputs elemen4 four ,,, - five Q 0 0 five combo OR group, the start address of the j-ro firmware control block (, N) is connected to the j-th input of the first block of OR elements, the output of the j-ro state of the microprogram control block is connected to the j-th inputs of the second group of logical conditions from first to (} -1) and with (jH) -ro no N firmware control blocks and j input element I, the output of which is the output of a sign of the end of the system, the inputs of the third group of logical conditions of the firmware control blocks are the completion inputs micro-operations of the system. 2. Pop-up system 1, differing from the fact that the microprogram control unit contains a microcommand memory node, a microcommand address generation unit, a microcommand address register, a buffer register, an OR element, the first and second one-oscillators, a T-trigger , AND element, OR group of elements, microcommand format decoder, delay element, trigger, first AND group, second AND group, the output of the microcommand address register is connected to the first information input of the microcommand address generation node, the output of which is not with the address of the microcommand memory node, the information output of which is connected to the information input of the microcommand address register, with the first inputs of the AND elements of the first group, and the second group, with the information input of the buffer register with the first inputs of the OR elements, the output of the second single vibrator is connected to the first the control input of the micro-command address formation node, the output field of the format and micro-commands of the micro-command memory node is connected to the information input of the micro-command format decoder, the first output of which o is connected to the second control input of the micro-command address shaping node and the micro-command address register synchronization input, the second output of the micro-command format decoder is connected to the third control input of the micro-command address formation node and the second inputs of the first group I elements, the third output of the format decoder micro-commands connected to the input of the installation in the register of the address of the micro-commands and with the counting input of the trigger, the fourth output of the micro-commands decoder is connected to the second inputs of the elements of the second group, and to the synchronization input of the buffer register, the output of which is connected to the input of the OR element, the output of which is connected to the input of the first analog-vibrator, the fifth output of the micro-instructions format decoder is connected to the counting input of the T-flip-flop, the output of which is connected to the first input of the AND element, the output of which is connected to the input of the second one-oscillator, the second inputs of the OR elements, groups are the inputs of the second group of logic conditions of the microprogram unit lot control, output or group of elements connected to the other inputs of the AND, vyhots second monostable coupled to a set input S T flip-flop, the output of the first monostable multivibrator is connected to a fourth control input node forming microinstruction addresses, the output of which is coupled gating 9.1 Qmb (4) 40.1 0 with the input of the delay element and the setup input into 1 flip-flop, the inverse output of which is the output of the state of the microprogram control unit, the output of the delay element is connected to the gate input of the microcommand format decoder, the second information input of the microcommand address generation node is the first input of the logic conditions of the microprogram control , the third information input of the micro-command address generation node is the input of the operation code of the microprogram control unit, the outputs of the AND elements the first group forms the output of the start addresses of the microprogram control unit, the outputs of the elements And the second group forms the output of the microoperations of the microprogram control unit, the third input of the logic conditions of the block is connected to the installation inputs 0 to 0 buffer register. 25 to ChFig. 2 Fig.Z from 22 From 46 10. i & g R L Лг.5 xm 20 m -a / 6 J U R ASA COLU 001fn and y, | 1-1-I 9mot / (W 1.1 (fall, A,, Lh t ... | 0, g | From 1 n ° 11 I Format C MO  ° ° Format D MOP .10-1  "Ro / s / ya / t Ј FIG. 7 s 33 P Sh R Vdg je / "Have &. kiv FIG. eight 9 / & fetff 7 J3ff 00 # 04 / ffjaff / aa 33 gdu la (fff  gy register & ffy / t mwMe # f0f 39 QdffoЈv5f amoЈ 3O fvemwf (39 od o & / 5 / ea / p0r s / 34, $ S / Miff cvfmvv 89 FIG. 9 / ett / em / / 9p & fv yj & fff-f FIG. ten