SU1183980A1 - Device for exchanging data between computer and subscribers - Google Patents

Description

The invention relates to computing and can be used as an input-output system for a computing system with distributed processing and distributed input-output data.

The aim of the invention is to increase the speed and expansion of the scope.

The essence of the invention is to increase the speed by reducing the number of calls to the operational memory when organizing the exchange between the main memory of the central processor and external devices (subscribers). Accessing the RAM occurs when the CPU issues the control word to the subscriber and when it is ready to receive or transmit the data word, i.e. when organizing direct access. After the control word is written to the channel, the control word is issued to the subscriber by the device independently of the central processor.

Direct access to the main processor memory is organized by the request of the direct access request signal from the device, without access to the main memory. The data address is stored in the fixed cell of the operative-memory (OP) of the device and, when performing I / O operations, is read from the OP, modified and written into the same fixed OP cell of the device.

Expansion of the field of application of the device occurs due to ensuring an increase in the exchange system with an increase in the number of subscribers participating in data exchange with the central processor; providing the possibility of buffering information in a special OP device; providing the possibility of preprocessing information; providing the possibility of priority processing of service requests from subscribers involved in the exchange of data; providing the possibility of information exchange with subscribers with a sequential code.

The introduction of the address generation block and the relations it establishes allows the formation

initial addresses of the firmware implemented by the device.

The introduction of the RAM and the relations caused by it allows the temporary storage of data and their processing by the device in parallel with the central processing unit (CPU)

The introduction of the synchronization unit, the first, second and third elements And, the first, second and third blocks of trunk elements, the first and second trunk elements, the decoder and the relations resulting from them, allows synchronization and control of the operation of the device.

The introduction of the channel matching unit and the relations determined by it allows the passage of data words (even and odd) from the central processor to the subscribers, as well as temporary storage of the data word coming from the subscribers and subsequent output of the data word to the central processor.

Thus, the proposed new set of essential, structural features of the device provides for the expansion of its field of application.

FIG. 1 and 2 shows the functional diagram of the device; in fig. 3 functional diagram of the address counter; in fig. 4 - functional block diagram synchronization; in fig. 5 is a functional diagram of the first multiplexer; in fig. 6 functional diagram of the second multiplexer; in fig. 7 is a functional diagram of the operating unit; in fig. 8 is a functional block diagram of channel matching; in fig. 9 functional block diagram of the master. Rally elements; in fig. 10 is a functional block diagram input; in fig. 11 is a functional ₀ microprocessor section (MPS) circuit; in fig. 12 is a functional block diagram of the MPS control decoder; in fig. 13 is a timing diagram of the operation of the device when executing exchange commands (OBM1 - OBMZ); in fig. 14 is a block diagram of the algorithm for determining the priority of subscribers; in fig. 15 is a block diagram of the subscriber service firmware; in fig. 16 3

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block diagram of the firmware direct access algorithm, when reading data from CPU RAM} in FIG. 17, the block diagram of the direct access firmware microprogram 5 with. data records in the CPU RAM.

A device for data exchange between the electronic computer and subscribers (Fig. 1 and 2) contains a permanent memory 1. (PP), an operative memory of 2 (OP), an address generation unit 3, an address counter 4, a synchronization unit 5, the first multiplexer 6, the second multiplexer 7, the third multiplexer 8, operational 15 block 9, decoder 10, register 11 micro-instructions, address register 12, subscriber register 13, trigger half-word 14, direct access trigger 15, exchange direction 20, block 17 matching with the beginning, the second block 18 of the main elements Comrade, 1-K th block 19.1-19. To input-output, respectively, the third block 20 of the main elements, 25 the first block 21 of the main elements, the first main element 22, the second main element 23, the first element And 24, the second element And 25 , third element AND 26, element 30 OR 27, address bus 28, data bus 29, internal bus 30, device start input 31, device control group of inputs 32, exchange request input 32.1, control word sign 32.2 of the control word (CSS), input 32.3 permits for LP, information input-output 33 of the device, input-output 33.1 of the first half-word a, input-output 33.2 of the second half-word, input-output 34 of the address of the device 49, 1-th input 35.1-35. To device subscribers, 1st-th group of subscriber outputs 36.1-36.K of the device, second group the control outputs 37 of the device, the first group of control outputs 45 of the device 38, the first 39 and the second 40 control, information 41 and the third control 42 outputs of the address generation unit 3, respectively, output 43 59

counter 4 addresses, write outputs 44, addresses 45, addresses 46, first 47 and second 48 information outputs of PP 1, respectively, outputs of addresses РОН 49, issue control 50, code 55, operation 51, block I / O register 52, 11 micro-commands, respectively, group 53 outputs of microoperations, group 54 of outputs of internal microoperations, output 55.1 of exchange resolution, output 55.2 of the end of exchange, output 55.3 of interrupts, respectively, of the register of 11 microcommands, the first 56.1, the second 56.2, the third 57 inputs-outputs of the block 17 matching the channel, respectively, output 58 block 20 trunk elements, a group of 59 outputs of the synchronization unit 5, the first 59.1, the second 59.2, and the third 59.3 outputs of the synchronization unit 5, respectively, 60 output of the register of the 13th subscriber, outputs 61.1-61. - outputs, respectively, 62.1-62. K - outputs of the sign of the first - K-th blocks 19.1-19. To input-output, respectively, conclusions

63.1- 63.3. The first 22 trunk element, the trigger 15 direct access, the second trunk element 23, respectively, the output

64 elements OR 27, output 65 of the result of the processing unit, input 66 and output 67 of the processing unit 9, respectively, 68.1 -

68.K - outputs of the end of the exchange of the first K-th blocks 19.1-19.K input-output, respectively, outputs 69 and 70 of the second and third multiplexers 7 and 8, respectively, 71.1-71. To the first-K-th outputs of the decoder 10, output 72 of the second block 18 main elements.

Counter 4 addresses (Fig. 3) contains a counter 73, the first 74 and the second 75 elements I.

The synchronization unit 5 (FIG. 4) comprises a clock pulse generator 76, a trigger 77 and an And 78 element, an output 79.

The second multiplexer 7 (Fig. 5) contains the first -K th switches

80.1- 80.K respectively, the first-K-th trunk elements 81.1—

81.K respectively, the decoder 82, the inputs and outputs 83-86.

The third multiplexer 8 (Fig. 6) contains a switch 87, a trunk element 88 and a decoder 89.

Operational unit 9 (Fig. 7) contains the first-K-th microprocessor sections (MPS) 90.1-90. K, respectively, ·, the accelerated transfer circuit 91, the element OR 92.

In addition (Fig, 7), the device contains outputs 93.G-93.K sign

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the result of the IPU 90.1-90.K respectively; input 94.1 opcode; input 94.2 of the input transfer of the IPU 90.1 and the scheme 91 of the accelerated transfer; input 95.1-95 (K-1) of the input transfer of the IPU 90.2-90.K, respectively; output 96.1-96. (K-1) transfer permits, respectively, MPS 90.1-90, K-1; output 97.1–97. (K – 1) of the transfer signal, respectively, of MPS 90.1–90K – 1; the inputs-outputs 98.1-98 (K-1) of the senior discharge of the RON by the shift of the MPS 90.] -

90.K respectively; inputs 99.199. To control the issuance of the IPU 90.1—

90.K respectively; inputs 100.1 —

100. To the address of the first operand of the IPU

90.1- 90.К respectively; inputs

101.1- 101.K address of the first operand of the IPU 90.1-90.K respectively; inputs 102.1-102.K data MPS 90.190.K respectively; outputs 103.1–103. To the data of the MPS 90.1-90.K, respectively.

The channel matching unit 17 (FIG. 8) contains a register 104, blocks 105-108 of trunk elements, And elements 109-113.

In addition (Fig. 8), the device also contains the first 114.1 and the second 114.2 inputs of the first control input 54.12 of block 17, the outputs 115118 of blocks 105-108 of trunk elements, respectively.

Block 18 of trunk elements (Fig. 9) contains the first -K-th trunk element 119.1-119. To, respectively, the outputs 120.1-120. To the first -K-th trunk element 119.1119.K, respectively.

The I / O block 19.M (FIG. 10) contains a counter 121, an input-output register 122, a control register 123, a second mode trigger 124, a first mode trigger 125, an exchange initiation trigger 126 (PNO), a character trigger 127, a trigger 128 controls, a trigger control, the eighth elements 130, the first element And 131, the second element And 132, the third element And 133, the sixth element And 134, the seventh element And 135, the ninth element And 136, the fourth element And 137, the fifth element And 138 , the eleventh element And 139, the tenth element And 140, the first element OR 141, the second element OR 142, the element NOT 143, the first 144.1, w swarm 144.2 and third 144.3

the inputs of the input group 59 of the I / O unit 19.M ', the first 145.1, the second 145.2, the third 145.3-, the fourth 145.4 the fifth 145.5 inputs of the input group 53 of the micro-operations of the 19.M I / O unit, the output 146 of the K-th digit of the control register 123, output 147 of the inverse K + of the 1st digit of the counter 121, output 148 of the And 133 element, the first 149.1, the second 149.2, the third 149.3 outputs of the output group 36.M of the 19.M I / O unit, the first K-th information inputs 150.1-150 To the register 122 I / o, respectively, the first-K-th outputs 151.1-151. To the register 122 I / o, respectively.

The microprocessor section 90.M (FIG. 11) contains a control decoder block 152, a first multiplexer 153, a switch 154, a second multiplexer 155, a third multiplexer 156, a block 157 of general purpose registers, a buffer register 158, an arithmetic logic unit 159.

In addition (Fig. 11), the device contains the first 160, second 161 ', third 162, fourth 163, fifth 164 sixth 165, seventh 166 outputs of control decoder 152, first 167 and second 168 outputs of general registers 157, output 169 arithmetic logic unit 159, output 170 of the third multiplexer 156.

The control decoder block 152 (FIG. 12) of the microprocessor section 90.M contains the decoder 171 of the sources of the operands of the device 159, the decoder 172 of the function of the device 159, the converter 173 of codes. The inputs of bits 174.1-174.3, 174.4-174.6 174.7-174.9 of input 94.1 of block 152 form, respectively, groups of information inputs of decoders 171. 172 and converter 173.

The time diagram of the channel when executing exchange commands (Fig. 13) shows the numbers of those elements, inputs and outputs of the channel, which are necessary to explain the functioning of the channel. In addition, the state of counter 4 on the time diagram is explained by the following symbols: - in counter 4

Recorded dynamic hangup firmware address 1; at

counter 4 recorded address micro7

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grams of dynamic freeze 2;

ON · - in the counter 4 the initial address of the ί-th microprogram is recorded, coming from the ^- input 33.2 of the channel (Fig. 1). _five

Structural schemes of firmware algorithms (Fig. 14-17) contain symbols that determine the order of execution of firmware. The addresses of microinstructions are formed by the 4-address address counter (Fig. 1). The logical condition signal comes from the output 65 of block 9 to the input of the address generation block, which generates control signals at outputs 39, 40 and 42. The latter control the passage of information through multiplexer 6 and record the initial addresses of the microprograms in the counter 4 addresses.

Consider the purpose of the elements, 20 nodes and connections of the proposed device.

Permanent memory (PP) 1 is designed to store the firmware implemented by the device. To the input 25 PP 1 is the address of the microinstruction from the output 43 of the counter 4 addresses.

PP 1 is a static type memory block and can be built on typical integral 30 elements manufactured by industry, for example, type 556 РТ5 (7).

The output of 44 PP 1 generates a control signal (recording), which, arriving at the input of the element And 24, resolves the arrival of clock pulses from the output 59.3 of the group 59 of the outputs of the synchronization unit 5 to the input of the OP 2.

On-output 45 PP 1 formed the addresses of the cells 0П 2, to which the access occurs. At the output 45 of the PP 1, a signal is issued to access the OP 2 cells. At the exit 47 of the PP 1, the signals of the microoperations are generated, which are; blunt on the register entry of 11 microinstructions.

At the output 48 of the PP 1, control signals are generated by the address generation unit 3. These are the signals of the end of the firmware and the sign of the transition.

RAM (OP) 2 is designed for temporary storage of information in the process of the channel. It is a static type memory device that can be built on typical integrated circuits of the type 541RU1. Information input-output OP 2 is connected to the bus 30, from where it arrives at OP 2 and where information is output from 0P 2 on the commands arriving at the address and control inputs 0P 2 from PP 1.

The address generation block 3 is designed to generate the initial addresses of the microprograms, modify the address of the next microcommand coming from the output 43 of the counter 4 addresses (output 41), as well as to generate control signals to multiplexer 6 (outputs 39 and 40), to the counter 4 addresses (output 42).

Block 3 of the formation of addresses is a combinational discrete device, the law of operation of which is uniquely determined by the correspondence table (Table 1). Tab. 1 determines the state of the inputs and outputs of the driver 3 addresses and the corresponding current and next status of the counter 4 addresses.

Table 1

Inputs block 3 Outputs of block 3 Counter 4 32.1 Requirements exchange 64 Demand analysis 65 ETC 32.2 Sign of CSS 32.3 Resolution ND 18 39 40 41 42 Current Following CMP Π1Ί

0 0 0 0 0 0 0 0 one ^A VE-1 one ^And OT-1 ^Α Β3-ι one X X X X X 0 0 one ^A 1) 3-2 one ^And VE-and ^A VZ-1 0 one X 0 X 0 0 0 one ^NA one ^And VE - 1 NA

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Continuation of table 1

Inputs block 3 Outputs block 3 Counter 4 32.1 64 65 32.2 32.3 18 39 40 41 42 Current Next Requirements exchange Demand analysis * ETC. Sign of CSS Time decision ND CMP PP the ear gush X X one X X X 0 one 0 one ^A lane d one Atek And first X X to · 0 X X 0 0 one ^A BZ-2 one ^A VE-2 ^A VZ-2 X xx one X X 0 one 0 ON. one ^A 1> 3-2 ON, X X X X 0 X 0 0 one ^And 3 one ^A VE-3 ^A G 3-3 X X X X one X 0 0 one ^ON HP one ^A 1> UH ^On CR X X X X X one 0 0 one ^A YAZ-1 one ^And those to ^A wei X X X X X X one one one Namp one ^A tech ON _sp ί mp 0 0 0 0 0 0 0 0 0 x 0 Atek BUT

Note. The x mark indicates the indifferent state of the corresponding input of the I / O channel.

. The signal "Exchange Requirements" is formed at the input 32.1 of the driver 3 addresses.

The signal "requirements analysis" is formed at the output 64 of the element OR 27 (Fig. 2).

PR-signal "Symptom of the result", formed at the output 65 of the block 9 testing.

The "Sign of the control word" signal is formed at the input 32.2 of the address generation unit 3.

The signal "Permission direct access" is formed at the input 32.3 of the block 3 forming the address

KMP - micro-program “End of microprogram”, which is formed at the output of 48 PP 1.

PP - microoperation "Sign of transition", formed at the exit 48 PP 1.

PE-1 ^> ^ OT-2 ^ VZ-3 ^- ADRs and microinstruction ^{codes ec} dynamic hang 1-3, 4 are in the counter address.

NAD _N - the starting address of the subscriber priority determination firmware.

ON _per - the initial address of the firmware coming from OP 2 or. block 9 via bus 30.

ON, is the starting address of the ίth microprogram, coming from the output 58 of block 20.

\ ek- ~ the current code of the micro-command address, located in the counter 4 "

A _ne p-address of the transition, formed by block 3.

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Block 3 forming the address (see

^! tab. 1) operates as follows. Under the influence of the input unit 3 forming microinstruction addresses dynamic codes Suspension unit _REMARK address generation generates at its output 41 the same code, which is written in the address counter 4 via a multiplexer 6 controlled-governing * signals at the outputs 39, 40 and 42.

If the signals "Requirements of exchange" and "Requirements of analysis" are sent to the inputs of block 3 of the formation of the address, then the code of the address of the microprogram of the dynamic freeze 2 is generated. The signal "Requirements of exchange" has a higher priority. If, at the time of the firmware execution, the signal "Analysis request" is received, then this signal is not perceived until the end of the firmware.

If the signal "Sign of US" arrives at the input block 3 of the formation, then block 3 at outputs 39, 40 and 42 Aormi. It controls the control signals (respectively, 1.0, 1) by which the starting address of the ί-th firmware (exchange commands) from output 58 of block 20 through multiplexer 6 will be recorded into counter 4 addresses. Thus, there will be a way out of the dynamic hang 2.

When the “ND resolution” signal arrives at the input of block 3, the latter generates at its output the initial address of the direct access firmware, which, according to control signals via multiplexer 6, will be recorded in the count of 4 addresses.

When entering the input of block 3 signal PR formed by block 9, block 3 implements the modification of the current address received from the output 43 of the counter 4 and outputs it at the output 41. Simultaneously, the control signals at the outputs 39, 40 and 42 of the block 3 ensure its entry into the counter four.

If the output of 18 PP 1 to the input of block 3 receives a PP signal, then single signals at outputs 39 and 40 of block 3 multiplexer is configured to transmit the initial address of the microprogram coming from OP 2. and block 9, and a single signal at the output 42 of block 3 allows it to be written to the counter 4.

When entering the input of block 3 of the signal of the CMP, the latter generates at its output the address of the microprogram of the dynamic hang, which, according to the control signals at the outputs 39,

40 and 42 block 3 will be recorded in the counter 4 addresses.

If at the inputs of block 3 there are no single input signals and none of the addresses of the microprograms of the dynamic hangup is recorded in the counter 4, then this means that the next address is formed in the counter 4 by increasing its content by one. This mode is provided with zero signals on all outputs of the address generation unit.

As a combinational device, the operating conditions of which are uniquely described in Table. 1, the address generation block 3 can be most easily implemented on a programmable logic array.

Counter 4 addresses (Fig. 3) is designed to generate the address of the next microcommand and its input to the inputs of PP 1 and the unit 3 forming the core. Counter 4 addresses has an information input, a control input and a synchronization input.

The counter 73 is designed to memorize, increase by one and issue the address of the next micro-command. It has an input of parallel recording of the address code, a counting input (+1) and a synchronization input C. An address code received at the information input is recorded in the counter if a clock pulse arrives at its synchronization input C. The contents of the counter increase if the pulse arrives at its counting input (+1).

Element And 74 controls the passage of a clock pulse to the counting input (+1) of the counter 73. Element And 75 controls the passage of the clock pulse to the synchronization input C of the counter 73. Counter 4 addresses work in two modes. If the next address is formed by increasing the current address by one, then from the output 42 of block 3 (Fig. 1) the zero signal arrives at the inverse input of the And 74 element, and the next clock pulse from input 59. 1 of the address counter 4 (Fig. 3) to account 13

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the input of the counter 73 and increases its content by one.

If the more complex law of formation of the next 5 is used.

address (at the beginning of the firmware), then the next address goes to the information input of counter 73 and is written to it by the next clock pulse received from input · ¹⁰ and 59.1 at input C of counter 73. In this case, from output 42 of block 3 to input of element I 75 a single signal is received, as a result of which a clock pulse passes to the input C of the 15-pin 73.

Synchronization unit 5 (Fig. 4) is designed to form at its outputs 79.1-79.3 three sequences of clock pulses, 20 shifted relative to each other, which ensure synchronization of the work of the entire I / O channel.

The trigger 77 is used to control the operation of the synchronization unit 5. ²⁵ In the initial state, the trigger 77 is in the zero state. In this case, the zero signal from its output is fed to the control input of the generator 76. 30

The latter forms at its outputs a sequence of pulses only in the presence of a single signal at its control input. Element And 78 is used to form 35 signal to the zero input of the trigger 77 after receipt of the control signal "End of work" from the input 54.7 of the block 5.

The synchronization unit 5 is launched at the start signal, which is fed to the input 31. It is fed to the single input of the trigger 77 and sets it to the single state. A single signal at its 45 output trigger 77 starts the generator 76, which begins the formation of a sequence of clock signals. The sync signaling continues until the end of control input signal “End of Work” arrives at the first input of the element E 78.

After that, when an element 78 of the next clock pulse arrives at the second input from output 79.2 55

the control signal is formed to the zero input of the trigger 77, which returns to the initial state

and removes the control signal from the input of the generator 76. As a result, the generator 76 stops the output of clock pulses.

Multiplexer 6 (Fig. 1) implements the following logical function

4o ⁱⁿ public areas ^{at the} e? ^at 4o ⁺ A $ and ^at ze ^ 4c '

where А_ ,, „is the address at the output of the mullet

plexor o;

And ₄₁ - the address formed

shaper address 3;

ί A ₃₀ - the address coming from the bus 30;

Αξβ - address coming from the output 58 of the block 20 of the main elements;

^at 3e * ^at 40 ~ Control signals generated at outputs 39 and 40 of the driver: 3 addresses, respectively.

Multiplexer 7 (Fig. 5) is designed for switching data words coming from outputs 61. ί-6.1. ^ Respectively, blocks 19.1-19. K, Multiplexer switches the passage of data words from the outputs of blocks

19.1-19. To input-output depending on the code of the subscriber number, which enters the multiplexer input from the output of the register 13 subscriber. Multiplexer 7 implements the following system of logic functions.

^{y 2.} '

^{where a} 1n is the value of the ηth digit of the data word of the ΐth subscriber;

H where K., if the corresponding register bit 13 is written "1";

if in the corresponding digit of register 13 is written.

K; <

year

η is the word length of data from the first K-th subscriber;

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C "- the number of digits of the register 13, and 2 ^ 7 / K-1;

K - the number of subscribers.

The multiplexer 8 (Fig. 6) is designed to embed a sign (direction of exchange) coming from the subscriber having the highest priority, depending on the subscriber code coming from the register 13. Multiplexer 8 implements the following logical function

1 = 1

where X, - is the sign signal value from output 62.1 of the input and output block 19.x.

Unit 9 (FIG. 7) for performing data processing and can be constructed on the template, such as bit slicing _AL, 2901A firm AMO, which is produced by a low-power technology TTL111.

FIG. 7 shows the first (younger) 90.1 and the last (senior) 90.K section of block 9. A typical functional diagram of the microprocessor section (MPS) 90.Ϊ is shown in FIG. 11. Block 9 also contains an accelerated transfer scheme.

Outputs 93.1-93.K are designed to issue a logic signal at the output 65 of block 9 through the OR element 92 (a sign of the result).

Input 94.1 is designed to submit an operation code to the corresponding input of the IPU 90.1-9.0.K from input 51 of block 9. ’

Input 94.2 is designed to feed the input transfer signal to the input of the junior MPS 90.1 of block 9 and to the corresponding input of the initial transfer of the accelerated transfer circuit 91.

Inputs 95.1-95.K-1 are designed to feed the input transfer signal from the outputs of the circuit 91 to the inputs of sections 90.2-90, respectively.

The outputs 96.1-96. K-1, respectively, of sections 9071-90. K-1 are designed to provide for the corresponding inputs of the circuit 91 an accelerated transfer of the signals of transfer distribution permission.

Outputs 97.1-97. K-1, respectively, of sections 90.1-90. K-1 are designed to provide transfer signals to the corresponding inputs of circuit 91.

Inputs-outputs 98.1-98. To the senior level of the working register (RON) unit 157 general-purpose registers. respectively, sections 90.1-90.K are intended for shifting the “unit” previously recorded in one of the RON units 157 of the fixed cell of RAM 2 (FIG. 1) when determining the priority of the subscriber.

Inputs 99.1-99.K respectively MPS 90.1-90.K are designed to control the issuance of data recorded in the general-purpose register from the outputs, respectively, 103.1-103.K sections 90.1-90.K to the output 67 of block 9.

Inputs 100.1 (101.1) -100.K (101.K), respectively, sections 90.1-90.K are used to supply addresses of the first (second) operand.

Inputs 102.1-102.K, respectively, sections 90.1—90.K are designed to supply data from the input 66 of block 9.

The features of using sections 90.1-90.K of block 9 are as follows: in section 90.K, the outputs of transfer propagation resolution and transfer signal are not used; in sections 90.1-90. K-1, the outputs for permitting the propagation of the transfer and the transfer signal are involved.

The decoder 10 (Fig. 1) is designed to form on the first-K-th outputs of the signals that control, respectively, the blocks 19.1-19. To input and output.

Register 11 microinstructions is designed to record the signals of micro-operations, coming from the output 47 of the PP 1.

Register 12 addresses is designed to record the addresses of the cells of the RAM of the central processor, from which information from the input-output 33 of the channel will be read or written.

The subscriber register 13 (FIG. 2) is used to record the code of the subscriber number, which has the highest priority for performing input-output information.

The trigger 14 is a half-word designed to control the recording of half-words, data in the RAM of the central processor.

I

The trigger 15 direct access is designed to generate a signal 'direct access to the central processor.

The trigger 16 direction of exchange is designed to record information that notifies the central processor of

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data transfer direction with a specific subscriber.

The channel matching unit 17 (FIG. 8) is designed to record and control the transfer of data between the central processor channel and the device.

Register 104 is used to record data from the input-output 57 of block 17 and the subsequent transfer of data to the inputs-outputs 56.1 and 56.2 through blocks 107 and 108 of the trunk; elements.

Blocks 105-108 of the trunk elements are designed to provide data to the inputs-outputs 57, 56.1, 56.2 of block 17.

Elements And 109-112 are used to generate signals that control the operation of blocks 105-108 main elements, respectively.

Element And 113 is designed to generate a synchronization signal that records information in the register 104. The synchronization signal is generated when a micro-operation signal is applied to input 54.13 and the next clock pulse arrives at input 59.3.

The input 54.12 receives a two-bit micro-operation, which controls the operation of the elements And 109-112. Control signals are formed at the outputs of these elements, respectively, with the following values of the signals at the inputs 114.1 and 114.2: 00.01, 10.11.

The block 18 of the main elements (FIG. 9) is intended to form and output from the output 72 to the bus 30 (FIG. 2) the signals of the exchange end from the blocks 19.1-19. To the input-output. At the input 54.17 of block 18, a micro-operation signal is received, allowing the passage of signals at the end of the exchange from the inputs

62.1-62.K block 18, respectively, through the main elements 119.1119.K to the outputs 120.1-120.К.

Block 19.M I / O (Fig. 10) is designed to control the issuance and reception of data words from subscribers, and also autonomously performs the formation of the frequency (rate) of the exchange of word bits.

Counter 121 is designed to record the code of the number of transmitted bits of the word when it is received and received from

(subscriber. Counter 121 'is defined by the expression n = 1-8 ₂ K + 1, where K is the number of bits in the control register 123.

The input-output register 122 is designed to record data words that arrive in parallel code at input 30 of block 19.M from the central processor and send them to the subscriber with a serial code from output 151.K of register 122. In addition, information is recorded in register 122 at the input of information data words. in a serial code from a subscriber and are output from output 61.M to the central processor in a parallel code.

The control register 123 is intended to form the rate of exchange of bits of data words when receiving (transmitting) them from the subscriber. Registers 122 and 123 can operate in write and shift mode. If the control input of the registers receives a single signal, then the registers operate in the recording mode, otherwise in the shift mode. ^{

The mode trigger 124 is designed to control the operation mode (write or shift) of the input / output register 122. The mode trigger 125 is designed to control the operation of the trigger 124 and register 123. The trigger 126 of the start of exchange feature generates a signal for requiring the exchange of data words between the central processor and the subscriber.

The trigger 127 characters is designed to store information about the direction of data exchange between the central processor and the subscriber. The control trigger 128 is intended for temporary storage of data bits from the subscriber from input 35.M 19.M. The control trigger 129 serves to control the output of the data word bits to the subscriber.

Element And 130 is designed to form the installation signal in the zero (initial) state of the trigger 128 before receiving one bit of the word from the subscriber.

Elements And 131-133 are designed to generate control signals when micro-operations signals from the group of inputs 53 of the block 19.M are received at their inputs, the control signal with input. yes 71.M and the next clock im19

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pulse from a group of inputs 59 block 19.M I / O.

Element And 135 is designed to generate a signal set to the initial state of the trigger 125 at the time of issuance (reception) of the last bit of the data word. Element And 136 is designed to generate synchronization signals that control the work of the subscriber, when issuing (receiving) one bit of a word. Element And 137 forms a control signal when a signal arrives at its inputs from input 145.5 and input 71.M of the 19.M I / O unit.

Element And 138 generates a signal, which is the signal synchronization register 122.

Element And 139 forms the bits of the word transmitted to the subscriber.

Element And 140 generates a signal set in the initial state of the trigger 129 controls at the time of issuance or reception of the last bit of the word,

The OR element 141 forms the signal of setting the initial (zero) state of the counter 121. The OR element 132 is intended for generating the synchronization signals of the register 122. The HE element 143 is intended for the formation of a single signal necessary for the independent generation of the bit rate of the data words.

Inputs 144.1-144.3 groups of inputs 59 of the block 19.M are designed to supply three sequences of clock pulses shifted relative to each other, respectively

Inputs 145.1-145.5 of the group of inputs 53 of the block 19.M are designed to signal micro-operations that control the operation of the block 19.M.

The output 146 of register 123 is designed to issue a signal that controls the operation of this device when issuing (receiving) a bit of a word.

The output 147 of the counter 121 is designed to issue a single when transmitting (receiving) a data word and a zero signal after the end of the transmission (reception) of a data word.

The output 148 of the element And 133 is intended for issuing synchronization signals of the trigger 127 characters.

Outputs 149.1-149.3 of the group of outputs 36.M of the block 19.M are respectively the outputs of the sign of the beginning of the exchange, synchronization and information.

Inputs 150.1-15P.K register 122 are designed to feed to the register 122 data words from the central processor in parallel code. At the entrance 150.K served sign (direction) of information exchange.

Outputs 151.1-151.K are designed to output a data word in a parallel code from a subscriber to a central [processor (CPU), output 151.K serves to output a data word to a subscriber from the CPU in a sequential code.

Block 19.M I / O operates in the following modes: issuing information to the subscriber and receiving information from the subscriber. Consider the operation of the 19.M I / O unit.

The mode of issuing information to the subscriber.

In the initial state, the registers, triggers and the counter are in the initial (zero) state. Circuit set to its original state in the functional diagram conventionally not shown. Work begins from the moment it arrives at the input 71.M of the 19.M block of the control signal from the output of the decoder 10 (FIG. 1). From this point on, from the group of inputs 53 and 59 of the I / O unit 19.M, the signals of synchronization and microoperations are received, controlling the operation of the I / O unit 19.M. Before issuing data words to the subscriber, a control word is always issued, which necessarily contains a sign informing the subscriber about the direction of information exchange. The control word enters the inputs 150.1-150.M register 122 and is written into it by the falling edge of the clock pulse, which from input 144.3 through the elements AND 138 and OR 142 enters the synchronization input of register 122. The character from input 150.K arrives at the information input of the trigger 127 is written to it on the back, the front of the clock pulse, which through the element 133 receives the trigger synchronization input 127. The resolution signals for passing the clock pulse ~ 3 through the elements 133 and 138 are respectively microoperations; s to the inputs 145.3 and 145.5 and the signal from input 71.M.

After that, according to the clock pulse q and the microoperation entering

21

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from input 145.2, the trigger IN 126 is set to one state. To the input 149.1 of the output group 36.M of the block 19.M, a signal is issued for the sign of the beginning of the exchange to the subscriber. In addition, the clock pulse from the output of the element And 132 sets the trigger 129 and 125 in one state, and also, after passing through the element OR 141 confirms the initial (zero) state of the counter 121. The register 122 is in the shift mode of the previously written control word.

The clock pulse to the register 123 is written to the low-order “one” from the output of the HE element 143. The transfer of the “one” to the high bits of the register 123 is carried out using the next clock pulse, after the trigger 125 is set to its original (zero) state.

On the second clock pulse, the trigger 125 and 126 are set to the initial (zero) state.

When writing "unit" to the high bit of register 123, the next signal from the single clock pulse outputs a single signal from the output 146 of the register 123 and the input element I 136 ’enters and through the next clock pulse it arrives at output 149.2 of the output group 36.M of the 19.M. In addition, a single signal from the output of the element And 136 through the element OR 142 is fed to the synchronization input of the register 122 and shifts the recorded control word. The information signal from the output 151.K register 122 through the element And 139 enters the output 149.3 of the group of outputs 36.M.

A single signal from the output of the element And 136 is also fed to the counting input of the counter 121, which counts the number of transmitted data word bits.

A single signal from output 146, passing through the element 135 and the clock pulse ^ (from the output 147 of the counter 121 to the input of the element 135 and 135 receives a single enabling signal, signal) enters the single input of the mode trigger 125, translating the latter into a single state. A single signal from the output of the trigger 125 allows the recording of the “one” in the lower order digit of the register. "123 from the output of the element NOT 143. Block 19.M is ready to issue the next bit of the data word. The output of the next bits from the output 151.K is similar.

When issuing the last bit of the data word from register 122, a single signal appears on the single output (K + 1) of the digit 121, which arrives at the output 68.M of the 19.M block, signaling the end of the control word output to the subscriber. In addition, a single signal from a single output (K + 1) -th digit of the counter 121 on the clock pulse

passes through the element And 134 and translates the trigger 124 in the original (zero) state, as well as through the element And 140 trigger 129 controls.

The output signal of the end of the exchange of the word, to the output 68.M of the block 19.M signals that the data word is issued to the subscriber and the block 19.M is ready for recording and issuing the next message.

After issuing a control word, data words * are transmitted, which we will call information words (IC). Record and issue IP has some features. When writing an IC on a clock pulse at input 145.3, there is no micro-operation that controls the recording of the sign in the trigger 127.

According to the clock pulse c, there is no micro-operation at the input 145.2 of the sign of the beginning of the exchange, but there is a micro-operation at the input 144.1, which translates an AND13 flip-flop 125 into a single state and also {? state. Subsequently, the recording of the IC in the register 122 and its issuance to the subscriber takes place in a manner similar to the recording and issuance of the control word to the subscriber. After the end of the output of the array of ICs to the input 145.5, a micro-operation of the end of the group exchange is received, which, after passing through the OR element 141, sets the counter 121 to the initial (zero) state.

Mode. receiving information from the subscriber.

19.M input-output unit switches to this mode of operation after issuing the subscriber the manager οπο23

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Va, kotrroe adjusts the subscriber to issue information to the input 35.M block 19.M I / O.

A micro-operation is fed to the input 144.1, which is based on the clock pulse

sets the mode trigger 125 to one. The signal from the output of the trigger 125 sets the trigger 124 in one state. The zero signal from the output of the trigger 124 permits the recording of information (data word bits) received at the input of the register 122 from the output of the trigger 128. The frequency (rate) of receiving the bits is carried out by the 19.M I / O unit, similar to the frequency when issuing data bits by shifting the unit “in register 123 When“ one ”appears on (K-1> -And register 123 output, a single signal from this output is sent through clock pulse Έ _{3 3} through element I 130 to zero input of trigger 128 and confirms its initial (zero) state, preparing trigger 128 to receive a bit of the word d nnyh.

By the next clock pulse

The “unit” will appear on the Kth output 146 of the register 123 and, via the clock pulse, through the element I, 136 enters output 149.2, synchronizing the arrival of the word bit from the subscriber to the input 35.M of the 19.M block. At the same time a single signal from the output of the element D 136 is fed to the counting input of the counter 121 and through the OR element 142 to the synchronization input of the register 122.

As a result, the information bits ("0" or "1") are written to the low-order digit of register 122 from the output of trigger 128.

Receiving the subsequent bits of the data word will be the same. The bits of the word will be sequentially written to the low-order bit of register 122 from the output of trigger 128, and the previously recorded bits will be shifted to the higher bits of register 122 until a single signal appears on the single output of the (K + 1) -th digit of the counter 121, arriving at the exit 149.2 of the output group 36.M of the block 19.M.

Receiving the following IP will occur in a similar way. Upon receiving the last IC in an information array _{(GOVERNMENTAL} words supplied to the input 145.5 microoperation end of the group of exchange which, through elements .proydya

And 137 ^and OR 141, sets the counter 121 to its original (zero) state, preparing it for further work. Next, we return to the consideration of the purpose of the elements and connections of this device (Fig. 1 and 2).

Block 20 of the trunk elements (Fig. 1) is designed to issue from the output 58 to the input of the multiplexer 6 initial addresses of the microprograms, which, after passing through the multiplexer 6, will be recorded in the counter 4.

The block 21 of trunk elements (FIG. 1) is intended for issuing to the bus 28 addresses of the cell of the CPU RAM, to which the call is made.

The main elements 22 and 23 (Fig. 2) are intended for issuing control signals to a group of 37 outputs.

The first 24, second 25 and third 26 elements And are designed respectively for the formation of the recording signal OP 2, the synchronization signals of the register 13 and 12.

The element OR 27 is used to generate the signal requirements of the analysis of interrupts from blocks

19.1-19. To I / O. The signal from the output 64 of the element OR 27 · block 3 of the formation of the address generates the starting address of the firmware analysis (processing) applications for service from the I / O units.

Bus 28 address is designed to transmit the address code of the cells of the CPU RAM. The data bus 29 (bit 0-31) is intended for receiving and transmitting data from the CPU RAM. 0-15 discharge bus 29 is used to transfer the first half-word, 16-31 discharge bus 29 is used to transfer the second half-word. The format of the CPU RAM data word is equal to two subscriber data word formats.

The internal data bus 30 is designed to transfer data between nodes and units of the device.

Microprocessor section 90.M (Fig. 11) is designed to perform data processing. The functional diagram (Fig. 11) shows those inputs and outputs and describes the functions of the MPS only in the part necessary to explain the essence of the invention.

The control decoder block 152 (FIG. 12) is designed to control

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the work of the IPU 90.M. The internal structure of the block 152 uniquely reflect the table. 2-4.

The multiplexer 153 is designed for direct transmission, for shifting data to the right or left by one bit and transmitting them to the inputs of block 157. The multiplexer 153 is controlled from output 162 of block 152.

Switch ί54 _; designed for switching operands to (first and second) block inputs., 59 from four

5 sources: input 102.M data, two sources of block 157 and register 158. The switch 154 is controlled by signals from output 160 of decoder 171 (FIG. 12), the operation of which is described in Table. 2

table 2

---------------------- _g Signals on inputs LH (Fig. 12) 171 Sources (input) signals at the outputs of the switch 154 (Fig., 1) 174.1 | 174.2 | ¹⁷⁴ · ³ First exit | Second exit 0 0 0 0 0 one 167 167 Register output 158 168 0 one 0 0 Register output 158 0 one one 0 168 one 0 0 0 167 one 0 one 102.M 167 one one . 0 102 .M Register output 158 one one one 102.M 0

Tab. 2 makes it possible to uniquely reflect the internal structure of the descrambler * of the torus 171 (Fig. 12) and the switch 154 (Fig. 11).

The multiplexer 155 (FIG. 11) is a multiplexer with a third state and is designed to switch data from two sources: output 169 of block 159 and output 167 of block 157. The multiplexer is controlled by a signal from output 166 of block 152 and by a signal from input 99 .M.

Multiplexer 156 is designed for direct transmission, for shifting the contained buffer register 158 to the right or left by one bit and transmitting it to the first information input of register 158. The multiplexer 156 is controlled from output 163 of block 152.

> Block 157 of general-purpose registers (FIG. 11) contains general-purpose registers used for

⁴⁵ storage of addresses, data or constants. The address of the first (second) operand is given by signals from the input

100. M (101st). From the outputs 167 and 168 of the block 157 to the switch 154, ⁵⁰ contents of the registers are given, the addresses of which are set at the inputs 100.M and

101. M. From the output of the multiplexer 153, the block 157 receives information intended for recording in the corresponding 55 registers of the block 157. The block 157 is controlled from the output 164 and from the input 59.3 of the block 152.

27

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Buffer register 158 (FIG. 11) is intended for intermediate data storage and can be used as a battery. Record 5 information in the register 158 can., Made from the output 170 of the multiplexer 156 and from the output 169 of the block 159. The control. The register 158 is carried out on the control signals from the output of θ and 165 of the block 152 and the input 59.3. In this case, the two-digit output 165 of the block 152 receives the recording resolution signal, respectively, from output 169 or from the output of multiplexer 170, ¹⁵

and from input 59.3 of block 152 there is a recording gate.

The arithmetic logic unit 159 (Fig. 1.1) is designed to perform ¹ arithmetic and logical 20

operations in accordance with the control signals that come from the output 161.

The operation unit 159 performs per cycle. This block ^{25 is} controlled by a decoder 172 (FIG. 12) in accordance with Table. 3

Table 3

thirty

Signals on the LH 172 inputs

174.4

174.5

174.6

The operation of block 159 on operands coming from the inputs; 167 (operand K) and input 168 (operand 8)

35

000 K + 8

00 1 8-K

Continued tabl; 3

The signals at the inputs D1Ch 172 Block operations 159 over operands coming from inputs 167 (operand β, and input 168 (operand 5) 174.4 174.5 174.6 0 one 0 K-8 0 one one κνδ one 0 0 KA8 one 0 one . ΚΛ8 one one 0 KF8 one one one K®5 ~

Tab. 3 provides a one-to-one correspondence between the input signals at inputs 174.4-174.6 and the function of block 159 and, therefore, reflects the internal structure of the decoder 172 and block 159 (Fig. 11).

MPS 90.M (Fig. 11) has a wide range of operations. In a single cycle of his work, short operations are carried out, listed in Table. 3. Long operations, such as division, multiplication, etc., are performed by microprograms composed of short operations, similar to microprograms used in known devices.

The operation of loading and shifting the contents of the registers of block 15U and register 158 is determined by the signals at the inputs 174.7-174.9 (Fig. 11) in accordance with the table. four.

L ^ T a b persons 4 * at ........... ¹ V Signals on block inputs Block 157 Register 158 173 • 174.7 174.8 174.9 Shift Loading Shift Loading 0 0 0 Bezrae- Not Not Loading well register 156 0 0 one Bezra- Not Bezrae- Not

personally

personally

29 1183980 \ thirty Continuation of table 4 Signals at the entrances 173 block Block 157 Register 158 174.7 (.74.8 174.9 Shift | Loading Shift | Loading 0 one one • ** Not Download by E 1 No matter Not one 0 0 To the right K 1 load To the right Loading register 158 one 0 one To the right K 1 load No matter Not one one 0 To the left Download by E 1 To the left Loading register 158 one one 0 To the left Download by E 1 No matter Not

Tab. 4 uniquely describes the operation of the converter 173 codes.

This device consists of two parts: I / O blocks 19.1 -

19.K, which autonomously carry out the formation of the rate of exchange of 35 bits of words, receive! (output) data words and input / output processor (firmware control device

OP, processing unit, channel matching unit, etc.), which microprogrammatically organizes the counter of the initial address and the array length counter, organizes the interrupt, buffers and processes (if necessary) information, ⁴⁵ controls the I / O blocks after receiving ( issuing) their data words, organizing communication with the CPU.

Consider the operation of this device. 50

In the initial state, all the triggers, registers and counter 4 addresses (Fig. 1 and 2) are in the zero state. OD 2 is in an arbitrary state, a zero yachey- ⁵⁵ PP 1 ke stored "single" microinstruction (without control signaling).

From the output of the 42 block 3 formation

addresses to the control input of the counter 4 receives a single signal, which sets the counter 4. in the mode of recording information on the information input. From the outputs 39 and 40 of the block 3 of the formation of the address to the inputs of the multiplexer 6 receives, respectively, the zero and single signals. The circuit set to its original state in the functional diagram is not shown.

The operation of the device begins with the arrival of the start signal at the input 31 of the device. As a result, block 5 synchronization at the outputs

59.1-59.3 groups of outputs 59 form three sequences of clock pulses shifted relative to each other, respectively, and

The zero address code of the counter 4 from output 43, acting on the input of the address generator 3, generates at its outputs the same zero code, which through multiplexer 6 enters the information input of counter 4 and is recorded in counter 4 on the trailing edge of the clock pulse “μ . 13). In this way,

> a “dynamic freeze” (DZ — 1) regime is organized. Out of the mode, 31

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MA DZ-1 is the appearance at the inputs 32.1 and 64 of the block 3 of the formation of the address, respectively, signals "Exchange Requirement" and "Interruption Analysis Request".

Before the exchange of information with subscribers by the exchange commands with the CPU, the input / output processor (PVV) records the "1", "0" and initial addresses of the subscribers' microprograms in fixed cells of OP 2, and also resets the general registers of the block 9. The PVV is configured to exchange information with the corresponding subscriber is three special exchange teams MBP1-3. Command format is given in Table. five.

Table 5.

Teams | Content teams OBM1 ΗΑ ^ ίΟ —15p) ON 03U _CPU (16-31r OBM2 ON ₂ (O-15P) D _sd (16-31r) OBMZ ON ₃ (0-15r) CSS subscriber

Consider the operation of UIP when executing exchange commands that are performed similarly to the configuration commands (Fig. 13).

Information exchange with the CPU is asynchronous. With the arrival of the “Exchange Requirement” signal, the input 32.1 of the address generation block 3 is the last in accordance with the table. 1 truth forms the starting address AC ₅ _ _{2 of} the exchange program with the CPU, which, according to the control signals with the output 39, 40,

42 block address formation passes through the multiplexer 6 and the clock pulse is recorded in the counter 4 addresses. At the recorded starting address, from microprocessor 1, a micro-command is selected, which will be recorded in the register of 11 micro-instructions on the trailing edge of the clock pulse T ₂ ·

As a result, the output 55.1 of the output group 38 of the device is issued to the central processor by the signal "Exchange Enable". In addition, at the output 54.12 of the group of outputs 54 of the internal micro-operations, a micro-operation is issued, which adjusts the matching block 17

with the channel in the mode of information transfer from the input 56.1 to the output 57 of the block 17 At the same time the code of the address Ap ₃ . ₂ counters 4, acting on the inputs of the address generation unit 3, generates at its outputs the same code А ^^, which is recorded in counter 4, i.e. organized mode "dynamic freeze" (DZ-2).

Upon arrival of the "Sign of CSS" signal to the input 32.2 of the address generation unit 3, the latter generates a signal at the outputs 39 and 40, according to which the initial address of the microprogram from the input

33.2 via bus'29, block 20 of trunk elements, multiplexer 6 is recorded in the counter 4 addresses by a clock pulse. At outputs 44-46 PP 1 there will be control signals for recording information from input 33.1 through the channel matching 17 block in the corresponding OPP cell 2.

On the falling edge of the clock pulse, a micro-command will be recorded in register 11, on which output 54.12 contains a micro-operation that controls the passage of information from input 56.1 to output 57 of block 17, and output 55.2 of the output group 38 of the End-of-Operation micro-operation device.

The clock pulse information from the output 57 of the block 17 through the bus 30 will be recorded in the corresponding cell 2 OP.

In addition to the control signals at the outputs 44-46 PP 1, at the output 48 a micro-operation "Microprogramme End" (ILC) is formed, which, acting on the input of the address formation unit 3, generates at the outputs of the last code zero address ^ at the outputs 39, 40 and 42 passes through the multiplexer 6 and is recorded in the counter 4 on the trailing edge of the clock pulse (Fig. 13). PVV goes into mode DZ-1

After writing on the OBM1 and OBM2 commands to the 0P 2 cells of the initial address of the central processor RAM cell (CPU CPU RAM) and the number of words (Ν _SL ) that will be transmitted during the exchange with the subscriber, the PVV executes the OBM 3 command.

The differences between the team MBO 3 and the execution of the commands MBO1 and OBMZ are

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the following: the outputs 44-46 PP 1 will not be control signals; the output 52 of the register 11 reads the code of the subscriber; on the group of outputs 53 of register 11 there are microoperations "Records of the US" (input 145.3 of the 19.M block of the I / O (Fig. 10), "Sign records" (input 145.4) and "Sign of the beginning of the exchange" (input 145.2), which together with the control signal at the output 71.M of the decoder 10 configure the corresponding block 19.M I / O to autonomous operation to receive the control word and then issue it to the subscriber.

The control word from the output 57 of the block 17 coordination with the channel via the bus 30 will be recorded in the register 122 of the block 19.M I / O. PVV goes into mode DZ-1.

At the moment when the last bit of the control word is finished, the 19.M I / O block at output 68.M outputs a signal for the end of the word exchange, and several I / O blocks can output this signal at the same time. UIP organizes priority maintenance of I / O blocks 19.M requiring further control after the end of the issuance (reception) of a data word. This service is performed by the subscriber priority determination firmware (Fig. 14). The signals of the end of the exchange from the outputs 68.M, where M = 1, ..., K, causing the firmware of determining priorities, arrive at the inputs of the block 18 of trunk elements and the inputs of the OR element 27. Signals that cause the firmware of determination of priorities appear asynchronously with respect to CPU and each other. At the same time, more than one signal at the end of a word exchange can occur at the same time. The UIP sets the priority of the mezzvdu with these signals so that only one service request is processed at a time. Until the end of word exchange signals are taken into account of the UIP, they are stored in I / O blocks.

From the output 64 of the element OR 27, the signal of the end of the exchange of the word is fed to the input of the driver 3 addresses. If the PVV is busy with the execution of the firmware, then the signal of the analysis requirement is not perceived, if the PVV is in the DZ-1 mode, then the signal from the output

64, acting on the input unit 3, the formation of the address, forms on you-:

I

During the last 42 zero signal, which translates the 4-address counter into the address generation mode by increasing the current address by one.

With the arrival at the input of the counter 4 clock pulse C from PP 1, the first microcommand of the subscriber prioritization microprogram will be sampled. By the C ₂ clock pulse, the first micro-command will be recorded in the register 11. At the output 54.17 of the output group 54 and the output 49 of the register 11 there will be micro-operations signals that allow the passing of the request code (exchange end signals) from the output 72 of the block 18 through the bus 30 to the input 66 block 9 and the subsequent recording of the application code in one of the general-purpose registers, for example, in the RHON 2 of block 157 (Fig. 11). on the clock pulse C3.

The second micro-command (MK) reads the "unit" from the fixed cell of the OP 2 (recorded in the OP 2 command of the exchange with the CPU) and writes it to the low-order bit of the general-purpose register of block 9, for example, in the RHONE 1,

According to the third MC, a logical multiplication of the contents ΡΟΗ 1 by the contents of the RHON 2 is performed. In the bits of the RON 2, "units" are recorded if the corresponding 19.M I / O unit output 68.M the exchange end signal. If the logical multiplication operation did not generate a signal of the result feature at the output 65 of block 9, then the next MC is shifted “1” to the high bits of the RON 1 and the subsequent logical multiplication ΡΟΗ 1 by RON 2. Thus, the priority poll is performed, at which more priority subscribers are polled more often (by shifting to RON "units") and receive more intensive service, while the service of a low-priority subscriber cannot be interrupted by a service request from a high-priority subscriber.

When generating a logical condition signal (result sign) at output 65 of block 9, the counter 4 address is modified in accordance with the truth table, i.e. he is forming

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Resa MK, which is a function of the product of the current address of the counter and the sign of the result Ζ: Α _Λ , _Κ = “£ (Α _Τ6Κ Ζ); According to this micro-command, a micro-operation “PP ¹ !” Is formed at output 18. PP 1 and micro-operation at outputs 49 and 50 of the register 11 micro-commands, which select the contents содержимого 1 at output 67 of block 9 and enter information counter 4 via bus 30, multiplexer 6 The code of the subscriber having the highest priority (contents ΡΟΗ 1) is recorded in the counter 4 addresses in accordance with the control signals at the outputs 39, 40 and 42 generated by the block 3 of the address generator by the clock pulse.

At the address recorded in counter 4, PP 1 selects the MC, at which the starting address of the service microprogram of the particular subscriber with the highest priority will be read from the fixed cell of OP 2. Signals of micro-operations are developed at the outputs. 18, 45, 46 PP 1. The contents of the fixed cell through the bus 30, multiplexer 6 is fed to the information input of the counter 4. and recorded in it by the next clock pulse.

Consider the implementation of the subscriber service firmware (Fig. 15). With the recording of the initial address of the firmware in counter 4 of PP 1, the first MC will be sampled.

At the outputs 44-46 PP 1, micro-operations are formed, according to which, by the clock pulse, the contents of the RHONE 1 will be recorded in a fixed cell of the OP 2 to indicate the subscriber who completes the exchange.

With the recording of the first MC of the subscriber service firmware into the register 11, at the outputs 49, 50, 54.2 of the group of the outputs 54 of the register 11, micro-operations are formed, which ensure the recording of the contents of the RHONE 1 into the register 13 of the subscriber by a clock pulse.

The address of the second MC will be formed by increasing the content of the counter 4 by one for the clock pulse T (Fig. 15).

The second MK reads the sign from the output 62.M of the 19.M I / O unit through multiplexer 8, bus 30 to the lower order

general-purpose register, for example in RON 3. For this purpose, at output 49 and output 54.16 of the group of outputs 54 of register 11, micro-operations are formed.

The third MK records "1" from the fixed cell of OP 2 to the low-order bit of RON 1. Micro-operations are formed at outputs 45 and 46 PP 1 and 49 of the register 11.

According to the fourth MC, a logical multiplication of the contents <ΡΟΗ 1 by the contents of the ROH 3. Micro-operations are formed at the outputs 49 and 51 of the register 11. If there is no comparison (the signal of the logical condition - the result sign at the output 65 of block 9 is absent) and the next micro-command will be a micro-command of the microprogram of reading data from the CPU RAM. If a logic condition signal appears at output 65, then the address of the next MC will be a function of the product of the current address of the counter 4 and the logic condition signal ()

^And cl “- ^ (Atek"

Those. A switch to the data recording firmware in the CPU RAM is performed (Fig. 15). '

At the fifth MC, the contents of the fixed 0P 2 cell are read into a general-purpose register, for example, RON 4. The zero code of the OP 2 cell is a sign of an odd half-word, and "1" in the low-order bit is an even-half sign. Micro-operations are formed at the exits 45

and 46 ROM 1 and output 49 of the register 11.

I

The sixth MC is the logical multiplication of the contents of the RON 1 by the contents of the ROH 4. Micro-operations are formed at the outputs 49 and 51 of the register 11. At the same time, if a signal is output at the output 65 of block 9, then the address of the counter 4 arriving at the input of the block 3 of forming the signal, modified by the logic condition signal from output 65. After the modified address is written to the counter '4, control is performed by recording the even half-word in the CPU RAM. If the comparison of the contents of ΡΟΗ 1 and РОН 4 does not occur, then os37 ^: 1183980 38

There is an odd half-word write control in the CPU RAM.

According to the seventh MK installing trigger 14 of unit 5 in halfword Noe condition and summation content RON 4 and RON 1. Yields uop at the outputs 54.3 (for even mid-sentence), 54.4 (for odd mid-sentence), and the outlet ¹⁰ 54.14 trup- nN outputs 54, micro-operations at the outputs of 49.51 register 11.

The eighth MC for micro-operations at outputs 44-46 PP 1, outputs 49 and 50 of register 11 records the sum of 15 RON 4 and ΡΟΗ 1 in a fixed cell 0П 2 by a clock pulse.

The ninth MC for micro-operations at outputs 45 and 46 PP 1 and outputs 54.10, 54.8 records in 20 register 12 the initial address of the CPU RAM from the fixed cell 0П 2 via bus 30 and the subsequent issuance of the initial address from register 12 to bus 28 of the address. Trigger 15 ustanavli- ²⁵ ND INDICATES uop in one state at the output 54.5 of register group 54 outputs 11. Signal direct access (ND) from the output

63.2 groups of outputs 37, acting on channel output 30, signals the CPU to demand direct access to the RAM of the CPU.

The address code of the ninth MC, recorded in the counter 4, acting on the inputs 35 of the address generation unit 3, generates the same code at the output 41, which, under control of the signals at the outputs 39, 40 and 42 of the unit 3, is powered into the counter 4 by the next 40 clock pulse . PVV goes into the mode of "dynamic freeze" DZ-W.

Thus, the PWV ⁴⁵ arranges three modes of "dynamic hang": RS-1 is a dynamic hang waiting for signals "Exchange Requirements" (input 32.1) and "Requirements Analysis" (input 64) at the input ⁵⁰ rows address generation unit 3;

DZ-2 is a dynamic suspension of waiting for the "Sign of the CSS" signal (input 32.2) at the input of the address generation unit 3; DZ-3 is a dynamic suspension of waiting for the signal "Resolution ND" (input 32.2) at the output of the address generation unit 3.

When the microprograms are executed, we are DZ 1-3, then the KMP micro-operation is not produced, the exit from the DZ mode 1-3 — according to the corresponding expected signal. The micro-operation of the CML is formed after the execution of any firmware, except for D31 - 3. The C-I output is carried out at the DZ-1.

Consider the execution of the Direct Access (ND) firmware when reading data words from the CPU RAM and sending them to the subscriber, which is performed when the “ND resolution” signal arrives at the input 32.3 from the CPU (Fig. 16).

PVV is in DZ-Zb mode. With the arrival of the "Resolution of the CD" signal on the input 32.3 of block 3, it forms, at the output 41, the initial address of the microprogram, which is a function of the product of the address of the address MP

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Starting address from output 41 to control signals with output 39,

40 and 42 of the imaging unit 3 through the multiplexer 6 enters the information input of the counter and is written into it by the clock pulse.

At the recorded address, from the PP 1, the MC is selected, which forms micro-operations at the outputs 45 and 46, PP 1 and the outputs 49 and 51 of the register 11. According to the micro-operations, a counter is written from the fixed cell 0П 2 to the general-purpose register of the operational unit 9 (for example, RHONE 5) array lengths (Ν _εΛ ), which indicates the number of words to be transferred between the CPU and the subscriber.

The second MK subtracts the “unit”, which was previously recorded in RON 1 from the contents of RON 5 Micro-operations are formed at outputs 49 and 51 of register 11. At the same time, if the array length counter is not zeroed (data words are not all transmitted), then the sequential the course of the microprogram is not violated (the signal of the logic condition at the output 65 of block 9 is not formed), and according to the third MK, micro-operations are formed at the output 54.12 of the output group 54, the output group 53 (input 145.1 "Channel recording" and input

39

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145.4 "Record CSS", FIG. 10) and the output 52 of the register of micro-commands 11, which pass the data word from the input 33.2 of the device through 5 channel matching block 17, the bus 30 to the input of the I / O block 19. write the data word to the register 122 (FIG. 10) and launching an input / output unit for autonomous output of a subscriber to a data bank. In addition, at the output 54.6 of the group of outputs 54 of the register, a micro-operation is issued, which sets the trigger 15 ND to the initial state (zero state, as well as the micro-operation at 15 output 55.2 "End of exchange", which arrives at the output 38 of the device.

On the fourth MC, the contents of the RON 5 are recorded in a fixed cell of the OP 2 according to a clock pulse of microoperations at outputs 44-46 PP 1 and outputs 49 and 50 of register 1 1.

The fifth PC records from the fixed cell 0П 2 to the general register of general purpose unit 9, for example RON 6, the starting address of the RAM of the CPU and the subsequent increase in the contents of RON 6 by "unit" to provide access to the next 30

RAM cell CPU. Micro-operations are formed at outputs 45 and 46 PP 1 and exit 49 registers 11.

The sixth MC for micro-operations at outputs 49 and 51 summarizes the contents of the RON 6 and RON 1. The seventh MK writes the contents of the sum of RON 6 and RON 1 in a fixed cell of OP 2 for micro-operations at outputs 44-46 PP 1 and outputs 49 and 50 40

register 11. In addition, according to the micro-operation of the KMP, the output of the 48 PP 1 PVV is switched to the DZ-1 mode.

If the array length counter is reset (see operators 5 and 6, fig. 16), 45

then the signal of the logic condition from the output 65 of block 9, block 3 generates the micro-command address, which issues the End of Group Exchange micro-operation at input 145.5 (FIG. 10), the micro-operation at output 52, and the Interrupt micro-operation at output 55.3 of the micro-command register 11. In addition, according to the micro-operation of the CMP, at the exit 48 PP 1 UIP, it also goes into the DZ-1 mode.

Consider the features of the execution of the ND firmware when transferring data words from the subscriber to the CPU RAM, in contrast to the ND firmware when reading data words from the RFQ CPU. The firmware (Fig. 17) contains the same MC as the previously reviewed firmware (Fig. 16). The differences consist in two microcommands of symbols 4 and 8 of the flowchart of the algorithm.

The first MK (symbol 4, fig. 17) carries out the formation of microoperations at the outputs 54.1, 54.6, 54.12, 54.13 of the group of outputs 54, and the output

55.2 register 11, which produce the issuance and recording of a word in block 17 through Ζ ^ through multiplexer 7, bus 30, 'and also issue a data word from block 17 to output 56.1 or 56.2 of block 17, depending on the value of two-bit micro-operation at output 54.12 (FIG . eight). ...

On the fourth MC (symbol 8, Fig. 17), the input-and-output unit (BWS) is launched to autonomously receive a word from the subscriber (using the "Channel Record" micro-operation at input 145.1 of the I / O unit, Fig. 10), and also the contents of the RHONE 5 in fixed cell OP 2 for micro-operations at the outputs 44-46 PP 1, at the outputs 49 and 50 of the register 11 micro-commands.

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Claims (2)

DEVICE FOR DATA EXCHANGE - between ELECTRON-COMPUTER MACHINE and SUBSCRIBERS, containing three multiplexers, address counter, read-only memory, microinstructions register, address register, subscriber register, operational block, half-word trigger, direct access trigger, a cryptographic transponder, and a cryptographic array. the output of the address counter is connected to the address input of the permanent memory, the first information output of which is connected to the information input of the register of micro-, commands, the address output of which is connected to the address input an operation unit whose output control input is connected to the control output of the micro-command register, the output of the operation code of which is connected to the operation code input of the operation-unit, characterized in that, in order to improve performance and expand the scope, an address generation unit memory, channel matching unit, decoder, synchronization unit, three blocks of trunk elements, a group of I / O blocks, two trunk elements, three AND elements, with the inputs Ena, the sign of the control word and the direct access permission of the address generation unit are connected to the control bus of the electronic computer, the first and second information inputs and outputs of the matching unit with the channel are connected respectively to the information buses of the first and second half words of the electronic computer, the exchange resolution outputs, the end of the exchange and interrupt the register of micro-commands are connected to the control bus of the electronic computer, the outputs of the first and second main elements and direct access trigger connected to the control bus of the electronic computer, the output the first block of trunk elements is connected to the address bus of the electronic computer, the start input of the synchronization block is the device start input, the first information outputs of the group I / O blocks are connected to the group of output information subscriber buses of the device, the first information inputs of the group I / O blocks connected to the group of information subscriber input bus device, while the information input output RAM is connected to the third information input-output unit with the channel, information input of the register of the address n „1183980 1183980 ca, the output of the second block of trunk elements, the first information input of the first multiplexer, the outputs of the second and third multiplexers, the second information inputs of the group I / O blocks, the information input of the subscriber’s register, the information input and output of the operation unit, the output of which result is connected to the first control input block address generation, the first, second and third address outputs of which are connected to the first, second control inputs of the first multiplexer and control the input of the address counter, respectively, the output of which is connected to the information input of the address generation unit, the second control input of which is connected to the second information output of the permanent memory, the output of the record, the address and circulation of which are connected respectively to the first input of the first And element, the address and control inputs of the RAM, the information input of the address counter is connected to the output of the first multiplexer, the second and third information inputs of which are connected respectively to the output of the third block trunk elements and information output of an address generation block whose interrupt signal input is connected to an OR element output, a group of inputs of which is connected to a group of inputs of the second block of main elements and exits of the end of the exchange of input / output blocks of a group whose sign outputs are connected to information inputs of a third multiplexer , the group of control inputs of which is connected to the group of control inputs of the second multiplexer and the group of outputs of the register of the subscriber whose synchronous input is connected to the output The second element And the group of outputs of the internal micro-operations of the micro-register register is connected to the control input of the first block of trunk elements, the first input of the third And element, the first and second control inputs of the matching unit with the channel that controls the input of the second multiplexer, the first input of the second And element, single and zero the trigger inputs of the half-word, direct access and exchange control, the control inputs of the first and second trunk elements, the control inputs of the third multiplex pa and the second block of trunk elements, the input of the end of the synchronization block, the first, second and third sync outputs of which are connected to the sync inputs of the group I / O; in addition, the synchronization input of the address counter is connected to the first sync output of the synchronization section; synchronization, the second input of the first element And is connected to the synchronous input of the operating unit, the second input of the second and third elements And, the synchronous input of the channel matching unit and connecting To the third synchronization output of the synchronization block, the output of the number of the block I / O register of the micro-commands is connected to the information input of the decoder, the output group of which is connected to the control inputs of the group I / O, the second information outputs of which are connected to the group of information inputs of the second multiplexer; the microinstructions register is connected to the groups of control inputs of the I / O blocks of the group, the output of the first element I is connected to the recording input of the RAM This input of the third block of trunk elements is connected to the second information input / output of the channel matching unit, and the control input is connected to the zero potential bus of the device, the output of the third element I is connected to the synchronous input of the address register, the output of which is connected to the information input of the first block. the outputs of the half-word trigger and the exchange control are connected to the information inputs of the first and second main elements, respectively. one 1183980 2