SU1277125A1 - Device for exchanging data between electronic computer and using equipment - Google Patents

Abstract

The invention relates to computing and can be used as a input-output system for a computing system with distributed processing and distributed input-output; 5th data. The aim of the invention is to increase the speed of the device. The device contains a signal level matching unit, an address generation unit, three blocks of trunk elements, two multiplexers, an address counter, current address register, permanent memory, random access memory, Two operational blocks, low byte register, high byte register, switching unit, decoder, synchronization unit, group of input-output blocks, sign multiplexer, time interval counter, microinstructions register j initial address counter, transfer characteristic trigger, low bye result trigger one, trigger sign of the result of the senior (L byte, control trigger, direct access trigger, exchange control trigger, two AND-OR elements, twelve AND elements, NOT element. 10 Il.

Description

1 The invention relates to computing and can be used as an input-output system for a computer system with distributed processing and distributed data input-output. The aim of the invention is to improve the speed of the device. FIG. 1a, b, c shows the functional diagram of the device; FIG. 2 is a functional diagram of the synchronization unit; FIG. 3 is a functional diagram of an operation unit (OB), in FIG. 4 - functional diagram of the unit level matching unit; in fig. 5 - functional circuit of the switching unit; in fig. 6 is a functional block diagram input; in fig. 7 is a functional block diagram of the control decoder block of the operating unit; FIG. 8 is a time diagram of the operation of the device when executing exchange commands (OBM1-OBM4); in fig. 9 is a flow chart of the subscriber service firmware; in fig. 10 is a block diagram of the microprogram of direct access. The device for data exchange between the computer and subscribers (FIGS. 1a, b, c) contains a permanent memory (PP) 1, a random access memory (SP) 2, an address generation unit 3, count 4 address ad-block 5 synchronization, the first multiplexer 6, the second multiplexer 7, the multiplexer 8 characters (exchange direction), the operating units (ON) 9.1 and 9.2, the decoder 10, the register 11 micro-instructions, the register 12 of the current address, the register 13 low byte, register 14 high byte, counter 15 n The starting address, the counter 16 time intervals, the trigger 17 of the transfer attribute, the triggers 18 and 19 of the results of the dead and high bytes, the control trigger 20, the immediate access trigger (ND), the exchange control trigger 22, the signal level matching unit 23, the unit 24 switching, blocks 25.1-25. N input and output, the second element AND-OR 26, the first element AND-OR 27, fifth: element And 28, the fourth element And 29. the seventh element And 29.2, the third ele. Ment And 30, the sixth element And 31, the second element And 32, the tenth element 52 And 33, the ninth element And 34, the eighth element And 35, the twelfth element And 36, the first element And 37, the eleventh element And 38, the second, the third, first blocks 39-41 of the main elements, the element NO 42, bus 43 high data byte, bus 44 low data byte, data bus 45, address bus 46, information output 47 of the device, input-output 47.1 high byte of the second half-word, input- output 47.2 of the low byte of the second half-word, input-output 47.3 of the high byte of the first half-word, input-output of 47.4 junior b The first half-word site, a group of 48 control inputs of the device, an input 48.1 of the exchange requirement, an input 48.2 of the control word feature (CSS), an input 48.3 of the direct access enable (LR), an input / output 49 of the device address, the 50 start of the device, inputs 51.1- 51.N device subscribers, outputs 52. device subscribers, device interrupt output 53, first device control outputs 54, second device control outputs 55, third 56.1, fourth 56.2, first, second 56.4, fifth, 57, 1 and sixth 57.2 informational inputs-outputs of unit 23 agreed and signal levels, control outputs 58 and 59 of the address generation block 3, respectively, of the recording and modification feature, information output 60 of the block 3, control outputs 61 and 62 of the address generation block 3, control outputs of the 63 and 64 block 3, respectively, of the counting account account blocking, input 65 of multiplexer 6, output 66 of register 12, output 67 of multiplexer 6, output 68 of the counter 4 addresses, outputs 69-76, respectively, of the control of the matching block 23, register control, 13 and 14, addresses, addresses, records, microoperations, signs of transition, addresses re PP 1, outputs 77.1 and 77.2 of the counter 15, respectively, the high and low bytes, outputs 78-80, 81.1-81.3, 82-84, respectively, of the control unit 24 switching, operating units, decoder 10, exchange resolution, ND, interrupt control, block management input-output, internal micro-operations, register micro-command counter 11, output 85

31

block 41 of main elements, input / output 86 OP 2, information inputs 87.1 and 87.2 of switching unit 24, output 88 of register 14, output 89 of register 13, output 90 of switching unit 24, four-bit inputs 91.1 and 91.2 of data, OB 9.1 and 9.2, respectively 92.1 and 92.2 of the input carry, respectively, OB 9.1 and 9.2, four-bit outputs 93.1 and 93.2 of the data OB 9.1 and 9.2, respectively, outputs 94.1 and 94.2 of the result indicators OB 9.1 and 9.2, respectively, outputs 95.1 and 95.2 of the transfer distribution, respectively, OB 9.1 and 9.2, group of outputs 96 synchronization unit 5, multiplexer output 97.1 8 characters Yield 97.2 of first AND-OR 27, the input plate 3 block 98.1, 98.2 input unit 3, the result of feature, information and control 99.1 100.1 25.1 outputs IO where January 1, N, yield

101.1 characters of block 25.1, input 102.1 of the service requirement of block 3, output 103.1 of the decoder 10, output 104 of the second multiplexer 7.

The synchronization unit 5 (FIG. 2) comprises a clock pulse generator 105, a trigger 106, and an AND 107 group of outputs 108.

The matching unit 23 (Fig. 4) contains the first 109.1-109.8, the second 110.1-110.8, the third 111.1-111.8, the fourth 112.1-112.8, the fifth 113.1113 .8, the sixth 114.1-114.8; the seventh 115.1-115.8, the eighth 116.1-116.8 trunk elements, entrances and exit 117-120 trunk elements.

The I / O unit 25.1 (FIG. 6) contains the counter 121, the I / O register 122, the control register 123, the second mode trigger 124, the first mode trigger 125, the start of exchange indication trigger 126 (PNO), the trigger 127, 127, the trigger 128 and 129 controls, the eighth element And 130, the first element And 131, the second element And 132, the third element And 133, the sixth element And 134, the seventh element And 135, the ninth element And 136, the fourth element And 137, the fifth element And 138, the eleventh element And 139, the tenth element And 140, the first element OR 141, the second element OR 142 the element NOT 143, the first 144.1, the second

144.2 and the third 144.3 group entry

254

inputs 96 of the I / O unit 25.1, the first 145.1, the second 145.2, the third 145.3, the fourth 145.4, the fifth 145.5 inputs of the group of inputs 82 of the microoperations of the I / O unit 25.1, output 146 of the N-th bit of the control register 123, output 147 inverse + About th digit of counter 121, output of element 148 I 133, first 149.1, second

149.2, the third 149.3 outputs of the group of codes of codes 52.1 of the input-output unit 25.1, informational inputs 150.1-150.

Operational unit 9.1 (FIG. 3) contains a control decoder unit 152, a first multiplexer 153, a switch 154, a second and third multiplexers 155 and 156, a unit of general purpose registers 157, a buffer register 158, an arithmetic logic unit 159, and first to seventh outputs 160 -166 block 152 of control decoders, first 167 and second 168 outputs of block 157 of general purpose registers, output 169 of arithmetic logic unit 159, output 170 third of its multiplexer 156.

The control decoder block 152 (FIG. 7) of the operation block 9.1 contains the decoder 171 of the sources of operands of the block 159, the decoder 172 of the function of block 159, the converter 173 of codes. The inputs of bits 174.1174 .3,174.4-174.6, 174.7-174.9 of input 79.5 of block 152 form, respectively, groups of information inputs of decoders 171, 172 and converter 173.

Switching unit 24 (Fig. 5) contains a decoder 175, the first 176.1 eighth 176.8 switches.

The time diagram of the operation of the device when executing exchange commands (Fig. 8) shows the numbers of those elements, inputs and outputs of the device, which are necessary to clarify the operation of the device. In addition, the status of the address 4 address on the timing diagram is explained by the following notation: ON - counter 4 records the starting address of the microprogram corresponding to the sample of the first personalized microsystem 1 (1 MK) {+1 is the second executive address (2 MK) The third (3 MK) micro 5 1 command is forged by increasing the content of counter 4 by one. Figures 9 and 10 show firmware flowcharts that contain symbols that determine the order in which the firmware will run. In addition, the following symbols are used in the figures: i.,; , ci, fixed OH 2 cells, in which information is stored respectively, about the low byte and high byte of the counter: the length of the array of data words along the 1st line: exchange direction, where i 4, N, N is the number of subscribers .oi.j. , about (.1- fixed OP 2 cells, in which the low and high bytes of the initial CPU address of the central processor OP information are stored respectively) () i fixed OP 2 cell, which stores information about the fact that a control word was issued to the subscriber; Ge, - Fixed cell OP 2, which stores information about the byte sample (high or low) of the transmitted data word to the subscriber. Consider the assignment of elements, dzl and connections of this device. Constant memory 1 is for storing microprograms, implemented e 30

my device. The input of the PI 1 is supplied with the address of the microcommand from the output 68 of the counter 4 of the address.

At the output 69 of the PP 1, micro-operations are formed that control the block 23. At the output 70 of the PP 1, a control (recording) signal is generated, which, arriving at the input of the element 37, allows the clock pulses from the output 96.2 of the group 96 of the outputs to the synchronization inputs of registers 13 and 14. At output 71 of PCB 1, addresses of OP 2 cells are formed, which are accessed. At output 72 of PCB 1, a signal is addressed to the OP 2 cells. At output 73 of PC 1, a micro-operation signal is generated, which enters the input of the element 32, control recording data in OP 2j and output 74 1 PP signals of external and internal micro; output 75 PP 1 - micro-operations signs of transition having

The following codes:

Symptom Result (Z) 100

Mark Analysis 011

Retractor device, the law of operation of which is determined by the correspondence table.

In tab. 1 shows the states of the turns and outputs of the address generation unit 3, where it denotes the indifferent state of the corresponding input of the device; Tr. obm - signal., The exchange requirement, which is formed on the entrance of 48.1 of block 3, - Tr. 1 - signal Service Requirement, from the 1st subscriber; Etc. US is the control word sign signal; Allow ND - direct access enable signal.

45., pa, Pr. Z - signal Sign of the result (Z), PP - three-bit micro-operations of transition signs, codes and names of which are given above.

50 As follows from table. 1, the block 3 for the formation of the address of the microcosm Zd operates as follows. When exposed to the input 75 of the block 3 micro-operations Sign of the source (code

with zero signals. -If an exchange request signal arrives at the inputs of the address generation unit 3, then its own control outputs 58, 59, 25 Sign of source 000 Sign of microprogram 001 End of microprogram 010 At output 76 of PI 1, a transition address A is generated when the firmware is executed. OP 2 is intended for the temporary storage of information during the operation of the device. It is a static type storage device that can be built on typical integrated circuits. Information input / output of OP 2 is connected to the bus 43 of the high byte of data, from where it arrives at OP 2 and where information is received from OP 2 by commands received at address and control inputs of OP 2 from PP The address generation block 3 is used to form initial addresses microprograms, modifications of the next microcommand address, as well as for generating control signals to multiplexer 6 (outputs 61 and 62). on the counter 4 addresses (exits 61, 63 and 64). The address generation unit 3 is a combination disk 55 0) on the outputs of the unit 3 form 71277

61-64 Block 3 generates control signals (respectively 1,0,1,0,1,0) for which the code of the initial address (the first microcommand) microprogram

exchange (ON MP

) from block outputs

06M.

39 and 40 trunk elements through multiplexer 6 are recorded in the address counter 4.

If the Service Requirement signal arrives at the inputs of block 3, then at its output 60 block 3 forms the code of the initial address of the service microprogram of the subscriber's i-ro (NA MP-), which, according to the control signal, is recorded into the counter 4 addresses. Signal Exchange Requirement has higher priority. If at the time of the firmware execution a Service Request signal is received, then this signal is not perceived until the end of the firmware

When a signal arrives at the input of block 3, the symptom US, block 3 at output 64 generates a single signal that permits the generation of the address of the next (second) micro-command by increasing the content of the counter 5 of the address by one for a clock pulse,

When block 3 arrives at the input, the ND resolution of block 3 generates a single signal at output 64, which, using a clock pulse c, in the counter, forms the lod of the initial address of the direct access microprogram.

If the microprogram Sign of the microprogram and the exchange request signal are input to the block 3, then the outputs 58 and 59 generate single signals that record and modify the current firmware address in register 12 "

Upon arrival at the inputs of block 3 micro-operation. Analysis of the sign and single signal The sign unit 3 generates control signals at its outputs, by which the transition address Angp from the output 76 of the PP 1 through multiplexer 6 is recorded in the counter 4 addresses. If a zero signal is received Sign, then block 3 generates control signals at the outputs, which form the address of the microcommand by increasing the content of counter 4 by one.

Upon admission to the inputs of the unit 3 micro-operations Sign of the result

eight

n single signal Symptom Z unit 3 forms on:. the inputs yIIpcJl lIc e are signals by which the transition address from the output 76 of the PI 1 through the multiplexer 6 is recorded in the counter 4 addresses. If the zero signal arrives. Sign Z, to block 3 generates control signals at the outputs that form the address of the next microcommand by increasing the content of counter 4 by one.

If the microprocessor enters the input of block 3: The end of the microprogram at the output of the latter produces control signals that pass and write the return address code Avo, the output of the register 12 of the current address through the multiplexer f 6 into the counter 4 addresses.

As a gomnotation device, it will function as shown in the table below. 1, the address generation unit 3 may be implemented on a programmable logic array.

Counter 4 of the address is designed to memorize, increment by one and REMOVE the address of the next microcommand. It has an input D of parallel writing of the Address code, a counting input (+1) and a synchronization input C. An address code supplied to input D is recorded in the counter if a clock pulse arrives at its synchronization input. The contents of the counter increase if the pulse arrives at its counting input (+1). Counter 4 addresses works in two modes. If the next address is formed by incrementing the current address by one, the null signal from the output of the AND 28 element goes to the synchronization input, and the next clock pulse from the output of the And 31 element to the counting input of the address 4 counter. input D, then to the counting input of the counter 4 receives a zero signal from the direction of the element And 31, and to the synchronization input is a clock pulse from the output of the element 28.

The synchronization unit 5 (FIG. 2) is designed to form on its outputs 96.1-96.3 three sequences of clock pulses shifted relative to each other, which 91 provide synchronization of the device operation. The trigger 106 serves to control the operation of the synchronization unit 5. The initial state of the trigger 106 is zero. In this case, the zero signal from its output enters the control input of the generator 105. The generator 105 generates at its outputs a series of pulses only if there is a single signal at its control input. Element AND 107 j serves to generate a signal at the zero input of trigger 106 after the arrival of a control signal. End of operation from input 83.2 of block 5c. Synchronization block 5 is triggered by the Start signal, which is fed to input 50. It feeds; the one on the trigger input 106 k sets it to the single state. A single signal at its output trigger 106 starts the generator 105, which starts the fi i and the sequence of sync signals, the sync signal formation continues until 5 until the control signal arrives at the first input of the element 107. End of work. After this, when the next clock pulse from the output 108.3 arrives at the second input element 107, a control signal is generated at the zero input of the trigger 106, which returns to its initial state and removes the control signal from the input of the generator 105. As a result, the generator 105 stops outputting Watch the clock pulse. Multiplexer 6 implements the following logical function: Chi. ,, Yea + AbLb- Y ,, -ь + А ,. Y, Mb-b 1 Hr-g where A „is their address at the output of multiplexer 6; the address formed by the adress address forming unit 3; A is the address coming from the output of the bus 45 data through blocks 39, 40 of the main elements JA (, is the address coming from the output 66 of the register 12 of the current address; A16 is the address coming from the output 76 PP G, 510 61 S 67 control signals generated at the outputs 61 and 62 of the address generation unit 3, respectively.Multiplexer 7 is designed to control the passage of the low byte of the data word coming from the outputs 99.1-99.N of the input / output blocks 25.1-25.N, respectively, and the high byte of the data word from the outputs 88 register 14 depending on the control code from output 78 register 11 microinstructions. Multiplexer 7 implements the following system of logical functions: Y, V, a;, k ;; у, .V ak ;; value of the first where a;, and a. of the eighth digit, respectively, byte of the data word of the i-ro subscriber if in the corresponding bit; output 78 of register 11 is present 1, if O is in the corresponding discharge of output 78 of register 11, y is the number of bits of output 78 of register 11, and 2 - Y - N N is the number of subscribers. The multiplexer 8 characters serves to select the character coming from the outputs 101.1-101.N, respectively, of the I / O blocks 25.1-25.N, depending on the control code at its output 83.1t. The multiplexer 8 implements the following logical function: K M V xk :,;, where x- is the signal value from the lOKi code of the I / O block 25.1. OB 9.1 and 9.2 (Fig. 3) are intended for processing eight-bit data and are an operational block, which can be adjusted according to a typical scheme, for example, on the K1804BC1 microprocessor sections. On the functional diagram of Ch. (Fig. 3) of a typical OB, input 79.3 OB corresponds to the 40th output of the K1804BC1 microcircuit, input 79.4 to the 17-20th output, input 43 - 22 to the 25th pin, input 79.5 - 5-7, 12 -14, 26-28th conclusions, outputs 92.1 and 96.3 - to the 29th and 15th conclusions, outputs 94.1 and 95.1 MPS - to the 11th and 33rd conclusions, output 93.1 MPS - to 36-39th conclusions. Outputs 94.1 and 94.2 are connected at a common point, connected via a resistor to a power source (not shown). The control decoder block 152 (FIG. 7) is designed to control the operation of the OB 9.1. The structure of the block 152 is shown in Table. 2-4. The multiplexer 153 is designed for direct transmission, data shift to the right or left by one bit and transfer them to the inputs of block 157. Control of multiplexer 153 is performed from output 162 of block 152. Switch 154 is intended for switching operands to the first and second inputs of block 159 from four sources: input 43 of data, two sources of block 157 and register 158. The switch 154 is controlled by signals from the output 160 of the decoder (DI) 151 (Fig. 7). The structure of the switch 154 and LH 171 is shown in Table. 2. The multiplexer 155 (Fig. 3) is a third-state multiplexer and is intended for switching data from two sources: output 169 block 159 and output 167 of block 157. This multiplexer is controlled by the output signal 166 block 152 and the signal from the input 79.3. The multiplexer 156 is designed to directly transfer, shift the contents of the buffer register 158 to the right or left by one bit and transfer it to the first data input of the register 158. The multiplexer 156 is controlled from the output 163 of the block 152. The block 157 of the general purpose registers (Fig 3) contains general purpose registers used for storing addresses, data, or const. The address of the first (second) operand is given by signals from input 79.4 (the input of the second operand is not conventionally shown). From outputs 167 and 168 of block 157 to switch 154, the contents of the registers whose addresses are set at output 79.4 are output. Information from the output of multiplexer 153 to block 157 is received to be written to the corresponding registers of block 157. Block 157 is controlled from output 164 of block 152 and from input 96.3. Buffer register 158 (FIG. 3) is intended for intermediate data storage and can be used as a battery. Information can be recorded in register 158 from the output of 170 m of the multiplexer 156 and from the output 169 of the block 159. The register 158 is controlled by control signals from the output 156 of the block 152 and from the output 96.3 ON. In this case, the recording resolution from the output 169 or the multiplexer output 170 comes from the two-bit output 165 of the block 152, and the recording gate from the input 96.3 ON. The arithmetic logic unit 159 (FIG. 3) is intended to perform arithmetic and logic operations in accordance with control signals that are output from output 161. The operations unit 159 performs in one clock cycle. This block is controlled by a decoder 172 (Fig. 7) in accordance with Table. 3. Tab. 3 shows the correspondence between the signals at inputs 174.4-174.6 and the function of block 159 and, therefore, reflects the structure of the decoder 172 and block 159 (FIG. 3), OB 9.1 (FIG. 3) performs a wide range of operations. In one cycle of his work, the operations listed in Table 2 are implemented. 3. Long operations, such as division, multiplication, etc., are performed on microprograms composed of short operations, similar to microprograms used in known devices. The operations of loading and shifting the contents of the registers of block 157 and register 158 are determined by signals at inputs 174.6-174.9 (Fig. 3) in accordance with Table. 4, which describes the operation of the converter 173 codes (PC). The decoder 10 (Fig. 1c) is intended to generate signals at outputs 103.1-103.n controlling responsibly with input-output blocks 25.1-25, N. The micro-command register 11 (Fig. 1a) is used to record the micro-therapy signals 1Y, coming from Alt 74 PP 1. The current address register 12 is used to record and modify the address of the micro-command to be executed when the signal is received. Exchange request from the central processor. Register 12 has information input D, a control input V and a synchronization input C. The code of the current address, arriving at the information input, is written to register 12 on a clock pulse t, supplied to the V input of the register from an output of AND 29.1. Modification of the code of the current address is carried out by increasing the contents of register 12 by one for a clock pulse from the output of the AND element 29.2. The control input and the synchronization input of the register 12 of the Current address correspond to the synchronization input and the counting input of the integrated circuit 533 IE 7, respectively. Registers 13 and 14, respectively, of the lowest and highest bytes of the apo data are used to temporarily store a data word. The device can read the contents of the counter in 16 time intervals by exchange commands in the CPU. When reading the contents of the counter by 16 exchange commands with the CPU, the exchange command can be superimposed on the pulse of the counter modification, which leads to a distortion of the read information. To eliminate this phenomenon, the contents of the counter 16 are read through registers 13 and 14, into which the contents of the counter are recorded by a clock pulse that does not coincide with the pulse of the counter 16 modification. The counter 15 of the starting address is pre-assigned to write to the information input of the addresses of the CPU OU from which is read or written information from the input-output 47 of the device. In addition, according to the clock pulse that arrives at the counting input of the counter 15 of the starting address, the modification of the starting address occurs. If a single signal is present at the synchronization input of counter 15, then counter 15 operates in parallel recording mode, if a zero signal is present at the synchronization input, then the counter operates in modification mode by incrementing the counter content by one for a clock t the input of the counter 15. The 16 time interval counter performs the formation of the CPU clock cycle duration, as well as the formation of various time intervals determining the time of the CPU interrupt signal. The CPU communicates with subscribers in real time. The time service is organized by a 16 time slot counter that operates. in the same modes and can be performed on the same integrated circuits as the counter 15 of the starting address and the counter 4 addresses. The trigger 17 of the sign of transfer (Fig. 16) is used to record the transfer from the output 95.1 of the senior OB 9.1. Triggers 18 and 19 signs of the result, respectively, etadshey and high bytes are designed to record the signal of the result when processing the low and high bytes of the data word. The control trigger 20 is designed to control the operation of the counter 16. The low-pressure trigger 21 is designed to generate an LP signal to the central processor. The exchange control trigger 22 serves to record information that notifies the CPU of the direction of data transmission with the ith subscriber. Block 23 (Fig. 4) is designed to coordinate the operation of the device with the central processor when writing (reading) data in the CPU OU. The first I09.1-109.8 and the second 110.1110 .8 groups of trunk elements serve to form, respectively, the high (16-23rd bit) and low (24-31st bit) bytes of even half-word data received from inputs 56.1 and 56.2 unit 23 through the first and second groups of trunk elements to inputs 57.1 and 57.2 of unit 23, respectively, on the control signal at input 120.1 of the group of inputs when reading data from the CPU OU. Third 111.1-111.8 and quarter 112.1-112.8

The 15 groups of trunk elements are used to form, respectively, the most significant (0-7th bit) and low (8-15th bit) bytes of an odd half-word data received from inputs 56.3 and 56.4 of block 23 when reading data from the CPU OU through the third and the fourth group of trunk elements on outputs 57.1 and 57.2 of block 23, respectively, on a control signal at input 120.3 of block 23. Parallel 113.1-113.8 and a pole 114. 114.8 groups of trunk elements are intended to form, respectively, the high and low bytes of the even half-word data received from inputs 57.1 and 57.2. block 23 when writing data to the CPU OU using the control signal at input 120.2 of block 23. The seventh 115.1-115.8 and the eighth 116.1-116.8 group of trunk elements serve to form the high and low bytes of the odd half-word data received from inputs 57.1 and 57.2 of block 23 when data records in the CPU CPU on the control signal at the input of 120.4 block 23.

Switching unit 24 (Fig. 5) is intended for switching eight-bit data from outputs 99.1-99.N, respectively, of input-output blocks 25.1-25.N, from outputs 87.1-87.2 of counter 15 of the starting address, and also from output 89 of register 13 low byte On the control signal from the output

The first and the eighth bits of the data word decoder from the corresponding block 24 are passed to the output 90 of the block 24 through the switches 176.1176 .8, respectively.

The I / O unit 25 (Fig. 6) is designed to control the output and reception of data words from subscribers, and also autonomously generates the frequency (rate) of the word bit exchange.

The counter 121 is designed to record the code of the number of transmitted bits of a word when it is received and received from the subscriber. The bit width of the counter 121 is determined by the expression n log N + 1, where N is the number of bits of the register 122,

The register 122 I / o is designed to record data words received in parallel code at the input 83 of the unit 25 from the central process27712516

litter and issuing them to the subscriber a serial code from the output 151.N of the register 122. In addition, the register

122 at the DI input

recorded

data words in the serial code from the subscriber and are output from the output 99.i to the central processor in the ftarallective code.

The control register 123 is intended to form the rate of exchange of bits of data words when receiving (transmitting) them from the subscriber. Registers 122 and 123 can operate in write and shift mode. If the V-input registers

a single signal arrives, then the registers operate in the recording mode, otherwise - in the shift mode. The mode trigger 124 is designed to control the mode of operation (recording

or shift) of the I / O register 122 trigger mode 125 - for controlling the operation of the trigger 124 and the register 123. The trigger 126 for the start of the exchange feature generates a signal for exchanging data words between the CPU and the subscriber. The character trigger 127 is intended to store information about the direction of data exchange between the CPU and the subscriber; the trigger 128 controls the temporary storage of the bits of the data received from the subscriber from input 51.1 of block 25.1. A control trigger 129 serves to control the generation of bits of data words to the subscriber.

Element And 130 is designed to form the installation signal to the zero (initial) state of trigger 128 before receiving one bit of the word from the subscriber, And elements 131-133 are for

The control signals are supplied when microoperations from the group 82 of the block 25.1, the control signal from the input 103.1 and the next clock signal arrive at their inputs

pulse from the group of inputs 96 of the block 25.1 I / o. Element And 135 is intended to form a setup signal to the initial state of trigger 125 at the moment of issuing (receiving) the last bit of the data word

element AND 136 — for generating synchronization signals controlling the operation of the subscriber, with a higher (one) bit of the word. Element And 137

It generates a control signal when signals arrive at its inputs from inputs 145.5 and 103.1 of the I / O unit 25.1, and element 138 is a signal.

the synchronization signal of the register 122, the AND 139 element — the bits of the word, the 140 element transmitted to the subscriber — the reset signal of the control trigger 129 at the moment of receiving or receiving the last bit of the word; the counter 121. The element OR 142 is designed to generate the synchronization signals of the register 122; element NOT 143, to form a single signal $ I necessary to autonomously form a bit rate of data words.

Inputs 144.1 144.3 groups of inputs 95 of block 25.1 are designed to supply three sequences of clock pulses shifted relative to each other, respectively tt Г3 j inputs 145.1-145-5 of a group of inputs 82 of block 25.1 - to signal, alo micro-operations controlling the operation of block 25.1, output 146 register 123 for issuing a signal controlling the operation of the proposed input-output channel when issuing (receiving) a word bit.

The output 147 of the counter 121 is designed to output a single when transmitting (receiving) a data word and a zero signal after the end of the transmission (irie-la) of the data word, output 148 jjitMeHTa AND 133 - for issuing a signal of synchronization 127 signs, syntax 147.1-149.3 output groups 52.1 block 25.1. are respectively exits of the sign of the beginning of the exchange, synchronization and information. The outputs 150.1-150.N of register 122 are intended to feed data register from TG1 to parallel register 122 in parallel code. At input 150.N, a sign (direction) of information exchange is given.

The outputs 151.1--151.N are designed to extract the data word in the parallel code from the subscriber 1Д1, Output 151. and serve to output the data word to the subscriber from the CPU in serial code 1

Block 25.1 I / O operates in the following modes: issuing information to the subscriber and receiving information from the subscriber.

The mode of sending information to the subscriber

In the initial state, the registers, triggers and the counter are in the initial (zero) state. Job

starts from the moment when the control signal from the output of the decoder 10 (figure 1) arrives at the input 25.1. Before each data word, the subscriber is always given a control word in which the sign necessarily informs the subscriber about the direction of information exchange. The control word enters the inputs 150.1-150, N of the register

122 and written to it on the falling edge of the clock pulse j, which from the input 144.3 through the elements

Both 138 and OR 142 arrive at the input of register synchronization 122. The sign from input 150.N enters the D input of the character trigger 127 and is written into it on the falling edge of the clock pulse 5, which through the element 133 arrives at the trigger input of the trigger 127. The permissive signals for the passage of a clock pulse (3 through elements 133 and 138 are actual micro-operations arriving at inputs 145.3 and 145.4.

After that, the clock pulse and the micro-operation coming from the input 145.2 set the ITO trigger 126 to one. At the output 149.1 of the group of outputs 52.1 of the block 25.1, a signal of the sign of the exchange to the subscriber is output. In addition, the clock pulse c, from the output of the AND element 132, sets the triggers 129 and 125 to one state, and also passes through the OR element 141, confirms the initial (zero) state of the counter 121. A single signal from the output of the trigger. 125 translates trigger 1-24 into one state and sets register 122 to the shift mode of the previously zapksanny control word.

By clock pulse Tj in regist

123 is written to the low-order bit from the output of the NOT 143 element. The paired unit to the higher bits of the register 123 is performed at the next Clock pulse j after the trigger 125 is set to the initial (zero) state.

On the second clock 1-1Mpulsu Sz triggers 125 and 126 mouths 191

being poured into the original zero state.

When the unit is written to the most significant bit of the register 123, a single signal from the output 146 of the register 123 is fed to the element I 136 and the next clock pulse G enters the output 149.2 of the output group 52.1 of block 25.1. In addition, a single signal from the output of the AND elements 136 through the OR element 142 is fed to the synchronization input of the register 122 and shifts the recorded control word. The information signal from the output 151.N of the register 122 through the element And 139 enters the output 149.3 of the group of outputs 52.1.

A single signal from the output of the element And 136 is also fed to the counting input of the counter 121, which counts the number of transmitted bits of the data word.

A single signal from the output 146 of the register 123, passed through the element And 135, the clock pulse T, (from the output 147 of the counter 121 to the input of the element And 135 receives a single enable signal) is fed to the single input of the mode trigger 125, transferring the last one to one. A single signal from the output of flip-flop 125 allows the unit to be written to the low-order bit of register 123 from the output of the HE element 143. Block 25.1 is ready to issue the next bit of the data word. The output of the next bits from the output 151.N is similar.

When issuing the last bit of data words from register 122, a single signal appears at the single output (n + 1) -th bit of counter 121, which arrives at output 100.1 of block 25.1, indicating that the control word has been output to the subscriber. In addition, a single signal from a single output of the (n + 1) -th bit of counter 121 according to a clock pulse f passes through the AND 134 element and triggers 124, as well as AND 140, the trigger 129 to the initial (zero) state. management

The issuance of the end-of-exchange signal to the output 100.1 of the block 25.1 signals that the data word has been output to the subscriber and the block 25.1 is ready for recording and issuing the next word.

2520

After issuing a control word, data words, but not informational words (IS) are transmitted. Recording and issuing an IP has some special features. When writing an IC on a clock pulse, at the output 145.3 there is no microoperation that controls the recording of the mark; in the trigger 127. According to the clock pulse 6, there is no microoperation at the input 145.2 sign of the beginning of the exchange, but there is a microoperation at the input 144.1, which translates through the element 1311 125 into one state, as well as through the OR element 14, which sets the counter 123 to the initial (zero) state. Subsequently, the recording of the IC in register 122 and sending it to the subscriber is similar to recording and issuing the control word to the subscriber. After the output of the array of ICs is completed, the microoperation of the end of the group exchange enters the input 145.5, which, after passing through the element SH1I14, sets the counter 121 to the initial (zero) state.

Regimen reception mode from abonent.

The I / O blocking mode 25.1 enters the information reception mode after the control word is sent to the subscriber, which sets the subscriber to read the information to input 51.1 of the input-output unit 25.1.

A microoperation arrives at the input 144.1, which, according to the clock pulse t, sets the mode trigger 125 to one state. The signal from the output of the trigger 125 sets the trigger 124 to one. The zero signal from the output of the trigger 124 permits the recording of information (data word bits) input to the register 122 from the output of the trigger 128. The frequency of receiving the bits is determined by input-output unit 25.1 similar to the frequency when the data word bits are higher by shifting the unit in register 123 When a unit appears at the (N - 1) -th output of register 123, a single signal from a given output for a clock pulse f passes through the element I 130 to the zero input of the trigger 123 and confirms its initial (zero) state, preparing the trigger 128 to receive bit data words.

On the next clock pulse (2 units appear on NM output 146 of register 123 and clock 211 through AND 136, the pulse stumbles on output 149.2, synchronizing the word bit from the subscriber to input 51.1. Of block 25.1. At the same time, a single signal from the output element 136 enters the counting input of counter 121 and through element OR 142 at the synchronization input of register 122. As a result, the information bits (nzsh or one) are written to the low-order bit of register 122 from the output of trigger 128. Reception of subsequent bits of the data word occurs in a similar way. cl Va are successively written to the low-order bit of register 122 from the output of trigger 128, and the previously recorded bits are shifted to higher bits of register 122 to those nopj while the single signal at the single output of the (n + 1) -th bit of counter 121 does not show a single signal, arriving at output 100.1 of block 25.1. The following ICs are received in the same way.When receiving the last IC in the array of information words, input 145.5 receives the microoperation of the end of group exchange, which, having passed through elements 13 and 141, sets counter 121 in initial (zero) state ie, preparing it for further work. Switch 26 is designed to switch signals from outputs 79.2 and 79.1 of microcommand register 11 and form an input transfer of low-order OB 9.2 at its output; Switch 27 serves for switching signals of the result when processing data from MilC 9.1 and 9.2. Elements 28-38 are designed to generate control signals that synchronize the operation of the device. The second 39 and third 40 blocks of trunk elements are designed to receive initial microprogram addresses from the CPU data bus 45, KOTO are fed to the input 65 of multiplex 6. The first block 41 of bus arresters serves to output to the bus 46 the address of the SP CPU cell to which appeal Bus 43 of the most significant data byte is used to transfer the most significant (0-7th bit) of the word dAN transmitted between Sch1 and the subscriber. The bus 44 of the low byte of data x is designed to transmit the low byte (815th bit) of the data word transmitted between the CPU and the subscriber. Data data bus 45 (0 31 bits) is used to receive and transmit data from the CPU CPU, 0-7 bit i 8-15th bus bit is used to transmit the high and low bytes of the first (odd) half-word, respectively. . The 16-23rd bits and the 24-31st bits are used to transmit the high and low bytes of the second (even) half-word, respectively. The format of the data word of the OP CPU is equal to two formats of the data words of the subscriber. The address bus 46 serves to transmit the address code of the OP CPU cells. The proposed device consists of two parts: I / O blocks 25.1-25.N. that autonomously generate the word bit rate, receive (word) the word. gyny, and I / O processor ... microprogram control device, OP, operational unit, switching and matching units, etc.), which organizes the initial address and counter counters; how long the arrays, discontinuing, processing (in the case of the need) of information, the management of I / O blocks after receiving (issuing) data words by them, organizing communication with the CPU. The device works as follows. In the initial state, all the triggers, registers and counters of the device are in the zero state, OP 2 is in an arbitrary state, the microinstruction is stored in the zero cell of the PP 1, and from the output 75 PP PP the microoperation of the input and output sets at the output 63 of the record-account and the output 64 of the blocking of the account of the address generation unit 3, zero control signals. Functioning of the device begins with the arrival of the start signal at the device input 50. As a result, the synchronization unit 5 begins to form at the outputs 96.1-96.3 of the group of outputs 96 three sequences of clock pulses shifted relative to each other, respectively - (h.

The ilyjioHhip s. signals from: the drives of b3 and b4 of the address formation unit 3 are received respectively at the inputs of the And 28 and 31 elements. As a result, the clock pulse G is not received at the counting input and the synchronization input of the counter 4 addresses. Thus, a static freeze (SZ) mode is organized, the output of which is the appearance at input 48.1 of the group of inputs 48 of the device signal Exchange Requirement.

The input / output processor (PVV) is configured to exchange data with the corresponding subscriber using the three OBM1-OBMZ exchange commands. In addition to the exchange commands

HAi, (0-15r) HAi RAM CPU (16-31r)

1 HAij (0-15p) Isl (16-31p)

2 HAi, (0-15p) US i (16-31p)

3

OPM 4 HA4 (0-15 where ON i i CPU RAM is the starting address of the array of data words transmitted in the i direction of the exchange and stored in the CPU OP, where i 1, N, N is the number of subscribers. TOBJ

N

number of words

ate data transmitted over the i-th exchange direction; MS; - control word

transmitted to the i-th subscriber;

ON the starting addresses of the corresponding

firmware executed by the input-output processor of the jth exchange command on the ith exchange direction, De i 1, N, j 1,4. Consider the operation of the device when a team of exchanges of the exchange of MBP1 and OBM2 are set up (see Fig. 8).

Data exchange with the CPU is asynchronous. When a signal address is generated at input 48.1 of the block 3, which generates the address of the signal. The exchange request at the outputs 58, 63 and 6.1 of block 3 is formed of single control signals. The control unit ONM1-0 -; M3, GK1 each exchange direction in the counter 16 time intervals of the device by the ONM4 exchange command is recorded a setpoint that determines the duration of the time interval, the end of which is fixed by the interrupt signal, which is the output signal of the device 53. After overflow, the counter 16 is set to the initial (zero) state and for its new start a new MBO 4 command is required by writing the code of the corresponding setpoint. Exchange commands have the following format:

The setpoint code (16-31pX auxiliary signal at output 58 records the contents of the address 4 counter (zero code) in the current register 12 of the address 12 on the clock pulse. inputs-outputs 56.3 and 56.4, blocks 39 and 40 of trunk elements, pass to input 65 of multiplexer 6. As a result, code 1.0 is present at the control inputs of multiplexer 6 (at outputs 61 and 62 of the address generation unit 3, single and zero signals are formed, respectively a) micro start address The program passes through multiplexer 6 and arrives at the information input of the address counter 4. Clock pulse

t from the output 96.1 of the synchronization unit 5, having passed through the element 28 and entering the synchronization input of the counter 4 addresses, writes the initial address of the firmware from the output 67 of the multiplexer 6 to the counter 4 addresses. From PP 1, the first micro-command of the exchange command is selected, which, according to the clock pulse G, is written to the register of 11 micro-commands. As a result, the exchange enable signal is output to output 81.1 of the output device group 55 of the CPU device. In addition, from the output 75 of the signs of the transition of the PP 1 to the input of the unit 3 of the formation, the microoperation is performed. This is a sign of the initial one, which sets zero signals at the outputs 58, 63 and 64 of the address maker 3 address after the removal of the signal. Thus, the transition to the SZ mode of waiting for a signal from the central processor occurs. With the arrival of the signal Signal CSS at the input 48.2 of the group of inputs 48 of the device 48 at the output 64 of the unit 3 of the NIN form of the address, a single control signal is generated that permits the passage of a clock pulse through the element 31 to the counting input of the counter 4 addresses. Counter 4 addresses by clock pulse, forms the executive address of the second microcommand of the exchange command. From output 69 of the PP, 1, microoperation arrives at the input of unit 23, which allows the contents of the 16-31th row of the exchange command to pass from the input-output 47.1 and 47.2 of the device through the data bus 45, inputs-outputs 56.1 and 56.2 of block 23 to outputs 57.1 and 57.2 blocks. 23. At output 70 of PR 1, there is a micro-operation that permits recording on the clock pulse of the 16-23rd bits and 24-31th bits of the exchange command, respectively, in the register 14 high byte and in regis 13 low byte. At the same time, at the outputs; 1, 72, 73 PP 1, control signals are present, intended for recording on the clock pulse 1 high byte (16-23rd bit of the exchange command) from the 43 high bus: its data part to the corresponding SP 2 On the next ity gy pulse. counter 4 is written to the executive address of the third micro-command, which drained bytes (24-31st digit of the exchange command) from the output 89 of the register 13 through the block 24 of the switch1-1I to the bus 43 of the higher part of the clock data and the subsequent write the low byte pulse to the corresponding cell of SP 2 using the clock pulse Tj. The low byte passing through the switching unit 24 is provided by microoperations from the output 78 of the register 11 of the ICoCoMand, coming to the control input of the switching unit 24. Simultaneously with the issuance of microoperations, the output 78 of the register 11,526 from the output 81.2 of the register 11 to the output group 55 of the device receives the signal End of Exchange, signaling the CPU to complete the exchange. In addition, from output 75 PP 1 to the input of the address generation block 3, the microprogram End of microprogram (CIP) J enters which passes the zero code from the current address register 12 through the address multiplexer 6 and writes it to the counter 4 through the next clock pulse 2, , Zero code selects zero cell Ш1 1 and generates at output 75 of signs of transition microoperation Sign of source blocking address counter 4 (see FIG. 8). Thus, transition to NW mode occurs. The device is ready to execute next com anand exchange. The operation of the device when executing the OBMZ and OBM4 exchange commands is similar. Consider the features of the team OBMZ. With the arrival of a signal, the US flag from the central processor resolves the following modification: the code of the address code of the address 4 addresses by the clock pulse D, and block 23 is also opened. In addition, by the clock pulse G, a micro-operation is written to write the high and low bytes to registers 14 and 13, respectively , According to the clock pulse tj at the output 82 of the register 11, micro-operations are performed to select a particular input-output unit 25.1, According to the clock pulse Tj of the microoperation Sign recording and Record the CS from the output group 82 of the register 11 micro-commands record the senior and exchanging the sign byte in the register 122 and input-output block mark 127 25.1 trigger IO, respectively (see Figure 5). At the next clock pulse L, the microoperation Sign of the beginning of the exchange from the input 145.2 of the group of inputs 83 of the block 25.1 is set to one state the trigger 126 of the PSN of the input-output unit 25.1, and also micro-operations are formed at the outputs 71, 72 and 73 of the software 1 for recording mx; ADG byte in OP2. By the next clock pulse, the unit is written to the register 123 of the I / O unit 25.1. From this moment, the block 27 25. i the I / O starts to work autonomously when the data word is output (received) to the subscriber. In addition, the following micro-operations are formed in the same operation cycle: micro-operations from the output 78 of the register 11, controlling the passage of the low byte from the output 89 of the register 13 through the switching unit 24 to the input-output 86 OP2; micro-operations End of exchange and ILC. Consider the features of the operation of the device when executing the CMD4 command. Setpoint code from I / O 57. (16–23 bits) from I / O 57.2 (24–31 bits) via data buses 43 and 44, respectively, enters the information inputs of the counter 16 time intervals. The clock pulse f in register 11 records the second micro-command which, from output 83.3 of output group 83, forms a micro-operation that enters the synchronization input of counter 16, writes the setpoint code to counter 16. Simultaneously, trigger 20 is set to one state. By the next clock pulse 2 in register 11 A third microinstruction is recorded which, at output 83.3, forms a zero signal. From the output of 81.2-register 11 to the group of outputs 55 of the device receives a signal End of the exchange, signaling the CPU to complete the exchange. At the moment of generating the executive address of the third microcommand from output 75 of software 1 to the input of the address generation unit 5, the microprocessor receives a microoperation that outputs zero outputs 61 and 62 of the address formation unit 3 to allow the control signals of the current address to pass through the multiplexer 6, and a single control signal at the output 63 of the driver 3, which, according to a clock pulse, writes the contents of the current address register 12 (zero code) into the address counter 4. The zero signal at the output 83.3 allows the clock pulse to pass through the AND 38 element to the synchronization input of the counter 16, increasing its content by one. In successive clock pulses T, the contents of counter 16 advance until the counter overflows. The overflow signal is fed to the output 53 of the device and simultaneously to the synchronization input of the trigger 20, transferring the latter to the initial (zero) condition. A zero signal from a single output of trigger 20 prohibits the passage of a clock pulse through element 38 to the synchronization input of counter 16. For the new launch of counter 16, the next OBM 4 command is needed. Consider the operation of the device after reading the data word to the subscriber (see Fig. 9) . The signals of the end of the exchange of the word from the outputs 100.1-100.N of the blocks 25.1-25.N are received respectively at the inputs 102.1-102.N of the address generation unit 3. These signals occur asynchronously with respect to the CPU and each other. At the same time, more than one signal at the end of the word exchange can occur at the same time. An I / O processor (UIP) sets the priority between these signals so that at any given time only one service request is processed. Until the end of word exchange signals are taken into account of the UIP, they are stored in I / O blocks. If the UIP is taken by the exchange command or the service firmware of the i-ro I / O unit, where, N-1, then the service demand signal from the I / O unit is not perceived until the current firmware is executed. If the UIP is in the € 3 mode, then the word end signal from the output 100.1, affecting the input of the address generation unit 3, generates at the output 60 of the last the initial address of the service subscriber of the 1st subscriber, where 1 1, N. In addition, at the outputs 61, 62 and 63 of the address generation unit 3, zero and single control signals are formed, allowing the passage of the NA MP through multiplexer 6 and its subsequent recording in a clock pulse into the counter 4 addresses. At the output 75 Ш1 1, a microoperation is formed. Sign analysis, the clock pulse G. At the output 83.1 of the output 83 group of the register 11, the control signals are generated, which arrive at the control inputs of the multiplexer 8 characters and allow

. 29. 1

passing the sign of the exchange from the output 101.1 of the block 25.1 through the mutiplusor 8 to the output 97.1. The signal of the exchange sign from output 96.1 is fed to the input 98.1 of the address formation block 3 K, depending on its value (zero P1i: one), forms the address of the next microcommand either by increasing the contents of the address counter 4 by one, or by recording the transition distance from the outputs 76 PI 1 (symbol 2, fig. 9). If the sign signal is zero (transmission direction corresponds to data transfer from RAM Lp to the subscriber), then at outputs 63 and 64 of the address generation unit 3, zero and one control signals appear, respectively, and the micro address of the control address is generated by moving the contents of counter 4 addresses per unit of clock t,. If the signal of the exchange sign is equal to one (the transmission direction corresponds to the data transfer to the CPU CPU), then the microcommand's executive address is generated by recording the address from output 76 -PP 1, by clock pulse J, while the outputs 63 and 64 of the formation unit 3 are present, respectively single and zero control signals.

Consider the operation of the device when reading data from the OP CPU.

According to the second microcommand of the microprogram of the subscriber's i-ro service (symbol 3), microoperations are formed at outputs 71 and 72 of CPU 1 to access a fixed cell in which the information about the high (0) or low (1) byte of the data word is stored; In addition, the following microoperations are formed in the same microcommand: logical multiplication operation code О The contents of the output cell 79.5 of the output group 79 of the register 11 microcommands; the code of the address of the general purpose register (for example, РОН1), in which the result of adding the contents of O is written by clock: pulse with i microoperation Sign of Z at output 75 PP 1.

If the result of the logical multiplication operation, zero is zero (sign. Byte 0), the trigger 18 is set to one state in the following way530

This impulse Zj e,; the initial signal from the output of 94 o i sign of the divisor ;;; -. that OB 9.1 and 9 o2 through element 34. A single signal from the output of flip-flop 18 passes through switch 27 to output 97.2 and is fed to input 98.2 of block 3, forming single signals (code Ijljl) at outputs 61, 62 and 63 of block 3 to pass and write the address of the transition from the output 76 PP 1 through multiplexer 6 into the counter 4 addresses. The resolving signal for passing a single sign of the result feature through the element 34 and the commander 27 is a zero signal at the output 79.1 of the sign of the group, the outputs 79 of the register 11 micro-commands.

When performing arithmetic operations on data of the usual size (eight bits), the output 79.1 always contains a zero signal, which from the output of the HE element 42. records the result feature in the trigger 18.

According to the third microcommand (symbol 4), the following microoperations are formed: at outputs 7.1 and 72 PP t, at output 80 of register 11 microinstructions to select an I / O unit that has completed the data byte to the subscriber of the high byte; inputs 145.4 and 145.1 of the group of inputs 83 of the input-output unit 25.1 (see FIG. 5),

These microoperations fetch the low byte of the data word from the fixed OP 2 cell and then write it. in block 25.1 input-output.

The fourth microinstruction (symbol 5) performs a logical multiplication of the contents of RON 1 (zero code) with a unit and the subsequent recording of the result of multiplication (unit) into a fixed cell of OP 2. For this, micro-operations are formed at the outputs 79.2, 79.3, 79.4 and 79.5 of the output groups 79 register 11 microinstructions, at the outputs 71, 72 and 73 PP Ij and also at exit 75 PP 1 microprocessor KMP.

If the result (symbol 3) of executing the Logical Fragment operation to zero is not zero (byte sign; 1), then the address formation of the next third microcommand occurs by increasing the contents of the counter 4 addresses by one by incrementing. As a result of the third microcommand (symbol 6), a sample is taken the low byte of the array length counter () oi, 3 is from the fixed 01G2 cell, performing the arithmetic operation of adding the content of the CB, with zero, and storing the result of the addition in the RHON 2. For this, microoperations are formed moves 71 and 72 PP 1, at outputs 79.5 and 79.4 of the group of outputs 79 of the register of 11 micro-commands. A fourth microcommand (symbol 7) samples the high byte from the fixed cell Co (, 1 ;;) performing the arithmetic operation of adding the contents of this cell to zero and writing the result to the RONZ. When the arithmetic microprocessor operations of the microprocessor sections 9.1 and 9.2 are executed with the low byte (symbol 6) the sign of the paranasus of the result of the arithmetic operation is written from output 95.1 OB 9.1 to the trigger 17 of the transfer attribute, while the result sign is written to the trigger 18 to the sign of the low byte result and arrives at the input of block 3 without receipt of a micro-operation. Character Z from output 75 of PS 1. When processing microinstructions with a sign (characters 7 and 8, fig. 9) older than the first byte (output 79 .. 1, there is a single signal) switch 26 for transfer on to: 9.4 OB 9.2 sign of transferring the result of the microcommand over the low byte from output 17, the switch 27 simultaneously switches to the output 97.2 of which the result of the logical multiplication of signals from the triggers 18 and 19 of the signs of the low and high byte results is transmitted about. The signal from the output 97.2 of the switch 27 is fed to the input 98.2 of the block 3 simultaneously with the arrival of the micro-operation Sign Z from the output 75 of the PP 1. Thus, if the counter of the length of the data array was zeroed (Njj 0), then by the fifth microinstruction, the address of which is formed output 75 PP 1, the installation of the counter 123 of the input-output unit 25.1 to the initial (zero) state is performed by micro-operation. The end of the group exchange at the input 145.5 of the group 2532 of the input 83 of the input-output unit 25.1 (symbol 12). In addition, a micro-interrupt is output to the output 81.3 of the group 55 of the device's output 55, and the micro-operation of the microshort of the microprocessor 75 to the output 75 of the PP 1. per unit. The fifth microinstruction (symbol 9) in this case adds the contents of the RON 1 to the unit and places the result of the addition in a fixed OP cell 2 ° the sixth Microcommand (symbol 10) records from the fixed cell I OP 2 low byte of the initial OP address of the central processor (HA OP CPU) in the counter 15. For this, micro-operations are formed at the outputs 71 and 72 PP t and at the output 84.2 of the group of outputs 84 of the register 11 micro-commands. The seventh microinstruction (symbol 11) is written from the fixed OP2 cell to the high byte of the CPU OP in the counter 15 by microoperations at the outputs 71 and 72 PP 1 and the output 84.1 of the register 11 microcommands. In addition, a micro-operation at the output 83.4 of the register 11 sets up a direct access trigger 21, which notifies the CPU from the group of control outputs 54 of the device, that the PIR is ready to receive a data word from the CPU UT. A microoperation is formed. A sign of the initial one, according to which the device enters the Sz mode. Consider the features of the operation of the device when recording data in the OP CPU from the subscriber. When writing data to the CPU OI (see FIG. 9) in the second microcommand (symbol 13), the byte sign is checked in the same way as the byte sign is checked when reading data from the CPU UF (3 character). When data is written into the CPU OU from the subscriber, the reception of information words into the device input-output block is always preceded by the control word being sent to the subscriber. Therefore, the third microinstruction (symbol 14 or 19) checks the contents of the fixed cell oi ,. OP 2 on the fact of issuing a control word to the subscriber. 331 If the cell of the transmitted byte flag is zero and the result of the logical multiplication of the cell contents (the indication of the control word output to zero is zero (the high byte is issued to the subscriber), then the fourth microcommand (symbol 15) is used to sample the second byte of the AC from the OP 2 and write BVV. By the fifth microcommand (symbol 16), the I / O unit is launched to autonomously issue a byte of the data layer to the subscriber 4, the logical multiplication of the contents of RON 1 (the sign of the transmitted byte) by one and the result of the addition in a fixed cell of Oil 2. In addition, a microcooler is formed, which performs the exit to its original state. If it turns out that the control word has already been issued to the subscriber, C, O, 0), then the fourth microinstruction (symbol 17) is performed write to OP2 high byte on the data from the I / O unit. According to the fifth micro-command (symbol 18). A logical multiplication of the contents of ROH 1 by one is made, the result is memorized in a cell (/ 41; OP 2; the I / O unit is launched to autonomously receive the low byte of the data word from the subscriber. In the same micro-command the micro-operation of the ILC is formed. control word byte (oL j 5 O, oii, - 0), then the fourth micro-instruction (symbol 23) starts the I / O unit to autonomously receive the high byte of the data word from the abbent and performs a logical multiplication of the contents of the ROH 4 per unit and memorizing the result in cell The result of the previous third microcommand (symbol 19) is stored in ROH 4. If the lower byte of the data word (c () 1; t 0) has been received from the subscriber, then the low byte and the high byte are written to the cell OP CPU. Respectively, from cells, installation of trigger 21 ND and trigger 22 characters in single states and formation of a micro-operation Sign of the source, which switches the device to the NW mode (symbols 2534 20-22). The output from the SOC mode is effected by a signal from the CPU. Resolution of the ID. Consider the operation of the device when recording data in the OP CPU (see Fig. 10). When a signal is received, the resolution of the ND at the input 48.3 of block 3 results in the formation at the outputs 63 and 64 of the latter, respectively, of the zero and single signals. According to the clock pulse o, the executive address of the first microcommand (symbol 13) of the memory direct access memory program is generated when data is written to the CPU RAM. The first microinstruction simultaneously issues the data of the high and low bytes to the bus 45 bytes of the word danns. The high byte is selected from the OP2 cell to the output 56.1 of block 23 via the high byte bus 43. The low byte from the output 99.1 of the I / O unit 25.1 through the multiplexer 7 enters the bus 44 of the low byte and then through the block 23 to the output 56.2 of the block 23. Thus, the 16-bit data word is output to the bus 45 data and his subsequent entry in the OP 1SC at the address recorded in the counter 15 and issued to the bus 46 addresses for micro-operations at the output 84.4 of the group of outputs 84 of the register 11 micro-commands. The second (symbol 14) and third (symbol 15, 16) microcommands check the array length counter (cells oi., OP2) for overflow and set the ND trigger to its initial state. If all the words in the 1st exchange direction are transmitted - O, then the input-output unit is transferred to the initial state of micro-operations. The end of the group exchange at the input 145.5 of the group of inputs 82 of the input-output unit 25.1. In addition, a microoperation is formed. Interruption on output 81.3 of the register of 11 micro-instructions and the ILC at output 75 of PI 1. The result of adding otil; with the unit, it is stored in the RHONE 2, and the result of adding with zero is stored in the ROH 3 (symbol 22). If it turned out that not all words are transmitted by 1 O, then in the fourth micro-command, the counter 15 is modified by a 1/3 clock pulse and micro-operations at 35

during 84.3 groups of outputs 84 of register 11, as well as the launch of the input-output block (symbol 17).

According to the fifth and sixth microcommands (respectively, the squabbles 18 and 19), the low byte and the high byte of the counter 15 are recorded through the switching unit 24 into the corresponding fixed OP2 cells.

On the seventh micro-command (symbol

20) the contents of the RHONE 2 is placed in the cell foii of the low byte of the array length counter OP 2.

According to the eighth micro-command (symbol

21) the contents of the RONZ is placed in the cell Syj J of the most significant byte of the array length counter OP2 and the microcooler is formed.

The address of the CPU slot of the CPU is determined by the counter 15. The counter width is determined in such a way that the low-order bit of the counter 15 does not arrive at the address input of the CPU OP. This allows you to save the address of the OP CPU cell during the issuance (reception) of two 16-bit data words to the subscriber. The format of the data word of the OP CPU is equal to the two formats of data words to the subscriber. Two cjfoBa data from the subscriber or to the subscriber is written (read) to one even or odd address, depending on which initial address was loaded into counter 15. For example, the initial address recorded in counter 15 is 00000000. The increase in the content of counter 15 is not leads to a change in the address of the OP CPU cell, since the address code is 0000000t. The first bit is equal to 1 and the remaining seven bits are stored in the value of O. Thus, two data words from the subscriber will be recorded (read) at address 0000000. In the following, counter code 15 will be 00000010 and data words from the subscriber will be written to address 0000001.

Reading data from the CPU CPU when executing the firmware direct access memory is similar to

(

data records in the CPU OP (see symbols 4-12, Fig. 10).

In the code for the implementation of the subscriber service firmware, the signal may be received. The exchange request to the input 48.1 of the address generation unit 3. In this case, at outputs 58 and 59 of block 3, single

12536

control signals that record the P modification of the address of the current microcommand, respectively, according to the clock pulses b, and c. The address of the interrupted firmware through multiplexer 6 is recorded in the address counter 4 and the execution of the interrupted firmware continues.

The operation of the device is terminated after a micro-operation. but

Claims (1)

Invention Formula A device for data exchange between a computer and subscribers, containing two multiplexers, a sign multiplexer, an address counter, a permanent memory, a microcommand register, a high byte register, two operational blocks, a random access memory, a signal level matching unit, a synchronization block address generation, decoder I / O group, direct access trigger, exchange control trigger, control trigger, three blocks of trunk elements, three AND elements, the inputs required exchange, control word tag and direct access access of the ad1) econ forming unit are connected to the control bus of the electronic computing machine, the first and second informational outputs of the signal level matching unit are connected to the information inputs and outputs of the high and low byte of the first computer The third and fourth information inputs / outputs of the signal level matching unit are connected to the information inputs / outputs of the high and low bytes of the second of halfword elektronnovychislitelnoy machine output of the first block of the main elements is connected to the address bus elektronnovychislitelnoy maoshny, the first group of information outputs of the microinstruction register, the output latch of direct access, exchange of the control flip-flop output being connected to the control bus electron-calculator 71 The first information inputs and outputs of the group I / O units are connected to the information outputs and inputs of the group subscribers, the trigger input of the synchronization unit is the device start input, the first and second information inputs of the signal level matching unit are connected to the information inputs of the second and third blocks of trunk elements, respectively, whose information inputs are connected to the first information input of the first multiplexer, whose information output is connected to the information the second input of the address counter, the information output of which is connected to the address input of the permanent memory, the first information output of which is connected with permission; the input of the signal level matching unit, the fifth information input of which is connected to the second information input of the input / output blocks, with the information input of the register the high byte, with the information input / output of the RAM and with the information inputs and outputs of the first and second operating units, address inputs, operation code inputs and inputs Controls which are connected to the corresponding bits of the second group of information outputs of the micro-register register, a third group of information outputs of which are connected to the group of control inputs of the second multiplexer, whose information output is connected to the sixth information input-output of the signal level matching unit, the information input of the second multiplexer is connected the information output of the high byte register, the sync input of which is connected to the output of the first element I, the first input of which o is connected to the second information output of the fixed memory, the third information output of which is connected to the address input of the operative memory, the resolution input of which is connected to the fourth information output of the fixed memory, the fifth information output of which is connected to the first input of the second element which is connected to the input of the memory record, the sixth information output of the permanent memory is connected to the information input of the register23 8 An array of microinstructions, a source of information on a data link is connected to the information input of the decoder, the output group of which is connected to the corresponding input (I; o input unit resolution) blocks of code conditions that are connected to the fifth group of information output registers microinstructions, the pole of the group of information outputs of which is connected to the enable input of the synchronization unit, a single control trigger input, to the single and zero inputs of a direct access trigger a, with single and zero inputs of the exchange control trigger and with the group of control inputs of the sign multiplexer, the group of information inputs of which are connected to the outputs of the sign of the group I / O units, the outputs of the service demand coors are connected with the group of inputs of the address maintenance request for services, information the output of which is connected to the second information input of the first multiplexer, the third information input of which is connected to the seventh information output of the permanent memory, the eighth information This output is connected to the input of the code conditions of the address generation unit, the first and second address outputs of which are connected to the first and second control inputs of the first multiplexer, respectively, the control inputs of the second and third blocks of trunk elements, and the control trigger input of the device , characterized in that, in order to increase speed, the current address register, the low byte register, the switching unit, the time interval counter are entered into it fishing, two elements AND-OR. high byte result flag trigger, low byte result flag trigger, transfer flag trigger, initial address counter, nine AND elements, NOT element, the output of the time interval counter is connected to the control trigger synchronous input and connected to the interrupt input of the electronic computer; The second information outputs of the I / O units of the group are connected 39 with the group of inf (the second multiplexer inputs and the group of information inputs of the switching unit, the first information input which is connected to the information output of the registrable byte register, the information input of which is connected to the information output of the second multiplexer and the first information input of the time interval counter, the second information input of which is connected to the information output of the operational memory, with the information output of the switching unit, with the first and the second information inputs of the start address counter, the second and third information inputs of which are connected to the first and second information outputs of the account The initial address block, respectively, also with the information input of the first block of trunk elements, the control input of which, the first input of the third element I, the first and second synchronization inputs of the count of the initial address are connected to the seventh group of information outputs of the microinstruction register, the third group of information outputs are connected to the control group the inputs of the switching unit, the group of synchronous inputs of the I / O units of the group is connected to the first, second and third outputs of the synchronization unit, the first output of which It is connected with the first inputs of the fourth, fifth, and neck of the And elements, the second output of the synchronization unit is connected to the synchronous input register of microinstructions with the first inputs of the seventh and eighth And elements, to the second input of the first element And, the output of which is connected to the sync input of the lower byte, the third output the synchronization block is connected to the clock inputs of the first and second operational blocks, with the second inputs of the second and third elements And, with the first inputs of the ninth and tenth elements And, with the first input of the eleventh element And, the output of which is connected to the counting input of the time interval counter, whose synchronization input is connected to the second input of the eleventh element I and to the single input of the control trigger, the output of which is connected to the third input of the eleventh element And, the third and fourth address 2540 outputs of the address generation unit are connected to the second inputs the fifth and sixth elements And respectively, the outputs of which are connected to the synchronous input and the counting input of the address counter, respectively, the information output of which is connected to the information the second input of the current address register, the information output of which is connected to the fourth information input of the first multiplexer, the synchronous input and the enabling input of the current address register are connected to the outputs of the seventh and fourth elements And, respectively, the second inputs of KOTopbiXi are connected to the fifth and sixth address outputs of the address generation unit, respectively, the inputs of the sign and the sign of the result of which are connected to the outputs of the multiplexer of the sign and the first element I-IPI, respectively, the second group of information outputs reg The country of microinstructions is connected to the first and second inputs of the second AND-OR element, the second input of the second AND-OR element is connected to the first inputs of the first AND-OR element, the twelfth AND element, and the input of the HE element, the output of which is connected to the second inputs of the first AND element OR, the eighth and ninth elements And with the third input of the second element I-SHIII, the output of which is connected to the transfer input of the second operating unit, the transfer output of which is connected to the transfer input of the first operational unit, the transfer output of which is connected to the second the input of the tenth element AND, the output of which is connected to the single input of the transfer sign trigger, the output of which is connected to the fourth input of the second AND-OR element, the outputs of the indication of the result of the first and second operating units are connected to the third input of the ninth AND element and to the second input of the twelfth element And, the outputs of which are connected to the single inputs, respectively, of the trigger sign of the result of the lower byte and the trigger sign of the result of the high byte, the zero inputs of which are connected to the zero input of the trigger n iznaka transfer and output of the eighth AND gate, the high byte of the result of feature trigger output connected to a third input of the first AND-OR, fourth and fifth 411277125А2 the inputs of which are connected to the output of the ment and are connected to the counting sign of the result sign by the younger counter of the initial address. byte, the output of the third eles. Table 1. Signals at the LH 171 Sources (input) signals at the outputs of the switch 154 167 Register output 158 167 168 Table 4 lpU2.fu ig. IS (Rig, 2 W.f F H .P ) Bf.i : "L X - X /and/ fffl.S / "F .З 23 HO.i 57.1: i /. f U / " 11S.1P Iis.  tli.s -fcn m. / to Ll s pl P. ifl.i R , 120.1 sh.z 69 120.1 -A With tfaw / 7g) ) KaHut ddpft and ffunponoHoHba 1  ) cmaño6kcl mpuzi   Data recording   bol or ttdcrmufujl W1N1N # C1 Y-- | y:; y / -. i7 ND 6 original / 5-1 jarit - AJtfJ I lg / 77 PiiS. W