SU1566362A1 - Multichannel device for control information exchange in computing system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of fault-tolerant computing systems. The aim of the invention is to increase the reliability of operation. The device contains a block of memory of micro-commands 1, a buffer storage unit 2, a block of memory channel number 3, a block 4 of associative memory, an address register 5, a register of micro-commands 6, a synchronization block 7, a control unit 8, an address switch 9, an output switch 10, comparison circuits 11, 12, logical conditions multiplexer 13, multiplexer 14, demultiplexers 15, 16, input register 17, AND unit 18, channel number 19 register, AND element 20, OR elements 21, 22, OR element unit 23, single vibrators 24.1 , 24.2, entry 25, start of operation, entry 26 of the operation code, informational entry s 27, 28, input 29 of the failure sign of the previous channel, input 30 of logic conditions, output 31 of the operating part of micro-instructions, output 32 of the failure sign, information outputs 33, 34, input 35 of the sign of failure of the subsequent channel of the device. The goal is achieved by providing reconfiguration in case of failures. 1 hp ff, 9 ill.

Description

The invention relates to computing and can be used in the construction of fault-tolerant control and computing systems.

The purpose of the invention is to increase the reliability of operation.

Figure 1 shows the functional diagram of the 1st (JNf) channel of a multi-channel device; figure 2 is a functional diagram of the buffer storage unit; FIG. 3 is a functional block diagram of the control; figure 4 is a functional diagram of the synchronization unit; in Fig.5 a, b are formats of micro-commands for information processing and micro-commands for exchange; figure 6 is an example of the structural organization of a multi-channel device; Fig. 7 illustrates an exemplary implementation of an associative memory block; Fig. 8 shows the temporal diagram of the work of the channel in the modes of processing its own microinstructions and issuing microcommands of the exchange; -figure 9 is a diagram of the channel in the mode of reception and processing of micro-commands of the exchange, as well as in the mode of modification of the micro-command of the exchange.

The multichannel device for exchanging control information in a distributed computing system contains channels, and the i-th (iI.N) channel (Fig. 1) contains block 1 of microprogram memory, buffer storage unit 2, block 3 of memory of channel number, block 4 associative memory, address register 5, register of 6 microinstructions with the fields: 6.1 - code of logical conditions; 6.2 - modified address bit; 6.3 - unmodifiable code

address bits; 6.4 - surgical floor; 6.5 - check mark of parity; 6.6 - the end of the firmware; 6.7 - transfer of control, synchronization unit 7, control unit 8, address commutator 9, output switch 10, first 11 and second 12 circuits. Neni, multiplexer 13 logical conditions, multiplexer 14, first 15 and second 16 demultiplexers, input register 17, block of elements AND 18, register 19 of the channel number, element AND 20, first 21 and second 22 elements OR, block of elements OR 23, first 24.1 and the second 24.2 one-shot,

input 25 of start of operation, input 26 of operation code, first 27 and second 28 information inputs, input 29 of the failure sign of the previous channel, input 30 of logic conditions, output 31 of the operational part of the microcommand, output 32 of the failure sign, first 33 and second 34 information outputs, input 35 sign of failure of the subsequent channel, Buffer storage unit 2

(Fig. 2) contains a block from K (where K is the depth of the service queue) of registers 36.1 - 36, K, multiplexer 37, demultiplexer 38, block from (K-1) -th switch 39.1-39.K-1, block of elements And 40, block of elements And 41, block of elements OR 42, one-shot 43, information output 44 of block, block of elements And 45.1 - 45.К, element And 46.

The control unit 8 (FIG. 3) contains the first 47, the second 48 and the third 49 modulo two, the failure trigger 50.

ten

The synchronization unit 7 (FIG. 4) contains a trigger trigger 51, a clock pulse generator 52, a counter 53 and a decoder 54.

The information processing microcommand format (Fig. 5a) contains the code of the checked logical condition X, the unmodified address bit of the address An, the code of the unmodifiable address bits A n, the code of the operating part (04), the parity of the information 1TL, the end of the microprogram MC,

The difference in the format of the exchange micro-command (Fig. 56) is that the operational part of the micro-command is divided into three subfields - channel numbers, recipient of information Ac, microprogram number MMk) channel numbers - source of information Mn,

The associative memory unit 4 (FIG. 7 represents a programmable logic array and contains two sub-arrays containing two blocks of resisors, two blocks of elements HE 55.1-55.f, 25 and 56.1-56.p.

The device works as follows.

The operation of the device is possible in four modes: the mode of processing own microcommands; mode of issuing the exchange exchange commands; the mode of reception and processing of microcommand exchange; modification of microcommand exchange.

Since in a multichannel device, channels are identical and can work20

15

thirty

35

independently, then the operation of the device is considered on the example of the operation of a separate channel.

In the initial state, the channel memory elements are in the zero state (with the exception of register bit 6, which defines the microprogram feature - field 6.6). Before starting the operation, the memory elements are set to the zero state (zero circuits are not shown in FIG.

In block 3, a code is recorded that identifies the location of the channel in a device constructed as a ring structure based on channels of the same type. This code is a channel identifier.

Channel operation in the processing of own microinstructions.

The operation of the channel in this mode of operation begins by submitting to the input 26 an operation code defining the address of the first microcommand micro0.

five

0

management programs. Simultaneously with the filing of the operation code, the input of the channel 25 (Fig. 1) is given an impetus to start operation. This signal through the OR element 21 sets the trigger 51 of the block 7 (FIG. 4) to one state and thereby enables the formation of pulses for synchronization of the channel operation.

Since at the output of the comparison circuit 11 (Fig. 1) there is a logical zero signal, this signal permits the passage of the opcode from input 26

5 through the multiplexer 37 to the information input of the demultiplexer 38 of block 2 (FIG. 2), a register is a sign of the end of the microprogram from the output of register 6 to the control input of block 2. This tag is fed to the control input of the first 40 and second 41 blocks of AND elements and determines the procedure for recording information in register 36.1 or passing through a block of OR elements 42.

Since the block of registers 36.1-36. K (Fig. 2) is in the zero state, the outputs of the elements 45.1-45. There are signals of a logical unit arriving at the control input of the demultiplexer 38 and defining the distribution of service incoming codes of firmware number by register as the queue of block 2 is filled,

Received information through the de-multiplexer 38, the block of elements And 40 and the block of elements OR 42 transit through the block 2 (figure 2)

Q through the address switch 9 to the information input of the register 5 and but to the first clock pulse from the output of block 7 (Fig. 1) the received information is entered into the register 5. Occurs

5 access to memory block 1.

On the trailing edge of the second clock pulse, the read micro-command, the format of which is shown in Fig. 5, a, is entered in register 6 (Fig. 1).

0 The operational part (04) of the microcommands from the output of field 6.4 of register 6 through the block of elements And 18 enters the output 31 of the channel to control the corresponding operational block, for example, an arithmetic logic unit (ALU).

Paul 6.1-6.3 register 6 form the address of the next microcommand using the multiplexer 13. Multi0

five

The plexer 13 is designed to form the value of the modifiable bit address of the next microcommand according to the value of the signals at its information inputs (field 6 „2 register 6 and logical conditions from input 30 of the device) and control input (field 6„ 1 register 6).

During the execution of the firmware from input 26 to block 2, clock codes from the output of block 7 can be entered with the codes of numbers of the next firmware (operation codes).

As control information is issued to the channels, it is monitored by block 8 (FIG. 3). In this case, both the address and the operating parts of the microcommand are monitored using the parity check method. If one of the codes is distorted or the address of the selected microcommand does not match, block 8 generates a channel failure signal by setting trigger 50 to one state (Fig. 3).

The sign of channel failure from the output of block 8 through the OR element 22 enters the control input of block 7 (FIG. 4) and sets the trigger 51 and the counter 53 to the zero state. The generator 52 stops generating pulses to synchronize the channel and ends the channel.

The sign of channel failure also goes to the output 32 of the channel to transmit information for subsequent reconfiguration of the outputs of the previous one and the inputs of the subsequent channels (Fig. 6). This is necessary to eliminate the failed channel and transmit the exchange micro commands, mine the failed channel.

The reconfiguration of the structure is achieved by the fact that the signal from the output 32 of the 1st channel is fed to the input 35 of the (i-l) -ro channel. The micro-commands for the demultiplexer 16 arriving for transit transmission are directed not to the 1st channel, but to (1 + 1) -th. The control signal of the 1st channel failure comes from the input 29 (i + 1) -ro channel (Fig. 1) to the control input of the multiplexer 14. The transit information is received from the (i-1) -th channel, and not. from the failed 1st channel.

The channel works in the mode of issuing micro-commands of exchange.

During the processing of microinstructions, the device channel may issue a mic, -

.

mQ

- 20 25

Jq) 40

d5, -p

55

Rokomandy exchange other channels of the device, forming a ring structure. The format of microcommand exchange presented in figure 5, b. In this case, the operational part of the micro-command - field 6.4 of register 6 forms the micro-command of the exchange

m l Ј M 4 M io with r L1 ms t 11n

Where Ac is the code (number) of the channel of the information receiver; Mmk-code (number) of the firmware that should be performed by the ac channel of the device; M p - code (number) channel information transmitter; F is the sign of concatenation (concatenation) of the individual syllables of the microcommand exchange.

Simultaneously with the code of the micro-command of the exchange M0 from the output of field 6.7 of register 6, a control transfer indication is issued. This label arrives at the control input of the switch 10 and permits the exchange microcommand to pass to the information input of the demultiplexer 16. Depending on the state of the next (1 + 1) -th channel (in a healthy state or failure state), information is output (iH ) -My or (1 + 2) th channels. Simultaneously with the release of information (exchange microcommand), a clock pulse is output to record information in the subsequent channel of the device.

The tag-indication of the transfer of control from output 6.7 of register 6 enters the inverse control input of the block And 18, thereby prohibiting the issuance of control information from field 6.4 of register 6 to the output 31 of the channel.

Further, the channel can either form to issue an exchange micro-command in the next micro-command, or it can continue processing the microprogram similarly to that discussed earlier.

The channel operation in the mode of reception and processing of micro-commands of exchange.

Depending on the status of the previous channel, the exchange micro-command comes either from the input 27 of the channel or from the input 28 to one of the information inputs of the multiplexer 14 (Fig. 1).

Simultaneously with the arrival of the exchange micro-command, a clock pulse arrives. This pulse allows entering the received information (exchange micro-command) into register 17, sets via OR 21 trigger 51 (FIG. 4) of block 7 to one state, which allows generation of clock pulses for synchronization of the channel operation. In addition, by the incoming clock pulse, the memory unit 3 is accessed, in which a single code is stored that identifies the location (number) of the channel in the device structure

The identifier read from memory 3 is stored in register 19.

The exchange micro-command code recorded in register 17 consists of three parts: the code of the channel of the receiver of information (Ac), the code of the microprogram number (Mmc), which you must

complete the corresponding channel of the device and the code of the channel of the source of information (Mn).

The code of the channel number of the receiver of information from the floor of the register 17 is fed to the input of the comparison circuit 11, where the comparison with the code (identifier) of this channel takes place. Since the code of the channel of the source of information in the comparison circuit 12 did not coincide with the channel identifier, the information from the output of the demultiplexer 15 added to the code of the channel of the source of information through the block of elements OR 23 and the switch 10 depending on the state of the subsequent (i + 1) A channel channel is provided to one of the outputs of the demultiplexer 16 and one of the outputs 33 or 34 channels, followed by the channel of the device.

When the code of the channel of information receiver coincides with the identifier of this channel, a signal of a logical unit is generated at the output of the comparison circuit 11. This signal is fed to the control input of the multiplexer 37 (Fig. 2) of block 2 and thereby permits passage of the firmware number code (Mmc) from the output of the register field 17 (Fig. 1) to the information input of the demultiplexer 38 (Fig. 2) for recording the corresponding register register block 36.1-36.K and its subsequent processing in the order of incoming requests in the same way as it is considered.

When issuing the last microinstruction in field 6.6 of register 6, the end-of-microprogram sign is inserted. This label from the output of the register 6 is fed to the control input of block 2 (FIG. 2) and generates a single pulse at the output of the one-shot A3, which, entering the control inputs

15

20

25

thirty

35

.with

40

0

five

mutators 1Q.1-39, K-1, thereby allowing the rewriting of information in block 36.1-36 K registers. When a clock pulse arrives from the output of block 7 to the clock inputs of registers 36.1-36. The information is shifted (overwritten). The single-oscillator 43 is set to the initial (zero) state, and thus the unit 2 is ready to receive the firmware for servicing.

The operation of the channel in the mode of modifying the microcommand exchange.

When the device is in operation, a situation is possible in which, when transmitting information (exchange micro-instructions) to the j-th channel, its failure is possible. In this case, the exchange micro-command, the failing channel mine, returns the source of information to the channel through the device’s ring structure and enters the register 17.

The comparison circuit 12 compares the channel identifier and the source code, and when they match, forms a signal of a logical unit. This signal from the output of the comparison circuit 12 is fed to the control input of the demultiplexer 15. Information about the code number of the information receiver and the firmware code from the outputs of the register fields 17 through the multiplexer 15 is fed to the input of block 4.

Unit 4 is made in the form of a programmable logic matrix (Fig. 7) and performs the role of a code converter, modifying the code of the channel number of the receiver in which the failure occurred. This achieves the transfer of control (exchange microcommand) to the channel, in the memory block of which copies of the failed channel firmware are stored. Modified code of the receiver's channel number together with the code of the firmware number and supplemented with the code of the source information channel number from the output register floor 17 through the block of elements OR 23, the switch 10 is fed to the information input of the demultiplexer 16 and depending on the (i + 1) -ro status of the channel either output 33 or channel output 34 is output.

Next, the device operates in the considered modes.

The end of the channel operation is as follows.

First, in the event of a channel failure, the signal from the output of block 8 through the OR element 22 enters the input of the zero setting of the trigger 51 (Fig. 5), sets it to the zero state, and the channel terminates.

Secondly, after the queue of block 2 is empty (no firmware number codes for servicing), the output of the element 46 (Fig. 2) is a signal of a logical unit. This signal from the output of block 2 is fed to the input of element AND 20, and when issuing a register 6 of the 6 microprogram end mark from the 6.6 register 6, the one-shot 24.2 generates a pulse and a logical unit signal from the output of element 20 through the element OR 22 sets the trigger 51 ( Fig. 4) of block 7 to the zero state; The channel is shutting down and ready to receive regular information.

Claims (2)

1. A multichannel device for exchanging control information in a computing system containing N channels, and in each channel — a microprogram memory block, a synchronization block, a buffer storage block, a control block, an address switch, an address register, an input register, a micro-command register, a multiplexer logic conditions, channel number memory block, channel number register, first comparison circuit, AND5 element block, AND element, two OR elements, and the first information output of the i-th (i 1, N-1) channel is connected to the first information input ( 1-th) device channel, the output of the address switch is connected to the information input of the address register, the output of which is connected to the information input of the microprogram memory unit and the first input of the control unit, the output of the control parity of the address register is connected to the second input of the control unit, output the microprogram memory register is connected to the micro-command register information input, the output field of the logic conditions code of which is connected to the control input of the multiplexer logic conditions, the output of the modifier bit register of micro-commands is connected to the first information input of the multiplexer logical conditions, the field output of the unmodified address register bits of the micro-commands is connected to the unmodified address bits of the first information input of the address switch, the output field of the register of micro-commands is connected to the information input of the AND block whose output is connected to the output the operational part of the channel microinstructions, the output of the logical conditions multiplexer is connected to the input of the modified bit address of the first about the information input of the address switch, the outputs of the code fields of the logic conditions, the output of the modifiable and non-modifiable address bits, the outputs of the operating field of the micro-command register are connected to the third input of the control unit, the output of the parity check sign of the micro-commands register is connected to the fourth input of the control unit whose output is connected to the output the sign of channel failure, the first control input of the channel start is connected to the first input of the first OR element, the output of which is connected to the trigger input of the syn block synchronization, the first output of which is connected to the synchronization input of the buffer storage block, the output of the channel number memory block is connected to the information input of the channel number register, the output of which is connected to the first input of the channel number register, the output of which is connected to the first input of the first comparison circuit, the output of the first circuit comparison is connected to the input selection source of information buffer storage unit, the output of the first field of the input register is connected to the second input of the first comparison circuit, the second output of the sync block connected to the synchronization input of the address register, the third output of the synchronization block is connected to the synchronizing input of the micro-register register, the input of the channel logical conditions is connected to the second information input of the logical conditions multiplexer, the fourth output of the synchronization block is connected to the control output of the channel with the first information input of the buffer storage unit, the output of the sign of the junction of the micro-register of micro-commands is connected to the direct and the inverse control inputs of the address switch, the output of the AND element is connected to the first input of the second OR element, the output of which is connected to the stop input of the synchronization unit, the output of the control unit is connected to the second input of the second OR element, the information output of the buffer storage block is connected to the second information input of the switch address, the output of the sign of the end of the queue of the buffer storage unit is connected to the first input of the element I, the output of the second field of the input register is connected to the second information input The house of the buffer storage unit, which is due to the fact that, in order to increase the reliability of operation, each channel additionally contains an associative memory block multiplexer, two demultiplexers, an output switch, a second comparison circuit, a block of OR elements, two single vibrators, and the first information output N-ro channel is connected to the first information input of the first channel, the second information 0 the first OR element, the control input of the channel number memory, the synchronization input of the input register and, through the first one-shot, with the synchronous input of the channel number register, the output of the channel number register connected to the first input of the second comparison circuit, the second input of which is connected to the output of the third field of the input register , the output of the second comparison circuit is connected to the control input of the first demultiplexer, the first output of which is connected to the first input of the block of OR elements, the second output of the first demultiplexer is connected to the input the house of the associative memory block, the output of which is connected to the second input of the block of the OR elements, 0 the output of the OR block is connected to the first information input of the output switch, the outputs of the first and second fields of the input register are connected to the information input of the first demultiplexer, the output of the third floor of the input register is connected to the first and second inputs of the block of micro-commands connected to the second 5 35 40 the output of the i-th (i 1, N-2) channel connects the information input output of the output to the second information input of the (i + 2) -ro channel, the second information output of the (N-1) -th channel is connected to the second information input of the first channel, the second information output of the N-ro channel is connected to the second information input of the second channel, the output of the sign of failure of the i-th (, N-1) channel is connected to the input of the sign of failure of the previous channel (i + 1) -ro channel and the input of the sign of failure of the subsequent channel (i-1) -th channel, the output of the sign of failure of the first channel is connected to the input of the sign of failure n Previously, the channel of the second channel and the input of the sign of failure of the subsequent channel N-ro channel, the output of the sign of failure of the N-ro channel is connected to the input of the sign of failure of the previous channel of the first channel and the input of the sign of failure of the subsequent channel (N-1) -ro channel, the first and second information - the inputs (i-th (i 1, N) of the channel are connected respectively to the first and second inputs of the multiplexer, the output of which is connected to the information input of the input register; the bit of the timing attribute of the multiplexer output is connected to the second input the switch, the output of the sign of the end of the microprogram microprogram register is connected to the shift enable input of the recorded information of the buffer storage unit and through the second one-vibrator to the first input of the And element, the output of the indication of the supply of the control of the microcommand register to the And block of the direct and the first inverse control inputs of the output switch, the output of which is connected to the information input of the demultiplexer, the output of the first circuit is compared to the second inverse control The output input of the output switch, the input attribute of the failure of the previous channel is connected to the control input of the multiplexer, the input sign of the failure of the subsequent channel is connected to the control input of the second demultiplexer, the first and second outputs of which are connected to the first and second information outputs of the channel, the fourth output the synchronization unit — with the clock discharge of the information input of the second demultiplexer. 2. The device according to claim 1, from l and 50 55  output information input the switch, the output of the sign of the end of the microprogram microprogram register is connected to the shift enable input of the recorded information of the buffer storage unit and through the second one-vibrator to the first input of the And element, the output of the indication of the supply of the control of the microcommand register to the And block of the direct and the first inverse control inputs of the output switch, the output of which is connected to the information input of the demultiplexer, the output of the first comparison circuit is connected to the second inverse control The output input of the switch, the input sign of the failure of the previous channel is connected to the control input of the multiplexer, the input sign of the failure of the subsequent channel is connected to the control input of the second demultiplexer, the first and second outputs of which are connected respectively to the first and second information outputs of the channel with the clock of the information input of the second demultiplexer. 2. The device according to claim 1, from l and This is due to the fact that the buffer storage unit contains a block from K registers, where K is the depth of the service queue, a block from (K-1) -th switch, a block from K elements I, a multiplexer, a demultiplexer, two blocks of elements I, a block the OR elements, the AND element and the one-shot, the output of which is connected to the direct and inverse control inputs of the unit's switches, the first and second information inputs of the buffer storage unit are connected to the corresponding information inputs of the multiplexer, the output of which is connected to the information input the multiplexer, the inverse output of the P-th register of the block is connected to the inputs of the P-th element I of the first block (P 1, K), the output of which is connected to the Pm control input of the demultiplexer and the Pm input of the element I, the output of which is connected to the output the sign of the end of the queue of the buffer storage block, the synchronization input of the buffer storage block is connected to the synchronization inputs of the block registers, the input selection source of information of the buffer storage block is connected to the control input of the multiplexer, the write enable resolution information of the buffer storage unit is connected to the one-shot input, the direct control input of the second block of elements And and the inverse control input of the third block of elements And whose output is connected to the first information input of the first switch of the block, the output of the second block of elements And is connected to the first input of the block OR elements, the output of which is connected to the information output of the buffer storage block, the output of the first register register of the block is connected to the second input of the OR element block, the first input of the demultiplexer is with information inputs of the second and third blocks of elements And, -and output (, K-1) of the demultiplexer is connected to the first information input 0 -th switch of the block, the output of which is connected to the information input of the ith register of the block, K-th output of the demultiplexer is connected to the information input of the K-th register, the output of the j-th register (j 2, K) of the register block is connected to the second information input (j-1) -ro of the switch, the output of the first switch of the block is connected to the information input of the first register of the block. FIG. five / Ls-sss ///////// / 7 /////// ////// FIG. 6 fiyo.7 czzЈ - basic exchange VZZZfy - exchange in case of refusals ch X П п п ПДПП0. LNAP A J0DL0 at i Ј-l I  i FIG. eight A J0DL0P at i Ј-l x X