SU1580382A1 - Device for data exchange in distributed computing system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-performance computing systems, vector, matrix and conveyor processors. The purpose of the invention is to expand the field of application due to the possibility of information exchange in a matrix distributed computing system in two directions. For this, the device has additionally introduced channel selection block 2, multiplexer 7 and demultiplexer 9. Introducing these elements and the connections generated by them allows you to organize vertical and horizontal pipelines in a matrix computing system, which, in combination with the cyclical organization of these pipelines, allows for efficient, in terms of hardware office expenses, data exchange between all elements of the matrix computing system. 7 il.

Description

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The invention relates to computing and can be used in the construction of high-performance computing systems, multiprocessors with a dynamic architecture, microcontrollers with multiple flow control commands for organizing wave, systolic, matrix, and conveyor processes.

The aim of the invention is to expand the field of application of the device by providing the possibility of information exchange in a matrix distributed computing system in two directions.

The firmware executed by the device consists of two submultiple operating microcommands (nano commands M and M "with Mt L Mg 0. The first type of nano commands (M) is designed to control the operating unit. During the execution of the microprogram, the device can issue to a similar device a nanocomand of the second type ( Mj), forming a subset of the nano command transmission control.

The format of the nano-command transfer control is represented as

m "

where t „p is the number (code) of the modular device - the receiver of information; m R - the number (code) of the firmware that the device must execute - the receiver (the starting address of the firmware); F - a sign of coupling. turn

m

Yar

m g

where m and m are, respectively, the address codes of the device location in the matrix of similar devices of the distributed system.

Each device included in the distributed system is assigned its own number (identifier). The devices forming the system are combined into a double ring system by a row of system devices and a column of system devices. This organization is the interaction of individual

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five

system devices allows you to organize a full exchange between devices.

A nano command transfer control from an ij-ro device (i 1, go, j 1, n, where type is, respectively, the number of devices in the matrix horizontally and vertically) goes to (i + 1) je device, which determines whether information is intended for it . The determination of the ownership of information occurs by comparing the device code as the receiver of information in a nano command to transfer control with the code identifying the device. If these codes do not match, the incoming information is sent horizontally to the (i + 2) j-My device, and so on until the codes match horizontally. When horizontal codes match, information is sent around the vertical ring until the codes match.

When the codes match, both horizontally and vertically, information about the firmware number is stored in the buffer storage unit. The control information can be entered into this block both from the system devices and from the supervisory block (for example, the central processor). The processing of information from the buffer storage unit is carried out according to the rule: first come, first served (organization like F1FO).

FIG. 1 is a functional diagram of a device for exchanging data in a distributed computing system; figure 2 is a functional diagram of the channel selection block (BVK); on fig.Z - functional diagram of the buffer storage unit; figure 4 is a functional diagram of the synchronization unit. (BS); FIG. 3 is a functional diagram of a logical conditions multiplexer; Fig. 6 shows the formats of micro-instructions stored in the memory block of micro-instructions; Fig. 7 shows an example of the organization of a distributed control system built on the basis of devices of the same type. . A device for exchanging data in a distributed computing system (FIG. 1) contains a block of 1 memory of micro-instructions, a block 2 of channel selection, a buffer storage unit 3, a block 4 of synchronization with outputs 4.1-4.5, a register 5 of address, a register 6

microinstructions with the code field of the checked logical condition 6.1, the modified address bit 6.2 with the field of unmodifiable address bits 6.3, the transaction field 6.4, also the fields of the transfer control sign 6.5 and the end of the microprogram 6.6, the multiplexer 7, the multiplexer 8 logical conditions, demultiplexer 9, address switch 10, input of logic conditions 11 of device, first 12, second 13 and third 14 information inputs of device, control input 15 of device, operational output 16.1 of device, second output 16.2 demultiplexer The first 17 and second 18 data outputs of the device.

In addition, the device contains (Fig. 1) the third informational 19 and the control 19.1 outputs of the channel selection unit 2, the information 20 and the control outputs 21 of the buffer storage unit.

Block 2 channel selection (figure 2) contains the first 22, second 23 and third

24 buffer storage blocks

25 constants with fields 25.1 and 25.2 defining the composite location code of the device for exchanging data in the distributed system horizontally and vertically, de multiplexer 26, command register 27, counter 28, block OR elements 29, first 30 and second 31 decoders,

the first 32 and second 33 comparison schemes, the AND 34 element, the OR 35 element, and the delay element 36. In addition, the device comprises (FIG. 2) the control inputs 37-39 of the corresponding buffer storage units 22-24.

The buffer storage unit 3 and the first to third buffer storage units of the channel selection unit 2 (FIG. 3) contain a block of registers 40.1-40.N (where N is the queue depth), a block of information switches 41.1-41.N- -1, the first 42 and the second AND 43 blocks of elements, the block of synchronizing switches 44.1-44.N, the third block of elements AND 45.1-45.N-1, the element AND 46, the block of elements OR 47.1-47.N, - a single vibrator 48 and a synchronizing input 49

The synchronization unit 4 (FIG. 4) contains a trigger trigger 50, a clock pulse generator 51, a counter 52, a decoder 53, a first 54 and a second 55 And elements,

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The multiplexer 8 logical conditions (figure 5) contains the multiplexer 56 and the element OR 57.

The purpose of the main units and device elements is as follows.

Block 1 of the memory of micro-instructions is intended for storing a variety of micro-instructions M M LM2. h

The channel selection unit 2 is designed to analyze the information received in order to determine the direction of further transmission in one of three directions: to the processing of this device, for transit transmission in the ring of transmission devices horizontally, for transit transmission in the ring of devices vertically.

The buffer storage unit 3 is intended for storing codes (numbers) of microprograms received for servicing by this device.

The synchronization unit 4 is designed to synchronize the operation of the device.

Multiplexer 7 is designed for switching incoming requests from the supervisor or from one two-direction cheese (horizontal or vertical).

The de-multiplexer 9 is intended for switching the nano-command to control the operating unit and for issuing the control command to the n-command.

The purpose of the main elements of the channel selection block (Fig. 2) is as follows.

The first to third buffer storage units 22-24 are intended for the temporary storage of incoming for - analysis of messages from the own device and from adjacent to the left and bottom of the modular matrix devices, forming respectively the horizontal and vertical conveyors (Fig.7).

The constant memory unit 25 is designed to store a code identifying the location of the device in the matrix of devices for data exchange in a distributed computing system.

The block of elements OR 29 is designed to store the transmission of messages stored in blocks 22-24 for their analysis of the ownership of information on the first 32 and second 33 comparison schemes.

The counter 28, the decoder 30 and the element And 34 are designed to organize the survey and read information from the buffer storage blocks 22-24.

The demultiplexer 26 is designed to switch the message after analyzing it from three directions: either to its own device, or to horizontal or vertical conveyors.

Command register 27 and delay element 36 are designed to synchronously issue commands to one of the three directions of information transfer.

A device for exchanging data in a distributed computing system can operate in two modes: in the mode of implementing its own firmware or in the mode of receiving and processing commands.

Before starting operation, the memory elements of the device are in the zero state (with the exception of the register register 6 micro-instructions, field 6.6 of which defines the end-of-microprogram sign (Fig. 1).

The firmware starts operation by applying start-up pulses c to the control input 15 of the device. The first pulse C., the trigger 50 of the start of the synchronization unit 4 (Fig. 4) is set to one. The generator 51 starts producing clock pulses that arrive at the counting input of the counter 52 and the V input of the decoder 53. At the decoder 53, the clock pulses 2 arrive at the output 4.1 of the synchronization unit 4 and are fed to the synchronous input of the address register 5. From the second output of the decoder 53, the clock pulses Cj are fed to the input of the element 55, closed with a zero signal from the control output 21 of the buffer storage unit 3 (Figures 1, 3 and 4). From the third output of the decoder 53, the clock pulses Ј are fed to the input of the register 6.6 of the microcommands of the I 54 element closed by a single signal at the output. From the fourth output of the decoder 53, the clock pulses pass to the output 4.3 of the synchronization unit 4 and then to the synchronous input of the channel selector 2. The sync pulses п with the second output of the decoder 53 are passed to the output 4.4 of the synchronization unit 4 and then to the second synchronization input of the channel selection unit 2 and the synchronization input of the buffer storage unit 3 (Fig. 1). In addition, sync

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the pulses U translate into the zero state trigger 50. With the arrival of the next start pulse C, at the input 15, the operation cycle of the synchronization unit 4 is repeated.

The device, in the implementation mode of its own firmware, begins to operate when the operation code arrives from input 14 to the information input of multiplexer 7 (Fig. 1), at the control input of which there is a zero potential. This signal comes from the output 19.1 of channel selection block 2, the memory elements of which are in the zero state (Fig. 2). The operation code from input 14 is fed to the information input of the buffer storage unit 3 and to the input of the switch unit 41.1-41.N-1, as well as to the input of the block of elements And 42. At the same time, a single signal from input 49 of the information input of the buffer storage unit 3 is set to the inputs of the switches 44.1-44.N and closes the elements And 4j.1-45.N-1 and the element And 46. Zero potentials from the outputs of the elements And 45.1-45.N-1 lock the switches 44.1-44.N-1. Thus, when the first clock pulse arrives

& from the output 4.4 of the synchronization unit 4, the latter passes through the open switch 44.N to the synchronization input of the register 40.N. In this case, the operation code is entered into the register 40.N, to the information inputs of which it passes through a switch 41.N-1 opened by a zero signal at the output of the one-vibrator 48. As a result, a single signal appears at the output of the OR 47.N element, which is installed at the inputs of the AND 45.1-45.N-1 elements, opens the AND 46 element and passes to the output 21 of the buffer storage unit 3.

From the output 21 of the buffer storage unit 3 (Fig. 1), a single signal passes to the input of the synchronization unit 4 (Fig. 4) and opens the element And 55 for passing the clock pulses. from the second output of the decoder 53 to the output 4.5 of the synchronization unit 4. A single signal from the output of the field 6.6 of the register 6 passes through the open element I 46 (FIG. 3) and opens the block of elements AND 43 In this case, the operation code from the outputs of the register 40.N passes through the block of elements AND 43 to the output 20 of the buffer storage unit 3. C

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the output 20 of the buffer storage unit 3, the operation code passes through an open single signal in the field 6.6 of the register of 6 micro-commands the address switch 10 to the input of the register 5 of the address (FIG. 1). According to the clock pulse Ј from output 4.1 of the synchronization unit 4, the operation code is entered into the address register 5. The initial address of the firmware from the output of the register 5 address goes to the address inputs of the microcommand memory block 1. At the outputs of the micro-instruction memory block 1, a first micro-instruction is formed. The sync pulse Ј from output 4.5 of sync unit 4 zeroes the register of 6 micro-instructions. As a result, a single signal from the output of field 6.6 of the register of 6 micro-instructions is removed. In this case, the element AND 54 is opened (Fig. 4) and the clock pulses Ј + are passed to the output 4.2 of the synchronization unit 4. Besides

element I 46 is closed and a single impulse is formed at the output of the one-shot 48 (FIG. 3). This signal locks the block of elements AND 42 and the block of switches 4t.1-41.N-1 through the information input of the buffer-storage unit 3, the block of switches 41.1-41.N-1 is opened through the outputs of the corresponding registers 40.i (i 1, N ) and through the open switch box 44.1-44.N, the registers 40.1-40.N are synchronized. As a result, information is shifted by one register in the buffer storage unit 3. According to the first clock pulse Сn from the output 4.2 of the synchronization block of the microcommand of format A (Fig.6), it is entered into the register of 6 microcommands.

The floor 6.1-6.3 of the register of 6 micro-commands forms the address of the next micro-command using the multiplexer 8 (FIG. 5) of logical conditions. The multiplexer 8 logical conditions is designed to form the value of the modifiable address bit address of the next microcommand and recapitutes a logical function of the form

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xt a +

xt zf + x3z2 +

+ ... +

xMzfc

Where

- the output signal of the multiplexer 8 logical conditions;

ten

- CONJUNCTION

"and

the corresponding combination of output 6.1 of the code of logical conditions allowing the modified address bit to pass unchanged;

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X j -e OjOfj. . . "I

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. .. / t - conjunctions corresponding to the codes defining the output of multiplexer 8 of one of the logical signals

CONDITIONS Zj, Z2, ...,

input 11 logical conditions of the device.

The code of the checked logical condition from the output of field 6.1 and the modified address bit from the output of field 6.2 of register 6 together with the logical 5 conditions at the input 11 of the modular device enter the multiplexer 8 of logical conditions (if the microcommand is a branch microcommand). From the output of the latter, the modified address bit, together with the address at the output of field 6.3 of the register of 6 microcommands, passes through the open address 0 of the field 6.6 of the register of 6 microcommands, the switch U of address to the inputs of register 5 of address. Micro-operations from the outputs of field 6.4 of the register of 6 micro-commands using the zero signal in the field 6.5 of the register of 6 micro-commands pass through demultiplexor 9 and arrive at output 16.1 of the micro-operations.

Then, after restarting, sync-Q on input 15 of the device

pulse

to the next clock pulse

address

the next micro-instruction is entered in the address register 5 and the operation of the device is repeated. If, during the execution of the firmware, operation codes enter at device 14, which must be implemented after the current firmware has been executed, they are recorded in the order received in the buffer storage unit 3. The first operation code is entered into register 40.N. A single signal from the output of the element OR 47.N passes to the output 21 of the buffer storage unit 3 (FIG. 3), closes the switch 44.N and opens the element And 45.N-1,

eleven

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at the output of which a single signal is generated. This signal opens the switch 44.N-1.

Upon receipt of the next operation code, the input of the buffer storage unit 3 is synchronized with% & the latter is entered in register 40.N-1. The remaining registers of the buffer storage unit 3 are filled in the same way. Writing to the register 40.1 takes place when there are single signals from all the OR 47.1 + 1 - 47.N elements at the input of the AND 45.1 element and the zero signal at the OR 47.1 element output. At the end of the implementation of the firmware in the register of 6 micro-instructions, the micro-command of format B is entered (Fig. 6). A single signal from the output of the field 6.6 of the register of 6 micro-commands switches the address switch 10 to receive the operation code from the buffer storage unit 3, is fed to the input of the synchronization unit 4, prohibiting the formation of sync pulses {. at output 4.2 of synchronization unit 4, and is fed to the read input of the buffer storage unit 3. At the same time, at the information output 20 of the buffer storage unit 3, the next operation code is generated, which passes through the address switch 10 to the input of the address register 5. In the next clock pulse Cr at the output 4.1 of the synchronization unit 4, the operation code is entered into the address register 5 — and the device continues its operation in the same way.

The mode of receiving and processing commands is implemented in a modular device when commands of format D are received at inputs 12 and 13 of the device and when register in register 6 of micro-commands of micro-commands of format C (Fig. 6). In the latter case, in the field 6.5 of the register of 6 micro-instructions, there appears a single signal that goes to the control input of the demultiplexer 9. At the same time, the D format command from the outputs of field 6.4 of the micro-command register 6 passes through the demultiplexer 9 to output 16.2 to the same-name input of the block ka 2 channel selection. Commands format D with inputs 12 and 13 are received at the same inputs of block 2 channel selection. According to the sync pulse S from the output i4.3 of the block 4, the synchronization of the command from the inputs 12 and 13 and the output 1J.2 of the demultiplexer 9 are entered into the corresponding buffer storage units

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12

22-24 block 2 channel selection (figure 2). The design and operation of the buffer storage units 22-24 is similar to the buffer storage unit 3 (FIG. 3). As a result, single signals appear at the control outputs of the respective blocks 22-24, which form at the output of the element OR 3.5 a unit potential. This signal opens the element 34. At the same time, in accordance with the zero code at the output of the counter 28, a single signal from the output of the decoder 30 is fed to the read input of the buffer storage unit 22. The command from the information outputs of the buffer storage unit 22 passes through the block of elements OR 29 and goes to the information input of the demultiplexer 26. In addition, the horizontal component of the address command is format D (Fig. 7) is fed to the input of the comparison circuit 32, to the second input of which the horizontal address of the device arrives Exit-keeping a floor 25.1, a memory unit 25 konstanty.Vertikalna component is input to the comparison circuit 33, the second input of which is supplied to the vertical address of the device from the output unit 25 memory constants. If the two addresses in the circuits 32 and 33 of the comparison coincided, then the signals at the output of the decoder 31 demultiplexer 26 sends the subcommands to the input of the register 27 commands. Then, according to the delayed by the delay element 36, a clock pulse O, the instruction code is entered in the register field of the 27 instructions. If the coincidence occurs only according to the comparison circuit 32, then using the signals of the decoder 31, the demultiplexer 26 transmits the command code to the input of the command register 27, which is entered in the register field 27 of the commands. If a match occurs only in the comparison circuit 33, then the command is entered in the register field of 27 commands. If the addresses in the circuits 32 and 33 do not match, then the command code is entered in the register field 27 of the commands. Next, the command codes from the outputs of the register fields of 27 commands are passed to the outputs 17 and 18 of the module, respectively. The command codes from the output, the register field 27 are passed to the output 19 of the start selection block 2 and fed to the multiplexer 7 of the same name. The control bit of the command from the output 19.1 of the channel select block 2 is fed to the control input of the multiplexer 7. The operation code commands from the output 19 of the channel selection block 2 are transmitted through multiplexer 7 to the information input of the buffer storage unit 3. The sync pulse C1 is entered into the buffer storage unit 3. The same clock pulse in block 2 channel selection is increased by. nitsu the counter 28 (Figure 2). At the same time, a single signal is generated at the output of the decoder 30, which allows sampling and analysis of the command from the buffer storage unit 23. After restarting on input 15 with o1 clock, the sync pulse of the next microcommand is entered into address register 5, and the device continues in the same way . Thus, the reception and processing of coma-nd occurs simultaneously with the execution of the current firmware. I

The device closes at the end of the supply of sync pulses to input 15 of the modular device. In this case, the trigger 50 (Fig. 4) remains in the zero state, and the generator 51 stops forming the sync pulses.

Claims (1)

Invention Formula A device for exchanging data in a distributed computing system, comprising an address switch, an address register, a microinstructor memory block, a microcommand register, a logic conditions multiplexer, a synchronization block and a buffer memory block, the first input of the synchronization block being the control input of the device, the first and second the outputs of the synchronization unit are connected to the synchronization inputs of the address register and the register of microinstructions, respectively, the third and fourth outputs of the synchronization unit are connected to the first control yuschim input buffer memory unit and the input of the installation floor microinstruction register respectively, the first and second outputs of the microinstruction register connected to a first data input and a control input of the multiplexer logic conditions, five 0 five 0 five 0 five 0 five respectively, the second information input of the logical conditions multiplexer is the input of the logical conditions of the device, the output of the multiplexer of logical conditions and the third output of the micro-command register are connected to the first and second information inputs of the switch, respectively, the output of the address switch is connected to the information input of the address register, the output of which is connected to the address the input of the memory unit of the firmware, the output of which is connected to the information input of the microcommand register, the fourth output of which connected to the control input of the address switch, the second input of the synchronization unit and the second control input of the buffer storage unit, the control output of which is connected to the third input of the synchronization unit, the information output of the buffer storage unit connected to the third information input of the address switch, characterized in that in order to expand the scope of application by providing the possibility of information exchange in a matrix distributed computing system in two directions, the device neighbors a demultiplexer, a multiplexer and a channel selection unit, the fifth and sixth outputs of the command register are connected to the information and control inputs of the multiplexer, respectively, the first output of the demultiplexer is the control output of the device, the second output of the demultiplexer is connected to the first information input of the unit channel selection, the second and third information inputs of which are the first and second information inputs of the device, respectively, the third and fifth outputs of the synchronization unit are connected to the first m and the second control inputs of the channel selection unit, respectively, the first and second information outputs of the channel selection unit are the first and second information outputs of the device, respectively, the third information output and the control output of the channel selection unit are connected to the first information input and control input multiplexer, respectively, the second multiplexer information input is the third in12 I FIG. 7 Vertical conveyor