SU1462328A1 - Device for interfacing digital computer with communication lines - Google Patents

Abstract

The invention relates to computing and can be used to interface computers with common bus type interfaces with consecutive communication lines, combining digital computers and subscribers into information-measuring and automated control systems. The purpose of the invention is to expand the field of application by enabling the software to control the exchange protocol and increasing the reliability. The device contains three transceiver units, a control unit, a random access memory unit, three comparison nodes, a switch, a register of read information, a register of recorded information, an address switch, a reversible serial to parallel converter, a mode register, a register of flags, a write address counter for the recorded information, a counter the read address of the recorded information, the counter of the address of the read information, the register of the end of the array of written information ff. 1 .p. f-ly, 5 ill.

Description

one

The invention relates to computing and can be used to interface computers with common bus type interfaces with serial communication lines, for example, Manchester II, the union. . Our digital computers and subscribers in information-measuring and automated control systems.

The aim of the invention is to expand the scope of application by providing the ability to programmatically control the exchange protocol and improve reliability.

Figure 1 shows the block diagram of the proposed device; Fig.2 is a functional diagram of the third transceiver unit; in fig. 3 is a functional diagram of a reversible serial to parallel converter; in fig. 4 is a functional block diagram of the control unit; Fig. 5 shows a timing diagram for recording information into an operational storage unit from a communication line.

A device for interfacing a digital computer with communication lines (FIG. 1) contains a register of 1 modes, a register of 2 flags, a switch 3 of address, a register of 4 recorded information, a register of 5 readable information, a reversible converter 6 of sequential code

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in parallel, transceiver blocks 7 and 8, switch 9, control block 10, transceiver block 11, write record write address counter 12, read write address counter 13, write information storage register 14, record information end register 14, operative counter 15 a storage unit 16 and three nodes 17-19 (equal,

i Block 11 transceivers (figure 2) Contains three main receivers 10

7 transceivers and a switch 9, are fed to the first input of the shift register 26, to the third input of which signals are output from the generator 28, which carry out random recording of the received information. Each word contains sync (first three bits) v information part (16 bits) and even parity bit (20th bit).

From the second output of register 26, the received word .in the parallel code enters the analysis node 24

, 1 1 i -it Л & Ч L. v ..-..- ..j ----. Transmitter 20-22 and selector 23 address- 15 bits of parity and synchromending, which contains the decoder synchrophase-, counter and control circuit parity. The sync decoder of the first state and the last three bits 20 of the shift register 26 generates a signal to prevent exchange with the digital computer, which is held until all the received word is written to the shift register 26. On the signal front

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; Reversible converter 6 in series of code into parallel co-Jerzhit (Fig. 3) tkeTHOCTH bit analysis node 24 and sync piloting, timer 25, | The register 26 is shifted, the node 27. for framing the parity bit and the synchronicity, the generator of 28 clock pulses and is made on the basis of the BIS 388 VG6.

ry contains a synchro-descrambler, a counter, and a parity check circuit. The sync decoder of the first state and the last three bits 20 of the shift register 26 generates a signal to prevent exchange with the digital computer, which is held until all the received word is written to the shift register 26. On the signal front

The control unit 10 (FIG. 4) contains 25. The exchange prohibition with the digital computer is triggered by two groups of elements AND 29 and 30, Element AND 31, elements NOT 32-35, Elements I 36 and 37, elements OR 38-40 And triggers 41 and 42.

The device works as follows.

After powering up, by a signal from a digital computer, the device is reset, with the register of 1. modes, register 2 flags, counter 15, all elements of the inverter 6 of serial code into parallel, except the generator 28 clock pulses triggers. 41 and 42 of the control unit 10, and the meters 12 and 13 are set to one.

If the digital computer to which the device is connected is slave, then it

The ger of the beginning of the reception of the register of 2 flags and the trigger 42 of the control block 10, the output signal of which blocks the flow of control signals from

30 outputs of groups of elements And 29 and 30 of the control unit 10. The signal from the output of the control unit 10 to the input of the recording of the SDA 16 is cut by a signal cut, which receives the received word from the output of the register 5 into the OZB 16 at the address specified by the counter 15, After writing the received word into the OZB 16 the counter will automatically increase to 40 volts. unit.

B, the shift register 26 continues to receive the read information, parity bit analysis node 24 and sync pad periodically generate

after the installation signal is sent to the source, the Exchange is locked to the digital computer and the readout state is written through block 11 to mode register 1, the control word code that puts the device into receive mode, and the address switch 3 connects to the address inputs of the operational storage unit 16 the outputs of the counter 15, and the switch 9 connects the information output of, for example, the transceiver unit 7 to the serial code input of the converter 6,

Accepted on the first line of communication information, for example, in the form of an array of twenty-bit words through the block

This information is recorded in OZB 16. Timer 25 of transducer 6 analyzes the pauses between successive signals. It prevents the exchange with the digital computer. If the specified pause exceeds the duration of the synchrotrolling, then timer 25 generates the Unblock exchange signal from the DVR, the front of which is triggered by the trigger 42 of the control unit 10 control55

laziness and the trigger is raised End of reception of the register of 2 flags.

The contents of the counter 15 captures the amount of received information. Readable information may be

7 transceivers and a switch 9, are fed to the first input of the shift register 26, to the third input of which signals are output from the generator 28, which carry out random recording of the received information. Each word contains sync (first three bits) v information part (16 bits) and even parity bit (20th bit).

From the second output of the shift register 26, the received word .in the parallel code arrives at the analysis node 24

Bit parity and sync, which contains a synchro decoder, a counter and a parity check circuit. The sync decoder of the first state and the last three bits of the shift register 26 generates a signal to prevent exchange with the digital computer, which is held until all the received word is written to the shift register 26. On the signal front

The exchange prohibition with the digital computer is triggered The exchange prohibition with the digital computer is triggered by the start of receiving the register of 2 flags and the trigger 42 of the control unit 10, the output of which blocks the flow of control signals from

outputs of groups of elements And 29 and 30 of the control unit 10. The signal from the output of the control unit 10 to the input of the recording of the SDA 16 is cut by a signal cut, which receives the received word from the output of the register 5 into the OZB 16 at the address specified by the counter 15, After writing the received word into the OZB 16 the counter is automatically incremented by one.

B, the shift register 26 continues to receive the read information, parity bit analysis node 24 and sync pad periodically generate

Signal barring exchange with digital computer and readout Signal barring exchange with digital computer and readable information is recorded in OZB 16. Timer 25 of transducer 6 analyzes the pauses between successive signals of Interchange bar with digital computer. If the specified pause exceeds the sync sending time, then timer 25 generates the Unblock exchange signal from the DVR, the front of which is triggered by the trigger 42 of the control unit 10 control 5

laziness and the trigger is raised End of reception of the register of 2 flags.

The contents of the counter 15 captures the amount of received information. Readable information can be, fill5 .1

Both the entire volume of the HZB 16 and some of it are limited to the Address Edge of the Information Information Zone (CC s), which is installed externally at the first input of the comparison node 19, for example by soldering jumpers. For operation in the mode of limiting the amount of information readable, the digital computer registers the corresponding control word in register 1 of the modes, as a result of which a resolving potential appears at the input of the AND 37 element of the control unit 10. If, after the next word of the readable information is written to OZB .16, the contents of counter 15, which is fed to the second input of the comparison node 19, become equal to SR SI, then the output of the comparison node 19 shows a signal 1, which will go to the second input of the register 2 gov - a message from the digital computer about filling the allowed zone of the information to be counted, and a signal will be sent to the input of the element 37, forbidding the most impulse to write the read information to the OZB 16,

The reading of information in the digital computer from the OZB 16 is performed in the reverse order of the recording order, t, e. OZB 16 in this case works in stack mode. Each word is read in two steps. At the first stage through the main transceiver 20 block. 11 in the digital computer, the next word address is counted (the contents of counter 15 from the switch 3 address outputs.) and two service bits — a sync clock type bit and a read word parity check bit (from the OZB 16 information outputs), then through the main transceiver 22 of the block 11 in the digital computer are counted 16 bits of the information part of the word, after which the contents of the counter 15 are automatically reduced by one.

The digital computer, analyzing the address of a word, independently determines the moment of the end of reading a specific array of information. Reading in the digital computer of the register of 2 flags occurs through the main transceiver 21 of block 11 and is independent of the mode of operation of the device. After each reading, the register of 2 flags automatically zeros.

Before B1 1, the recording of the ground information is also in a communication line, for example, an array from a digital computer must be recorded in OZB 16, Dn of this from a digital computer

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The cut block 11 is written to the mode register 1, is written. The corresponding control word by which the switch 3 addresses connects the counter outputs 12 to the address inputs of the OZB 16. Next, from the digital computer, word by word, in order of communication, is recorded in the OZB 16 an information array. After each Q word is written, the contents of counter 2 are automatically reduced by one. Before the information in the communication lines from the digital computer via block 11 to the register

The modes of the record are the corresponding control word, according to which

the address switch 3 connects to the address inputs of the OZB 16 outputs of the counter 13, Next, an address code is written to the counter 13 through the digital computer via block 11

20 of the beginning of the array of information to be issued, and in register 14, the code of the address of the end of the output array of information is written, respectively. Actually in-line information

25 communication is performed automatically by the device. The digital computer only initiates the start of automation; Dp of this, from the digital computer, the command Start 1 ZI is given, which physically represents

30 the process of reading in the digital computer from the secondary security system 16 of the first word of the array of information at the address recorded in counter 13, for this purpose from the digital computer via the block

II of the control unit 10, a corresponding reading strobe is supplied, which from one of the outputs of the group of elements

And 30 enters through the element OR 39 at the input of the reading of the OZB 16, transferring it to the reading mode. This strobe reading dd also arrives at the second input of the trigger. Gera 41, transferring it to the unit state and to the input of the converter's transform resolution 6. At the information inputs / outputs of the OZB 16, the first word of the information array appears and enters both into the digital computer (via block 11) and through register 4 to the second the input of the parity bit and sync bit generation section 27, to the first input of which, from the first output of the control unit 10, a conversion enable signal is applied. Node 27 of transducer 6 complements the received information word (16 bpc) with a synchrotransmit (3 bits) and parity bit and writes the day of the bit word in the parallel code to shift register 26. Node 24 parity bit analysis and sync pad

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analyzes the recorded word, and detecting the sync backflash in it from its third output, generates a signal to prohibit the exchange with the digital computer, as a result of which the digital computer removes the reading strobe. A single BipeMeHHO at the second output of node 24 appears a high level of signal. End of conversion. The shift register 26 converts the first word of the information array written into it into a serial code, K | otor, through blocks 7 and 8 of the transceiver g | transmitters is transmitted to the communication line. The content of the counter 13 is automatically reduced by one. At the end of the process of converting the first word of the information array to a sequential code, at the second pjoM output of node 24 of converter 6, a low signal level is applied. End of conversion, which is NOT 32j element AND 31 and Element OR 39 comes in the form of a read signal to the input of the OZB 16, which leads to the appearance of the next layer of the information on its information inputs - the outputs of the next layer. The transmission cycles of the word of the information array will Continuously follow one by one until the contents of the counter 13 and the register 14 are matched. In this case, at the output of the comparison node 18, a signal is generated that through the element OR 38 and the element NOT 35 enters the input of the element And 31, prohibiting the reading of the next word of the ZI array from OZB 16. The timer 25 of the converter 6 generates the signal to ban the exchange with the digital computer. The trigger 41 of the control unit 10 is nullified by writing the corresponding control word from the digital computer to the register of the 1 modes. At this point, the process of issuing the ZR array in the communication line is over.

The device for interfacing the digital computer with the communication lines allows combining the processes of recording an array of information from the digital computer in the local protection zone 16 with the process of issuing information in the communication line. In this case, the digital computer should record in the AO 16 a few words of the beginning of the array of information, then issue the Start 2 ZI command. At this command, the device will start outputting the words of the information array in the communication line, while not prohibiting the exchange with the digital computer, which can now continue

five

Write down the words of the information array in the pauses between the reading cycles of the data from OZB 6 to the register 4.

The device eliminates the possibility of issuing false words in the communication line due to the lag of the digital computer that records the information array. For this, comparison node 17 compares the contents of counter 12 and counter 13. If they are equal, then the output of the digital computer, which cocks the corresponding trigger in register 2 flags, is generated at the output of the comparison node 17, and also passes through the OR element 38 and the HE element 35 , prohibits the reading of the next word of information from OZB 16 ,. The pause will last until the next word of the information array is recorded from the digital computer to the second safety zone.

The device for interfacing a digital computer with communication lines provides the digital computer with the option of directly controlling the operation of register 1 of modes, the counter 12 to 13.15 of the switch 3 addresses, OZB 16 directly, and the operation of the remaining units of the device indirectly through the Q organization of the control exchange. with subscribers of communication lines.

Claims (1)

1. A device for interfacing a digital computer with communication lines, containing a mode register, a flag register, a control unit, a register of readable information, a register of recorded information, a reversible serial-to-parallel code converter, a switch, the first and second blocks of transceivers, and the information inputs are the outputs of the first and second blocks of transceivers are the inputs-outputs of the device for connecting respectively to the first and second lines of communication, with the information outputs of the first and second blocks of of the electric transceivers are connected respectively to the first and second information inputs of the switch, the information output of which is connected to the first information input of a reversible serial to parallel converter, the first information output of which is connected to the information inputs of the first and second transceiver blocks, the first information output of the mode register is connected to the first input of the logical the conditions of the control unit, the first code and the second input of the logical condition of which are connected respectively, with the conversion enable input and with the output of the conversion conversion of the reversible serial-to-parallel code converter, the second information output of which is connected to the information input of the register to count the gage information, distinguish yourself from the fact that, in order to expand the scope of application capabilities of software control of the exchange protocol and increase of reliability; a third block of transceivers has been entered into it, a write address counter of the recorded information, a read address counter vania record information, the register of the end of the recorded information array, the address counter of the readable information, the operative storage unit, the address switch and three comparison nodes, the first and second groups of information inputs-outputs of the third transceiver unit form the input-output groups of the device respectively, to the groups of information and address inputs / outputs of the digital computer, the first information input of the first comparison node forms the input of the edge of the counted information of the device, with volume, the second information input of a reversible serial-to-parallel code converter is connected to the information output of the register of recorded information, whose information input is connected to the information output of the register of the read information, information input-output of the operational storage unit, information inputs of the write address counter of the recorded information, counter of the address of the read memory information, the address counter of the read information, the register of the end of the array of the written For information, a data input-output modes and register with the third group of the third unit of information input-output transceivers, the fourth group of information outputs of which is connected to the input group invariant formagdaonnyh register inputs-outputs 0 five 0 five flags, the first information input of which is connected to the first clock output of the reversible converter sequentially parallel to the code and the third input of the logic condition of the control unit, the fourth input of which logical condition is connected to the second clock output of the reversible serial to parallel converter and the second information input of the flag register, the third information input of which is connected to the output of the first comparison node and to the fifth input of the logic condition of the control unit, the sixth the logical condition of which is connected to the fourth information input of the flag register and with the output of the second comparison node, the first information input of which is connected to the first information input of the third comparison node, with the output of the read address counter of the recorded information and the first information input of the address switch, whose information output connected to the address input of the operative memory block, the information output of which and the information output of the address switch are connected to the information group formation inputs of the third transceiver unit, the first and second information outputs of which are connected respectively to the seventh and eighth inputs of the logic condition of the control unit, the first output of which is connected to the first input of the mode register read / write and the first control input of the third transceiver unit, the second control whose input is connected to the second input of the g / shadow / recording of the mode register, with the synchronous inputs of the write address counter of the recorded information, the write address counter of the recorded memory information, the counter of the address of the read information, the register- and the end of the array of the recorded information and the second output of the control unit, the ninth input of the logical condition of which is connected to the outputs of the third comparison node, the second information input of which is connected to the output of the register of the end of the array of the recorded information, the KOMNfyTaTopa control input is connected to the second information output of the mode register, the third information} 1st five 0 five 0 five the output of which is connected to the control of the P1IIM input of the address switch, the second information input of which is connected to the second information input of the first comparison node and the output of the counted information address counter, the output of the write address counter; the recording information is connected; the information input of the address switch and the second information input of the second comparison node; the fourth information output of the mode register is connected to the 1 input of the logic condition 15 | of the control unit, the third and the fourth the outputs of which are connected respectively to the write and read inputs of the operative storage unit. I, I 2, The device according to p, 1, o t l and - | h a 10 e e with the fact that the control unit; Lenn contains two trigger; a, three elements: And, three elements I. PI, four ; element NOT; two groups of elements; And, whereby the zero input of the first trigger,: the input of the first element are NOT the first, second inputs of the logical condition of the block, the single input of the second trigger is connected to the input. the second element IE k is the third input of the logic condition of the block, the zero input of the second trigger, the first input of the first element AND, the first 20 25 the second input of the first element OR, the second input of the first element AND are respectively the fourth, nth sixth, seventh, eighth, ninth tenth inputs of the logical condition of the block, the outputs of the AND elements of the second group are connected to the first input of the prygo ISCh1, with a single input the house of the first trigger and are the first output of the block, the outputs of the elements AND of the first group of connections to the first input of the third element OR are the second output of the block, the outputs of the third and second elements OR are the third and fourth outputs of the block, respectively In the control unit, the output of the first element is NOT connected to the first input of the second element AND, the second output of which is connected to the unit output of the first trigger, the output of the first element OR connected to the input of the third element NOT, the output of which is connected to the third input of the second element which is connected to the second input of the second element OR, the output of the first element AND is connected to the input of the fourth element NOT, the output of which is connected to the first input of the third element AND whose output is connected to the second input of the third element OR, the output of the second element is NOT connected to the second input of the third the left input of the first element OR, the first. "element AND, zero output of the second inputs of elements AND the first rpynnMjnep inputs of elements AND of the second group. the trigger is connected to the second inputs of the elements of the first and second groups. five about 0 five the second input of the first element OR, the second input of the first element AND are the fourth, fifth, sixth, seventh, eighth, ninth tenth inputs of the logical block condition, the outputs of elements AND of the second group are connected to the first input of the second orchemical element the single input of the first trigger and are the first output of the block, the outputs of the AND elements of the first group of the connection with the first input of the third OR element and are the second output of the block, the outputs of the third and second OR elements are respectively the third and fourth outputs in the control unit, the output of the first element is NOT connected to the first input of the second element AND, the second output of which is connected to the single output of the first trigger, the output of the first element OR is connected to the input of the third element NOT, the output of which is connected to the third input of the second element AND whose output is connected to the second input of the second element OR, the output of the first element I is connected to the input of the fourth element NOT, the output of which is connected to the first input of the third element I, the output of which is connected to the second input the third element OR, the output of the second element is NOT connected to the second input of the third the trigger is connected to the second inputs of the elements of the first and second groups. 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