SU1234843A1 - Interface for linking digital computer with using equipment - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is intended for use in information and control systems. The aim of the invention is to expand the capacity by combining information processing cycles in time and the possibility of flexible reorganization of the organization of the transmission of urgent messages. A device for interfacing a computer with subscribers contains a communication unit with a digital computer, a buffer memory unit, a pulse generator, a communication unit with active subscribers, a communication unit with passive subscribers, 2 cpf, 15 Il.

Description

The invention relates to computing techniques and can be used in computing systems having an extensive network of subscribers.

The purpose of the invention is to expand the capacity of the device due to the combination in time of the cycles of processing the transmitted information and the possibility of a flexible reorganization of the organization of the transmission (reception) of urgent messages,

Figure 1 shows the block diagram of the device; Fig. 2 is a functional diagram of the bus connection node; FIGS. 3 to 5 are functional diagrams of a microprogram control node, an external signal decoder, and a logic conditions controller; FIGS. 6-8 show algorithms for the operation of a communication unit with a digital computer; FIGS. 9 to 14 illustrate the operation of the block of active subscribers; in fig. 15 - an example of the algorithm of working with one of the subscribers of the block of passive subscribers. The block symbols of the algorithms in FIG. 6-15 have state designations from 1 to 73

The device (FIG. 1) contains a block 1 of buffer memory, a generator of 2 pulses, a block 3 of communication with a digital computer, a block 4 of communication with active subscribers, a block 5 of communication with passive subscribers, information buses 6 devices, address buses 7, buses 8 synchronization and control of the device, bus 9 input and output of communication with active subscribers of the device, bus 10 of input of parallel exchange with passive subscribers, bus 1 of input and output of serial exchange with passive subscribers and control signals of parallel communication channels, bus 12 inputs and outputs of communication with digital computers real estate.

Unit 3 contains the register 13 of the exchange node 14 amplifiers, node 15 firmware control, address counter 6, node 17.convolution, node 18 connection to tires, elements AND 19 information buses of the group, elements And 20 address buses of the group .. Block 4 contains the register 21 , node 22 amplifiers, address counter 23, array length counter 24, firmware control node 25, switch 26, bus connection node 27, convolution node 28, AND 29 elements of the address bus of a group, AND elements of 30 information buses. Block 5 contains the first

432

node and amplifiers for serial channels and control signals of parallel channels; second node 32 amplifiers for parallel channels;

a register 33, an array length counter 34, a convolution node 35, a switch 36, a firmware control node 37, a bus connection node 38, And group 39 information bus elements.

Nodes 18, 27 and 39 of connection to П1И-н (Fig.2) contain the element AND-NOT 40, the trigger 41, the element NO 42 with an open collector, the load resistor 43. The nodes 15.25 and 37 contain (fig. 3)

start trigger 44, control trigger 45, AND-OR 46 element, state register 47, PI element 48, AND 49 element, micro-command register 50, operation 51 register, AND 52 element,

decoder 53 microinstructions, decoder 54 external signals, decoder 55 opcode, switch 56, element NOT 57, encoder 58 microinstruction, counter 59 format, decoder 60

conditions FIG. 3 also denotes input 61-64, outputs 65 and inputs 66 and 67 of the node, with input 61 being the fourth input of node 15, the third input of node 25, and the second input of node

37, inputs 62 and 63 form the seventh input of the node 15, the first and eighth inputs of the node 25 and the first and fifth inputs of the node 37, the input 64 forms the first, second, third, fifth and sixth inputs of the node 15, the second, fourth, fifth and the sixth inputs of node 25 and the third, fourth inputs of node 37. Outputs 65 constitute the first to ninth outputs of node 15, ps-left and eleventh outputs of node 25 and the first to seventh outputs of node 37. Input 66 and 67 are the ninth and the eighth inputs of the node 15, the ninth and inputs y3Jja 25 and the seventh II uit-shy inputs of the node 37.

The R & C state 47 (FIG. 4) contains the elements NOT 68, AND-NOT 69, and the triggers 70, the number of which corresponds to the number of synchronized signals.

The decoder 54 external signals built on the elements And 71, the number of which corresponds to the number of control cycles and the number of input signals processed at each cycle (Fig, 5).

The condition decoder 60 (FIG. 6) of the system: m1T elements are NOT 72, elements 11 73 and elements And 74.

3

The device provides operation in the following modes: reading information through parallel communication channels (bus 10, control signals — bus 11), reading (writing) data from the charger and digital computer; reading information via serial communication channels (buses II), writing (reading) information in the memory on the initiative of subscribers connected to buses 9, reading (writing) data from buses 9 to a digital computer.

The device can combine in time the execution of each of the first three modes with the fourth. ,

The nature of the exchange with all subscribers is exclusive.

The device is configured by a DVM command with three significant fields.

In the first field is placed the operation code of the CPC unit 3, in which the signs of work with blocks 1, 4 and 5 and the direction of information transfer are coded.

In the second field, in the case of the CPC I, a CPC 2 is placed in order to work with block 5, in which the signs of working with subscribers in communities 10 and 11 are coded

The third field, when working with block 1, contains the starting address of the memory, and in the case of working with block 5, the code for the length of the array of information.

The device works as follows.

In the initial state, the decoder 53 generates a signal, which is transmitted to the encoder 58 and block 54. At the output of the encoder 58 there is a positional code of the initial operation, which is transmitted to the input of the switch 56. The exchange with the DVR always starts with the Work (RB) signal. This signal from busses 12 through one of the amplifiers of node 14 enters node 15, where it sets in one state a trigger 44, from the output of which the signal is transmitted Through the AND-OR 46 element to the trigger input 45, through the OR 48 element to the control input register 50, to the first input of the element 49 and to the input of the decoder 54. Since in the initial state at one of its inputs there is a resolving signal level, then at the output of it and correspondingly at the output of the encoder 58 a signal is formed which goes through element 49 control input of the switch 56,

348434

from the output of which the initial operation code is transmitted to the information inputs of the register 51.

The information input of the first J bit of register 50 permanently contains a level 1 signal, the inputs of the remaining bits are level O, and the parallel-write synchronous input receives signals from generator pa 2. After the formation of the next pulse from generator 2 (input 61 in FIG. 3) a trigger 45 is set, first bit: gist 50 and one bit of register 51. Signal

1 from the output of the trigger 45 sets to the initial state the trigger 44 and, if necessary, on subsequent cycles it can confirm its setting through the element AND-OR 46, at the third 2Q input of which in such cases there is 1 level from the output of the HE element 57. At the output of the decoder 53, the signal of the first control clock is generated, which is transmitted to the encoder 58 and the decoder 54, where the next clock pulse gates the first clock signal, thereby generating the Ready signal, which is transmitted through the encoder 58 and the amplifiers 14 to the digital computer (Fig. 7). The non-probed first clock signal transmitted to the encoder 58 causes the NOT signal to be generated at its sixth output and, accordingly, at the input of the element, which blocks the circuit confirming the installation of the trigger 45.

The same clock pulse through ele. TI 52 enters the sync input of the serial shift of the register 50. On the falling edge of the pulse, the state O triggers 45, and 1 is rewritten into the second register bit 50.

The decoder 53 generates and transmits a signal to the decoder 54, respectively

U

five

associated with the second control cycle.

The command of the serial code goes through the amplifier from the digital computer to the elements And 71 of the decoder 54, corresponding to the second clock (figure 5), and through the encoder to the register 13 and the counter 59. When the command is sent to the register 47, the signal ends. ,

55 which includes a trigger 70 corresponding to this circuit (FIG. 4). AT

the same time, the input element AND-NOT 69 comes from the output element NOT 68

prohibitive level. Thus, the synchronization circuit of the corresponding trigger flushes is blocked for the duration of the signal KS. After completion of the CS signal transmission, the trigger on the trailing edge of the next clock signal is reset. A signal from the output of this trigger is transmitted to the input of the decoder 54 The inputs of the decoder 60 are connected to the outputs of the convolution unit 17 and the counter 59 The synchronized signal of the CC polls the convolution state (input 67 in Figs. 3 and 6) and the counter 69. The outputs of the decoder 60 are grouped into the encoder 58 and form the enable signal of the mutator 56 on the input from the decoder 55 and, respectively, the register 13, as well as the input to the control of the modes of the register 50 through the element OR 48

In the case of a negative result of the analysis, a single signal level at the output of the HE element 72 (Fig. 6) is generated and transmitted from the output of the corresponding element AND 73 through the encoder 58, the node 14 in the digital computer - the Fault signal (NP). On the front of the next clock pulse, the code 51 is written to the register, the CPC 1 operation is set to state 1, the first register bit 50 and the trigger 45.

Thus, register 51 changes its state, and block 15 starts executing the firmware of the corresponding command specified in CPC 1. In the case of CPC i, the recording of information in the memory (FIG. 7) is used to record the initial memory address in counter 16, turn on trigger 45, then form and transmit the signal GT in DAM from DVM and record their memory, Record and control the information word is produced as described. At the end of the control, the firmware comes to a halt and generates a signal at the output of the encoder 58 and, accordingly, at the element 40, the inverse input of the installation state to the O trigger 41 of the node 18 (FIG. 2). The trigger output through the element NO 42 with an open collector is connected to the bus Busy busses 5 to the load resistor 43 to the input of the element 40.. A high level on this bus indicates the absence of information busses and, conversely, a low level indicates that they are busy. To the third

An input of the NE-40 element is connected to the generator output, through which the signals of one of the phases are formed. By ass; The front of the next signal of the generator 2 is triggered to it, the state 41 is set to state 1, on this bus, the level O is formed, and from the output of the trigger 41 the signal 1 is transmitted

10 to the decoder 54, at the outputs of which, and respectively of the encoder 58, signals are formed that open the information and address buses to the inputs of the AND elements 19 and 20, as well as

15 sig; 1L of the record (S3), which is transmitted to block 1. Thus, the information word is transferred from register 13 to block i at the specified address. The end of write cycle (CC) signal is transmitted from block 1 through register 47 to decoder 54. Next, the firmware will tumble t into counter 16, generate a signal GT and exit to a stop, where

;; reception of the next word is due

from digital computers. After the last word of the digital computer is written into the memory, the QO exchange end signal is transmitted, which sets block 3 to the initial state.

In the case of a KOP 2 signal for reading information from a charger (fig. B), the starting address is written to counter 16, then the bus is captured and signals are issued for unlocking the address bus at the I 20 and Read (MF) in the charger. From block 1, the information word is read to bus 6, the read cycle is accompanied by a CC signal, which is used to write to the register

Oil / sg

l-J, and trigger start 45. Next, the information on the register 13 is modulated, the counter 16 is adjusted, and the signal is generated

GT transfer to digital computers. five

At the CS signal, the flushing cycle is repeated until the QO signal is transmitted instead of the CS.

When KOP 1 to issue information to the block, 4, block 3, after receiving the command, generates a signal Gt in the digital computer, receives the first word of the array, organizes a bus seizure in the presence of a HZ 4 signal from block 4, unlocks the information widths and generates a signal. 3 in block 4 (IF). With KOP 1 to read information from block 4, block 3 (FC-, 9) with

0

the presence of Hz 4 generates a signal of the start of the NTS cycle () and awaits a response in the form of an IF signal () and the corresponding information on the tires 6, upon receipt of which organizes the word transfer cycle in the digital computer, while starting the next word reading cycle, in block 4, B In case of KOP 1 to work with block 5, block 3, after receiving the command, organizes: capture of tires and sends to block 5, KOP 2 and the array length code, accompanying the transmission with a signal; Setting block 5 and generating further the GtZ signal; waiting for information transfer from block 5 IF signal (). At the end of the transfer unit 3 transmits a signal to the CT in the digital computer, a signal from the CS generates a signal to the GTZ, etc.

The device is configured to work with active subscribers by a digital computer by writing commands of the second type to the memory. Each subscriber has two fixed cells in the memory, the address of which corresponds to the subscriber number and the sign of writing (reading). At these addresses, commands of the second type are written, having three significant fields. In them, the CPC 3, the code of the array length and the starting address of the array in the memory are entered. The last field is entered in case the work of the digital computer with the subscriber takes place without intermediate buffering of information in the memory. The first cell of the memory with zero address is used by block 4 to store the record (read) sign and the subscriber number that went on the link, and the second - to store the same values on the last subscriber who completed the transmission of the information array.

The eighth inputs of the node 25 through the amplifiers 22 receives signals from active subscribers. In particular, the input 62 sends a signal to the end of the transfer of the address by the subscriber - KPAA, to the inputs of the synchronizer 47 - the end of the transfer of the word by the subscriber - KISA, Failure of reception - SPA, Ready to receive. P1A, End of MaccTiaa - KMA

From the eighth output of unit 25, control signals are transmitted to the buses 9 through the amplifiers 22 Ready to receive — GP, End of word transmission — KIS, Failure receive — SP, End of array — KM.

On the fourth exit and the entrance for the organization of reading (writing) information

u 5 20

25 so

five

five

0

five

The signals from (in) block I to block 25 are summed up by signals - Read - FTS, Record - Sn, End of cycle - CW.

The second inputs, outputs and the third output of communication with block 3 are signals. The transfer of the number from block 3 to block 4 is IF (), from block 4 to block 3 is IF, (), Ready for cycle. block 3 - GCP, block 4 - Hz4, interrupt signal Pv.

In the initial state, the device generates and transmits a signal to the bus 9 (figure 10).

The operation begins with the subscriber transmitting the code of his address, which through the amplifiers 22 and block 25 is recorded in register 21. By the signal of the HVAC, which accompanies the transfer of the address, block 25 adjusts to the operation to enter the link, in accordance with which the first clock is used to monitor the address modulo, for which switch 26 is connected to the input to register 21, and, accordingly, an address code is transmitted to the convolution input 28. In the second cycle, where the control unit goes with a positive control result, a signal is transmitted to the device 27, which organizes inter-block bus acquisition. When the trigger 41 is activated in the device 27, the block 25 unlocks the switch at the input from the register 2 1, elements 29 and 30 and generates a signal Sn. Thus, at the zero address, the cycle of recording the address of the subscriber is organized (counter 23 is in the initial state). At the CC signal, block 25 goes to the third cycle, freeing buses 6 and 7, confirming the previous state of the switch, and generating a write signal to counter 23.

In the fourth cycle, the capture of tires is organized to read a cell with a command of the second type corresponding to the number of the requested subscriber. To do this, the switch 26 is unlocked at the input from the busses 6, the input of the elements And 29, and an MF signal is generated. At a CCP signal, the command from block I is recorded in counters 23 and 24, as well as in register 51 in accordance with its significant fields, and block 25 switches to a new operation corresponding to the specified CPC 3.

B KOP 3 can be encoded operations: Writing from tires 9 to memory, Writing from tires 9 to digital computers, Reading from memory to pins 9, Reading from digital computers to tires 9.

In the case of operation with digital arrays (2 and 4 operations), block 25 generates an interrupt signal, which is transmitted through amplifiers 14 of block 3 in a digital computer. When recording from bus 9 to a computer, it organizes the reading of the first word of the array from bus 9 to register 21 and waits for the HCH signal , and when reading from the digital computer to the bus 9, it forms the signal Hz 4 "

On the interrupt signal, the digital computer transmits to the device a command to read the zero cell of the charger, after the command completes, the subscriber number and mode of operation are determined.

Then the digital computer transmits a command for operation of unit 3 with unit 4, indicating the direction of information transfer. In the case of reading from the digital computer, unit 3 immediately receives from the digital computer the first word of the array and arranges for capturing the tires with transmitting this word to unit 4 by the IF signal (3, 4) 5, having previously analyzed the presence of the Hz4 signal (figure 3) . Block 3 upon completion of the transfer of the word in block 4 transmits to the digital computer a readiness signal to receive the second word. Block 4, on an IF signal (), writes an information word to register 21 and starts a cycle to issue it to buses 9, after which it corrects the contents of counter 24, analyzes its state, s sets signal Hz4, etc., Information words are transmitted over buses 6 with the control codes for the module and in the receiving unit, they are monitored, and in the transmitting unit - the formation of the control codes with and without or with the control codes for the module, with a different base. Upon overflow of the counter 24, a CM signal is generated, and block 4 proceeds to the completion operation of the communication (FIG. 14) 5 on which the address of the subscriber who completed the communication from the zero cell of the buffer memory first is recorded by periodically reading the state of the first cell of the memory unit can monitor the addresses of the subscribers who have completed the communication. In case of recording from tires 9 in a digital computer unit

u, 15

20

25 5

thirty

40

five

4 prepares the first word of the array in register 21 and waits for the HZZ signal. After receiving a command from the digital computer to write the array (FIG. 12), block 15 generates a Hz signal, and block 4 organizes the transmission of the information word to register 13 by the IF signal (), while block 4 starts reading the second word of the array from the buses 9. In the same time block 3 transmits the first word to the digital computer. All subsequent subscriber array words are transmitted in a similar manner. The last word of the subscriber array is accompanied by a signal KMA, upon receipt of which the state of the counter 24 is monitored.

In the case of KOP 3, the block 4 automatically organizes word-by-word write (read) cycles from these tires and work with the charger (Figs. 1 and 12) for writing (reading) from tires 9 to the memory,

Preparation of the device for work with subscribers on buses 10 and 11 is performed by the Signal Configuring, I build the transmission in block 5 of the CPC 2 and the code for the length of the array of information, which are recorded respectively in the register 51 of block 37 and counter 34 (Fig. 15). Signal Setup, entering the input 62 of block 37, starts the microprogram readout of the array of a given subscriber, in accordance with which subscriber readiness is analyzed. In case of work on buses 10, the microprogram performs the following action: unlocks one of the input group of the switch 36 corresponding to the specified subscriber, initiates request for the first word of the array, organizes the recording through the second node of the yci-shchitel 32 switch 36 to the register 33 and its control at convolution 35. D; 1, block 5 in the presence of a GtZ signal organizes the capture of interconnects tire through assembly 38 and transmitting the data word from the register 33 via the commentator 36 and AND gates 39 to the register 13 by the signal I M (), the counter 34 is corrected then analyzed its state, the cycle is started to read the next word of the array, etc. When the counter overflows, a signal for the end of the exchange is formed. The operation of the device on tires 11 differs only in the way information is transferred to

block 5. The information words are transmitted in serial code from bus 1 through the first node of amplifiers 31 and block 37 to register 33.

Thus, due to the inter-unit bus transmission of information and the presence of blocks that have autonomous, practically independent processing cycles, an increase in the capacity of the device is ensured.

The possibility of a flexible reorganization of the organization of information transfer when working with active subscribers allows reducing the transmission time of an urgent message (array of information).

An interconnect bus organization can reduce the total number of connections in a device and simplify its

structure.

The amount of equipment for organizing the capture of inter-block tires is insignificant, and the method of their use is simple and reliable. The use of internal information buses in blocks 4 and 5 contributes to increasing the survivability of the device as a whole, since faults such as a short circuit of two register, counter, or one of the inputs to the housing in one of these blocks do not lead to a malfunction of the device in relation to subscribers of another block.

The presence of a convolution modulo improves the resolution of the location of arising mjix faults and thereby increases the availability of the device.

The use of the proposed interface with such a structure makes it possible to organize information exchange with subscribers having different characteristics of communication channels.

Claims (3)

Invention Formula  , A device for interfacing a digital computer (DVR) with subscribers, containing a communication unit with a DVR, the first input and output of which are the input and output, respectively, of a communication with the DVR of the device, the first input-output is connected via information buses with information input 34484312 output of the buffer memory block, and a pulse generator, which is so necessary, in order to increase the capacity of the device, a communication unit with passive subscribers and a communication unit with active subscribers are entered into it wherein the first input and output of the communication unit with the active subscribers are input and Id communication output with the active subscribers of the device, the second input, the second and third outputs are connected respectively to the second output, the second and third inputs of the communication unit with a digital computer, 15, the third input - with the first output of the pulse generator; the fourth input of the communication unit with active subscribers is connected to the fourth input of the communication unit with the digital computer and the synchronizing output 20 of the buffer memory unit, and the fourth output - with the third output of the communication unit with the digital computer and the control input of the modes of the buffer memory block, whose information input-output is connected 25 through the information buses with the first inputs-outputs of the communication unit with active subscribers and the communication unit with passive subscribers, and the address input through address fault with the fourth output of the communication unit with DVM and the fifth output of communication unit with active subscribers, The second input-output of which is connected to the second inputs-outputs of the communication unit with the digital computer and the communication unit with passive subscribers, the first input and output of which are the input and output of the serial exchange with the passive subscribers of the device, the second input and output Q connect the corresponding tii continuously with n output and input of communication with a digital computer, input group forms a parallel input to passive exchange subscriber unit, a fourth input coupled to ., the second output of the pulse generator, the third output of which is connected to the sixth input of the communication unit with a digital computer, and the communication unit with a digital computer contains an exchange register, amplifier node 1 |, address counter, convolution node, bus connection node, information elements AND group , a group of elements And the address bus, the node of the firmware control, the first, second and third inputs and outputs of the node 5i of the firmware control are, respectively, the second input and output, the fourth input and the third output, the fifth input and output of the control unit. 50 t3e, the fourth input is connected to the first input of the bus connection node and the sixth block input, and the fourth output is connected to the second input of the bus connection node whose input / output port is the second input / output block, and the output is connected to the fifth input of the firmware control node, The sixth input and sixth input of which are connected respectively to the control input and output of the exchange register, and the sixth output to the first information input of the amplifier node, the second information and control yush inputs, the first and second outputs of which Dineny, respectively, with the first and third inputs, the first output of the block and the seventh input of the firmware control node, the seventh output of which is connected to the counting input of the address counter, the output group of which is connected to primary inputs of the corresponding elements AND address buses of the group whose outputs form the fourth the output of the block, and the second inputs are connected to the eight-f-ibiM output of the firmware control node, the eighth input of which connected to the output of the convolution node. the group of inputs of which are connected to the ninth input of the firmware control node, the information input of the address counter, the group of outputs of the exchange register and the first inputs of the corresponding elements AND information buses of the group whose outputs and information input of the exchange register form the first input-output of the block. and the second inputs are connected to the ninth output of the firmware control node, while the communication unit with active subscribers contains an amplifier node, an address counter, an array length counter, a switch, a register, a bus connection node, a convolution node, a group of elements AND address buses The K group of information buses and the microprogram control unit, the first and second inputs and outputs and the third output of which are the second, fourth inputs and outputs and the third output of the block, the third input is the third input of the block band: the first input node connecting to Shih us, the input-output is input-output of the second block, and a second input and an output connected respectively j; 0 five 0 directly to the fourth output and input of the microprogram control unit, the fifth output and input of which are connected respectively to the control input and output of the register, the sixth input and output respectively to the output and counting input of an array length counter, the seventh output of the microprogram control node is connected to the counting input of the counter addresses, the seventh input is with the first output of the convolution node, the eighth output is with the First input of the amplifier node, the first output and the second input of which are the first output and input of the block, respectively, and the second The output is connected to the eight-M1LM input of the microprogram control node, the ninth output of which is connected to the control inputs of the elements AND address buses of the group whose outputs form the fifth output of the block, and the information inputs are connected to the output of the address counter and the first input of the switch, the second input of which connected to the register output group, the third input — to the second output of the convolution node, the fourth input — to the tenth output of the microprogram-I control node, the fifth input of the switch is connected to the first input-output of the unit and to the outputs Groups of information whose control inputs are connected to the eleventh output of the firmware control node, and the information inputs are connected to the switch output, the input of the convolution node, the ninth input of the firmware control node, information inputs of the register, address counters and the length of the r-array, in addition, the communication unit with passive subscribers contains the first amplifier node, the second amplifier node, a register, an array length counter, a convolution node, a switch, a bus connection node, a group of elements, and info The control bus, the firmware control node, the first input and output of which are respectively the second input and output of the block, the second input is the fourth input of the block and is connected to the first input of the connection node to the bus whose input-output is the second input output of the block, and the output and the second input are connected respectively to the third input and the second output of the microprogrammed rc-rrr node, the third output of which is connected to the control input of the register, the fourth input and output, respectively, with the output and the counting input of the array length counter, a. the fifth input is with the first output of the first node of the amplifiers, the first input and the second output of which are correspondingly a first input and output of the block, and the second input is connected to the fifth output of the microprocess control node, the sixth output of which is connected respectively to the first output of the convolution node and control inputs, elements AND information buses of the group, the outputs of which are connected to the first input-output of the block and the first input of the switch, and the information inputs to the output of the switch, the input of the convolution node, the information inputs of the switch an ister and an array length counter and the seventh input of the microprogram control node, the seventh output of which is connected to the second input of the switch, the third input of which is connected to the register output, the fourth input to the second output of the convolution node, and a group of inputs to the group of outputs of the amplifier node, a group of inputs which is a group of block inputs. 2, The device according to claim 1, wherein the bus connection node contains a trigger, an AND-NO element and a NOT element with an open collector, the output of which is the input-output of the node and connected to the first input of the AND element -NOT and through the load resistor to the positive polarity of the power supply, the input is connected to the trigger output and the node output, the second and third inputs of the AND-NE element are the first and second inputs of the node, respectively, and the output is connected to the synchronous trigger input whose information input and reset input are connected by respectively to the bus of the logical unit and the second input of the node, 3. The device according to claim 1,. This is because the microprogrammed control unit of the communication unit with a digital computer contains a start trigger, an AND-OR element, a control trigger, a micro-operation code decoder, a switch, an operation register, micro-commands decoder, micro-commands coder, external decoders signals register mik0 five 0 five 0 five 0 five rokomand, format counter, status register, condition decoder, OR element, two AND elements and F1E element, the first group of outputs of the micro-command encoder connected to the first - ninth outputs of the node, the second group of outputs and the first group of inputs are connected respectively to the groups inputs and. outputs of the condition decoder, the first and second inputs of which are connected respectively to the eighth input of the node and the first output of the format counter, the second output and input connected to the first input of the external signal decoder and the first output of the microinstructor encoder, the second groups of inputs and output of which are connected respectively to the output group and the second input of the external signal decoder, the first group of inputs of which is connected to the first, second, third, fifth and sixth inputs of the node, and the second and third groups of inputs are respectively with the group of outputs of the state register and the first group of outputs of the de-encoder of external signals, the first, the second group of inputs of which are connected respectively to the groups of outputs of the register of microinstructions and the register of microoperations, and the second group of outputs - to the third group of inputs of the encoder of microinstructions, the third, fourth, the fifth and sixth outputs of which are connected respectively with the first inputs of the element OR, the element AND-OR, the first element AND and the input of the element NOT, and the seventh and eighth outputs - respectively with the first information and control switch inputs, the second information input of which is connected via the decoder of the micro-operation code to the ninth input of the node, and the second control input and output — Respectively — to the output of the first AND element and the information input of the operation register, the synchronization input of which is connected to the fourth input of the node, inputs control trigger synchronization register of microinstructions, the third BXQ-house of the external signal decoder and the clock input of the status register, whose group of inputs and the start trigger setting input form the seventh th node input start trigger output connected to a fourth input of the decoder of external signals, the second the inputs of the OR element, the first AND element and the AND-OR element, the third input of which is connected to the output of the elevator is connected to the output of the AND-OR element, the second input of the second element is connected to the fourth input of the node, and the output is NOT, the fourth input - from the first - stroke - with the clock input of the shift with the roaring input of the second element I, the reset input of the trigger trigger and the output of the control trigger, information 9 a master of microoperations whose control input is connected to the output of the OR element. the input of which is connected to the output of the element that is AND-OR, the second input of the second element AND is connected to the fourth input of the node, and the output - to the clock input of the shift of the registrar of micro-operations, the control input of which is connected to the output of the element OR. KDS  S3 6f S3 Vuf.3 t (D1 5i / Cf / afjf / Ipul tl H ue.6 S, fS, 3O.ia, 4f JL S, g, 5,3.SZ L Rig i 9ul.9 69.69, SS, "Vif / JiJ i 9ff J P SB at FD f4O yy WITH. Editor E. Kopcha Compiled by V. Vertlib Tehred M. Khodanych Order 2987/52 Circulation 671 Subscription VNIIPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d.4 / 5 Production-GEOLIGRAPHIC ENTERPRISE, Uzhgorod, Projecto st., 4 Proofreader S. Shekmar