SU1532939A1 - Device for interfacing computer with common main line - Google Patents

Abstract

The invention relates to computing and can be used to build multi-machine computing systems. The aim of the invention is to increase the reliability of information transmitted over a common highway and received by one of the devices of the system, by providing an automatic return transmission of the received data packet to the transmitter device. The device contains two blocks of buffer memory, eight main amplifiers, a node for capturing a line, a pulse generator, a pulse distributor, an address decoder, five triggers, four counters, seven AND elements, five OR elements, two single vibrators, a comparison unit. 1 hp f-ly, 5 ill.

Description

The invention relates to computing and can be used to build multi-machine computing systems.

The aim of the invention is to increase the reliability of information transmitted over a common highway and received by one of the devices of the system, by providing an automatic return transmission of the received data packet to the transmitter device.

Figure 1 shows the structural diagram of the proposed device; Fig. 2 illustrates an exemplary implementation of buffer memory blocks; on fig.Z - the structure of the node capture the line; figure 4 is a structural diagram of the address decoder; Fig. 5 is a diagram of the integration of a computer into a multi-machine system using this device.

The device (figure 1) contains blocks

1 and 2 buffer memories, counters 3 and 4, flip-flops 5 and 6, a trunk acquisition unit 7, a pulse generator 8, an address decoder 9, an AND 10 element, an OR 11 element, a trunk amplifier 12-19, 20 block 1 address inputs and

2 buffer memory, read inputs 21 of blocks 1 and 2 of buffer memory, bus

22 information, confirmation bus 23, busy bus 24, synchronization bus 25, counters 26 and 27, triggers 28-30, comparison block 31, pulse distributor 32, one-shot 33 and 34, elements AND 35-40, elements OR 41-44 , data line 45, inputs 46 and outputs 47 of blocks 1 and 2 of buffer memory, interrupt line 48, Record requirement line 49, record line 50, records of 51 records of buffer memory blocks 1 and 2, interrupt line 52, line 53

i -

WITH

setup, read line 5, transfer request line 55, address inputs 56 of blocks 1 and 2 of the buffer memory, read inputs 57 of blocks 1 and 2 of the buffer memory, outputs 58 of blocks 1 and 2 of the buffer memory.

The blocks 1 and 2 of the buffer memory (FIG. 2) contain memory nodes 59, each of which includes a register 60, a multiplexer 61 and groups of elements AND 62 and 63 and a control circuit consisting of decoders and 65, groups of elements AND 66- 68 and groups of elements OR 69 and 70, inputs 71 and 72. The trunk acquisition node 7 (FIG. 3) contains a counter 73 register 74 and a trigger 75. The address decoder 9 (FIG. 4) contains a comparison node 76, register 77, trigger

ten

15

on line 53. On this impulse, counters 3, 4, 26, and 27 flip-flops 5, 6, 28, and 29 are reset to zero, a zero potential occurs at the stroke of the gripper line 7, which triggers the appearance of a zero level at the outputs of flip-flops 30 and Decoder 9 of all devices 80 systems. line 49 appears as a logical unit potential.

In devices 80, blocks 1 of the memory buffer are accessible from line 45 only records, and blocks 2 of buffer memory are read only. Data recording in block 1 is accompanied by a signal on Research Institute 50, and reading from block 2 is accompanied by a signal on the line. Having a line unit of 49 means that block 2

78 and element 79. In Fig. 5, Fig. 2Q is free. When recording information in

80 mates and

thirty

35

ger

device razheny

Computer 81.

The device works as follows.

The exchange of information between a pair of computers 25 81i (i 1-n) and 8lj (j 1-n) of the system using devices 801 and 80j (FIG. 5) is carried out via a common bus consisting of the following buses: information bus 22; confirmation tires 23; 2k tires; Bus 25 sync.

The exchange includes the following j steps: checking the computer 81i by the initiator of the exchange of the occupation of its device 801 and, if necessary, waiting for its release; transferring the packet of information via line 45 from computer RAM 81 to block 1 of the buffer memory of the device 801; the capture device 801 common highway; checking the block 2 of the buffer memory of the device 80j and, if necessary, waiting for its release; transmitting a packet of information from block 1 of the buffer memory of the device 801 to block 2 of the buffer memory of the device 80j; reverse transmission of a packet from block 2 of the buffer memory of the device% 80j through the common line and comparison of the buffer memory of the device 801 transmitted to the contents of block 1; in the event of a data mismatch, switching the computer 81i to an interrupt mode by transmission error; reading information from block 2 of buffer memory of device 80j in computer RAM 8lj no interrupt. 55. The system is started up from the initialization of the devices 80, which is produced by feeding the impulses

45

50

block 1, on the trailing edge of the pulse on line 50, the value of counter 3 y is readable by one. The value at the outputs of this counter determines the res of the information word recorded in block 1 "

i

After the overflow of the counter 3 of its overflow output, an impulse appears, on the front of which the counting trigger 5 and the trigger 29 are set to one, resulting in line 49 appearing zero level indicating that the block of the device 801 is occupied at the inputs The elements 38 and 40 appear to have zero potentials. The computer 81is, writing the packet in block 1, sets the requirements for transmitting a unit level to the line 55, thereby giving the unit output potential of the element 35 to the input of the request for node 7. After resolving all possible conflicts to the output node 7, there appears a single potential indicating the capture device vom 801 common highway. This capacity is fed to bus 24 busy in device 801 to the inputs of elements 36, 38, and 40. At the output of element 36, a potential of a logical unit appears that permits the passage of clock pulses from generator 8 to the first output of distributor 32 pulses. The clock pulses from the output p of the limiter 32 are fed to the input 2 of the reading of unit 1 and to the bus 25 of the synchronization. From these pulses, the first word is read from block 1 in device 801. The content of this with yours determines the address of device 80j

on line 53. According to this impulse, counters 3, 4, 26, and 27 trigger 5, 6, 28, and 29 are reset to zero; at the output of node 7 of the capture line, a potential of zero appears. initiates the appearance of a zero level at the outputs of the flip-flops 30 and decoders 9 of all devices 80 of the system. On line 49 a logical unit potential appears.

In devices 80, blocks 1 of buffer memory are accessible from line 45 only by writing, and blocks 2 of buffer memory are accessible only by reading. Write data to. block 1 is accompanied by a signal on line 50, and reading from block 2 is a signal on the line. The presence of a unit on line 49 means that block 2

Q is free. When recording information in

0

five

five

five

0

five

0

block 1 on the trailing edge of the pulse on line 50, the value of counter 3 is increased by one. The value at the outputs of this counter determines the address of the information word written in block 1 „

i

After the counter 3 overflows, a pulse appears at its overflow output, on the front of which the counting trigger 5 and the trigger 29 are set to one, with the result that on line 49 a zero level appears, indicating that block 1 of the device 801 is occupied, At the inputs of the elements 38 and 40, zero potentials appear. The computer 81is, by writing a packet in block 1, sets the requirement for a unit-level transfer to line 55, thereby the unit potential from the output of element 35 is fed to the input of the request of node 7. After all possible conflicts are resolved, the output potential of node 7 appears to indicate the seizure device 801 common highway. This potential enters the bus 24 busy and in the device 801 - the inputs of the elements And 36, 38, 40. At the output of the element 36 there appears a potential of a logical unit that permits the passage of clock pulses from the generator 8 to the first output of the distributor 32 pulses. The clock pulses from the output of the distributor 32 are fed to the input 21 of the reading unit 1 and to the bus 25 synchronization. These pulses read the first word from block 1 to device 801. The content of this word determines the address of the device 80j.

on a common highway. The address word enters the bus 22 through the trunk amplifier 12, opened for transmission by the level of one at the output of the element OR 41.

In the device 80j, the address word che through the trunk amplifier 12- | steps on the inputs of the decoder 9 addresses. The decoder operation is synchronized by pulses arriving at its sync input from bus 25. If block 2 in device 80j is free (as indicated by the presence of a logical unit at the zero output of flip-flop 6), the output potential of the decoder 9 appears bus 23 and into the device 801,. switches the passage of pulses from the distributor input 32 pulses to its second output. The sync pulses from the second output of the distributor 32 initiate the reading of the entire packet from block 1. The reading of the word is accompanied by a pulse at the input 21 of block 1 at the address specified at its input 20. The specified pulse edge increases the content of counter 3 by one. Information from the outputs 47 of the unit 1 of the device 801 through the amplifier 12 enters the bus 22. After the counter 3 overflows, a pulse appears on its overflow output that zeroes the trigger 5, thereby initiating a logic zero level at the outputs of the And 35 and 36, the zero level at the output of the AND 36 closes the passage of the clock pulses through the distributor 32. Simultaneously with this level of the logical unit, a single level appears at the output of the AND 40 element, which in the device 801 closes m amplifier 12 for transmission in both directions.

In device 80j, information from bus 22 enters through amplifier 12 to inputs 46 of unit 2. Synchronization is performed by pulses on bus 25, which through amplifier 18 and element 10 (element 39 is closed by a zero level at the output of trunk amplifier 14) arrive at input 51 write block 2 and through the element OR 43 to the counting input of the counter 4. On the trailing edge of the pulses there is a build-up of the counter 4, the value of which sets the address of the recorded information on

about

five

0

five

0

five

0

five

the inputs of the address 20 of block 2 of the device 80j. After the overflow of the counter 4, a pulse appears at the output of its overflow, which sets the triggers 6 and 28 to one. The zero level at the zero output of the trigger 6 closes the AND 10 element, and the single level at the output of the trigger 28 permits the passage of pulses in the device 80j from the generator 8 through element 37. At the same level, amplifier 12 is switched to transmit. The sync signals from the output of the element 37 are fed to the input 57 of the reading unit 2 and to the synchronous input of the counter 27.

On the falling edge of the pulse, an increase in its value occurs, which determines the address of information in block 2. Thus, information is output from block 58 to bus 22. After the entire packet is output, the overflow output of counter 27 causes an impulse to trigger a trigger 28 , thereby closing the element 37. Over a differential to zero at the output 28, at the output of the one-shot 34, an interruption pulse appears, which is transmitted via line 48 and switches the computer 81j to the packet reading mode. Reading pulses are fed to the input 21 of the reading unit 2 of the device 80j. On the trailing edge of the pulse, the value of counter 4 is increased by one. The data from block 2 of device 80j enters the computer 8lj via line 45. After reading the entire packet, counter 4 overflow emerges a pulse through which the counting trigger 6 is zeroed. Trigger value 28 unchanged by the presence of a logical zero level at its D input.

In the device 801, information is received from the bus 22 through the trunk amplifier 13 to the inputs of the comparison unit 31. The synchronization pulses from the bus 25 through the element 38 arrive at the synchronous input of the counter 26 and the input 57 of the reading block 1. The impulse reads the word from the block 1 to the outputs 58. The counter edge of the pulse increases by one the value of the counter 26 defining the address of the read information, which enters the other information inputs of the comparison unit 31. When the first discrepancy of information transmitted via bus 22 and read from block 1, a unit potential appears at the output of comparison block 31. On the falling edge of the synchronization pulse, trigger 30 switches to a unit, issuing an interrupt signal on line 52 to the ZVM 81i, indicating a transmission error. After the counter 26 overflows, an impulse appears at its overflow output, which flushes the trigger 29 and resets the node 7, as a result of which a single potential appears on the kS line, a logical zero potential appears on the 23 and 2k buses, the trigger 30 is reset to zero. The 81i computer, having received an interrupt on line 52, can retransmit the packet by completing the newly described cycle.

The blocks 1 and 2 of the buffer memory (FIG. 2) operate as follows.

The capacity of blocks 1 and 2 is determined by the number of nodes 59, and the size of the register is 60. The nodes are addressed from inputs 20 and 156. After setting the address, the potential output of the decoder 6k or 65 appears on the corresponding output of the decoder through the group of elements OR 69, it enters the corresponding Requests for the capture of the common highway from the input of the request to the D input of the trigger 75. If the potential of logical zero is located at a width of 2k, then upon receipt of pulses to the synchronization input of the node 7 The rotation of the value of the counter 73. The initial value of the counter 73 is determined by the value at the outputs of the register 7k, which represents the set of logical zeroes and ones corresponding to the priority of the device 801. The higher the device priority, the greater the binary value is at the outputs of the register 7k. As soon as counter 73 overflows, a pulse arrives at its overflow output, arriving at the C input of the trigger 75, putting it into one state. The trigger 75 exposes to the output of the node 7 a unit level, which through the bus 2k enters the inhibit inputs of all the nodes 7 of the devices 80 of the system,

the most initial production of the installation of counters 73 and block their work. The trigger 75 is reset by applying a signal to the set or release inputs. So taka

the input of a group of elements And 66. After 30, the implementation of node 7 allows the

when a write pulse arrives at input station 51 or 72 at the corresponding output (depending on the address) of the JTOB OR 70 element group, an impulse appears that goes through the corresponding element of the AND 66 element group to the synchronization input of the register 60 of one of the channels 59 in accordance with addressing. Moreover, when a write pulse arrives at input 51, recording is made from inputs 6 at the address specified at inputs 20, and when a recording pulse arrives at input 72, information is recorded from inputs 71 at the address specified at inputs 56. Information is read by applying a read pulse to input 21 or 57. In this case, when a reading pulse arrives at input 21, information arrives at outputs k7 through a group .. of elements AND 62 of the corresponding addressing from inputs 20 of node 59, and when a reading pulse arrives at input 57, information arrives at output 58 through the group of elements And 63 corresponding addressing from the inputs 56 of node 59.

Node 7, (fig.Z) works as follows

Only one device 801 can capture a common trunk.

The address decoder 9 (figl) provides for the addressing of devices 80 s

35 common highway. The device address code 80j is specified by register 77, representing a set of zeros and ones depending on the device address 80j. The operation of the synchronization comparison node 76 by the pulses coming from the synchronization input of the decoder 9 When the address of the device 80j specified by register 77 coincides with the information at the inputs of the decoder 9, the pulses arriving at the input of the AND element 79 appear at the output of the comparison node 76. If block 2 of the addressed device 80j is free, then the pulses from the output of the element And 79 are sent to the C input of the trigger 78 (D input to the state of logical unit), switching it to the one state. The potential from the output of the address decoder enters the bus 23 of the sub-order-5 neither. C) the flip of the trigger 78 is performed by applying a logic zero level to the input of the prohibition of the address decoder, which is connected to the reset input of the trigger 78,

at

)

ten

- 25 and 532939 .8

Requests to capture the common highway come from the input of the request to the D input of the trigger 75. If the potential of logical zero is at 2k, then when the pulses enter the synchronization input of node 7, the value 73 of the counter begins to increase. The initial value of the counter 73 is set by the value at the register outputs 7k representing the set of logical zeros and ones corresponding to the priority of the device 801. The higher the device priority, the greater the binary value is at the outputs of the register 7k. As soon as counter 73 overflows, a pulse arrives at its overflow output, arriving at the C input of the trigger 75, putting it into one state. The trigger 75 exposes to the output of the node 7 a unit level, which through the bus 2k enters the inhibit inputs of all the nodes 7 of the devices 80 of the system,

the most initial production of the installation of counters 73 and block their work. The trigger 75 is reset by applying a signal to the set or release inputs. So taka

20

the implementation of node 7 allows only one device 801 to capture the common trunk.

The address decoder 9 (figl) provides for the addressing of devices 80 s

common highway. The device address code 80j is specified by register 77, representing a set of zeros and ones depending on the device address 80j. The operation of the comparison node 76 is synchronized by pulses coming from the synchronization input of the decoder 9 When the address of the device 80j specified by the register 77 coincides with the information on the inputs of the decoder 9, the output of the comparison node 76 appears pulses that arrive at the input of the AND 79 element. 2 addressable device 80j is free, then the pulses from the output of the element And 79 are posited to the C input of the trigger 78 (D input to the state of the logical unit), switching it to the one state. The potential from the output of the address decoder enters the sub-termination bus 23. C) the flip of the trigger 78 is performed by applying a logic zero level to the input of the prohibition of the address decoder, which is connected to the reset input of the trigger 78,

Claims (1)

1. A device for interfacing a common-line computer that contains two blocks of buffer memory, two counters, three triggers, a node for capturing a highway, a pulse generator, an address decoder, eight main amplifiers, the first AND element, the first OR element, two single-vibrators, and The first information input / output of the first main amplifier is connected to the information input of the second main amplifier and is the input-output of the device for connection to the information bus of the common line, information input / third the trunk amplifier is connected to the information output of the fourth trunk amplifier and is the input-output of the device for connecting the common trunk to the bus, the information input of the fifth trunk amplifier is connected to the information output of the sixth trunk amplifier and is the input-output of the device for connecting to the occupancy bus common highway, information The input of the seventh trunk amplifier is connected to the information output of the eighth trunk amplifier and is the input-output of the device for connecting a common bus to the synchronization bus, the first address inputs of the first and second blocks of the buffer memory being connected to the outputs of the first and second counters, overflow outputs which are connected to the counting inputs, respectively, of the first and the second trigger, the output of the second trigger is connected by the addressing input of the address decoder and to the first input of the first element I, the second input of which i connected to the outputs of the address decoder and with the information input of the fourth trunk amplifier, the output of the pulse generator is connected to the syncro. an input of the line acquisition unit, characterized in that, in order to increase the reliability of the transmitted information by providing an automatic return transmission of the data packet received by the transmitter device to the transmitter device, two counters are inserted into the device, 0 .five 0 five 0 five 0 five 0 two triggers, four OR elements, six AND elements, a comparison unit, a pulse distributor, the outputs of the first single vibrator and the third trigger are device outputs for connecting respectively to the first and second computer interrupt inputs, the information input of the first buffer memory block is connected to the first information the output of the second block of buffer memory and is the input-output of the device for connecting to the information input-output of the computer, the output of the fourth trigger and the first input of the second element AND are the output and input of the device for connecting respectively to the input of the recording requirement and the output of the transmission requirement of the computer, the recording input of the first block of the buffer memory is connected to the first input of the first element OR / and is the input of the device for connecting to the recording output of the computer, the first input of the second block the buffer memory is connected to the first input of the second OR element and is the input of the device for connection to the reading output of a computer; the installation input of the first counter is connected to the installation inputs of the second, third, fourth of the trunk pickup unit, with zero inputs of the first and second triggers, with the first zero inputs of the fourth and fifth triggers, and is the input of the device for connection to the installation output of the computer, while the output of the pulse generator is connected to the synchronous input of the pulse distributor and the first input of the third And element, the second input of which is connected to the start input of the first single vibrator, with the first input of the third OR element, and with the output of the fifth trigger, the second zero input of which is connected to the output of the fourth overflow The third counter, the output of which is connected to the second address input of the second block of buffer memory, the recording input of which is connected to the output of the first element AND, and the second input of the second element OR whose output is connected to the counting input of the second counter, the counting input of the first counter connected to the output of the first the OR element, the second input of which is connected to the first inputs of the fourth and fifth OR elements and distribute 1 with the first sync output l pulses, the second sync output, which is connected to the second inputs of the fourth and fifth OR elements, the outputs of which are connected respectively to the first read input of the first block of the buffer memory and the information input of the eighth trunk amplifier, the second information input and output of the first main the first amplifier connected to the first, second information outputs of the first block of buffer memory, with the second information output and information input of the second block of buffer memory, with information input of a decoded and the addresses, with the first information input of the comparison unit, the second information input and output of which are connected respectively to the information output of the second main amplifier and the information input of the third trigger, the output / third counter is connected to the second address input of the first block of the buffer memory, the second reading input which is connected to the counting input of the third counter, to the output of the fourth element I and to the synchronous input of the third trigger, the zero input of which is connected to the enabling input of the address decoder, with the information output of the fifth main amplifier and with the input of the prohibition of the main line gripping unit, the output of which is connected to the first inputs of the fifth, sixth I-elements, to the information input of the sixth main amplifier and the first input of the fourth And element, the second input of which is connected to the third input of the first element I, with the information output of the seventh trunk amplifier and the first input of the seventh element I, the output of which is connected to the start-up inputs, the second one-oscillator, the output of which is connected to the address decoder synchronous input, the information output of the third trunk amplifier is connected to here 293912 the second input of the seventh element And five 0 five five 0 five the control input of the pulse distributor, the enabling input of which is connected to the output of the fifth element AND, and to the second input, the third element OR, the output of which is connected to the input of the operating mode of the first main amplifier, the enabling input of which is connected to the output of the sixth element AND, the second input of which connected to the third input of the fourth element And with the zero output of the first trigger, the unit output of which is connected to the second input of the fifth element And and to the second input of the second element And whose output is connected to the input the house of the request. node for capturing the highway, the release input of which is connected to the overflow output of the third counter and to the second 4th zero input of the fourth trigger, the counting input of which is connected to the overflow output of the first counter, the output of the third AND element is connected to the third input of the fifth OR element, with the counting input the fourth counter and with the second read input of the second buffer memory block, the output of the second flip-flop is connected to the information input of the fifth flip-flop, the sync input of which is connected to the overflow output of the second and chetchika. 2, The device according to claim 1, TL and the fact that the node of the seizure of the highway contains a register, a counter and a trigger, and the counting input of the counter is the synchronous input of the node, the installation input of the counter, the first, second zero inputs, information input and output the trigger is a prohibiton input, a release input, a setup input, a request input and a node output, while at the master capture node — whether the register output is connected to the information input of the counter, the overflow output of which is connected to the trigger synchronous input. // 1gpf 2L IS 3S Ot U . „IUr ° K P. -rrtit n 6Ј62 “l t FIG. five Editor T. Parfenova Compiled by S. Pestmal Tehred M. Khodanych Order 8101/54 Circulation 668 The State Committee for Inventions and Discoveries under the State Committee on Science and Technology of the USSR was entered in 113035, Moscow, Zh-35, 4/5 Raushsk nab. Production and Development Combine Patent, Uzhgorod, st. Gagarin, 101 T Fm.z Thebes. H Proofreader O. Tsiple Subscription