SU1439612A1 - Device for interfacing computer with communication channel - Google Patents

Abstract

The invention relates to computing technology and can be used to build multi-physics computing systems. The aim of the invention is to increase the reliability of information exchange by providing the possibility of ahnaratratnogo control of the device. The device contains two blocks of buffer memory, a node for capturing a line, a shift register, an address decoder, three state register triggers, three counters, seven triggers, three WL elements, nine AND elements, three single vibrators, two bus driver, and a pulse generator. 1 з.п, ф-л, 3 Il.

Description

WITH

with about

The invention relates to computing technique and can be used to construct a multi-step calculation. systeg.

The aim of the invention is to increase the reliability of the exchange of lyieft by ensuring that the hardware control of the device operation when transmitting a packet to the device and holding the packet to its memory (loop mode) p as well as simplifying the device by reducing the lipid of the channel from: hzi and due to the possibility of transmitting control signals of capture and confirmation over the communication channel.

Fig, 1 prs.tsetavlena

from the device heme; in fig. 2 is a diagram of a node for capturing a highway in FIG. 3, the integration of a computer with the help of a proposed device into a multi-machine system

The device (FIG. 1) contains blocks 1 and 2 of the buffer memory, 5 counters 3 and 4, triggers 5–7 of the state register, decoder 8, address generator 9 pulses., Node 10 of the main line, trigger 11 and 12. And elements 13 and 14, an OR element 15, bus forks 16 and 17, a data line 18, a record 19 record, a read line 20, a write request line 21, a capture line 22, an input 23, and a junction 10, output 2A of node 10, reading line 25. input / output (trunk) 26 synchronization, information input / output (trunk) 27, shift register 28, counter 29s triggers 30-34, ЗЗ-ЗУ single-oscillators, AND 38-44 elements, OR 45 J 46 elements, node 47 output 47 10, release 48 release node. 10, inlet 49, confirmation of node 10, inlet 50 for synchronization of node 10, exit 51 of the communication channel of node 10, initial installation line 52, installation inlet 53

Node 10 capture master. .li contains (FIG. 2) counters 54-55, register 56, triggers 57 and 58, elements I 59 - 61 - I element I. PI 52.

On fig.Z computer labels 63. The proposed device 64,

The operation of the device is as follows.

Exchange between par.y E.VM 6.3.; and 63 j through devices 64 .; and 64; ,, through ipfor ;-( ayioppu magistrate- .. includes stages:

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verification by the initiator 63; sharing is busy to toast your device and when it comes to it. waiting for his release;

transfer of the data packet via line 18 from the computer 63 to the block 1 of the buffer memory of the device 64, -;

the capture device 64 information line 27;

checking the block 2 of the buffer memory of the device -64, i- in case of necessity waiting for its release;

transferring a data packet from block 1 of the buffer memory of the device fi to block 2 of the buffer memory of the device 64 ;;

transfer of the grigget from block 2 of the buffer memory of the device 64,. on line 18 in computer 63,

Neither the first stages of the Wearable Generation is carried out from the computer 63 ;. l-1, the last it - 63 :.

Work; - Stroys.tV ,. It is based on the initial installation of the devices b-, which is carried out by applying a negative impulse to the line 52 ,, According to this signal, counters 3 and 4 are set to maximum. state, triggers 5 and 6 of the STATUS register, triggers 30 and 34 are set to logic zero, and trigger 31 are in logic state 1e,

In devices 64, block 1 of the buffer memory is accessible from line 18, dap11yk to.pko, by writing, and block /. buffer memory - read only.

Writing data from the 1S line to the block, 1 buffer memory is contiguous; it is negatively implied on LEGEPIA 19 and reading .134-ix from the block. sa 2 buffer-. memory is accompanied by a negative impedance on line 20. According to the impedance of lines 19 and 20, respectively, recording occurs. Or, the readings of blocks 1 and 2. On the falling front of the impulse, on page 19 contains counter 3 is reduced by si-u .- | .1, y5, and by the forward impulse on line 20, reduction of counter 4 is reduced by one, lg-res of the written or readable word n blocks 1 and 2 of the buffer n bs-gi; gpt is the state of the b-outputs - :: revision counters 3 4

After the start of the 7th installation: on popk 21 there is a level. the ..li.i-nrniaiij analyzing -: otori ;, E. BM 633. -14396 starts entering the data packet into the block 1 of the buffer memory of its device 64. After entering the first word of the packet, a pulse appears at the output of the positive transfer of counter 3, which sets the trigger 5 of the state register to one, thereby removing the logical level units from line 21 o

After entering the package in block 1 computer 63; exposes the capture requirement on line 22 to the level of a logical unit.

ten

On the leading edge of this signal, in the state register trigger 6, a logical unit is recorded, which is fed to the input 23 of the requirement of the node 10 of the line capture. After resolving all sorts of conflicts to seize trunk 27 from various devices 64 and provide trunk 27 to a device at output 24 of node 10, a single potential appears, an output 51 of establishing a communication channel of node 10 shows an impulse that, through elements AND 43, OR 15 and the bus driver 16 of the device 64- and the synchronization highway 26 are fed to the inputs 49. Confirmation of nodes 10 of all devices 64. On the falling edge of this pulse at the outputs 47 of the confirmation of node 10 a positive potential appears, indicating that Tralee 27 captured. After the appearance of this signal at the output of element AND 42, a positive front appears, which enters the input of a single vibrator 37, which forms a positive pulse, which arrives at the inputs of a single vibrator 35 and an element OR 46 o At the output of a single vibrator 35 on the leading front of this pulse a negative impulse is formed, which initiates the reading of a word from the block 1 of the buffer memory, writing a unit to the trigger 30 and setting the counter 29. On the leading edge of this impulse, the content of the counter 3 decreases by one and ends and this pulse - unit installation at zero trigger input 32, which operates in the counting mode. The trigger 30, when set to one, resets the trigger 31 to zero. On the falling edge of the pulse at the output of the ISH 46 element, the word with is parallel to.

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 from the input of the register 28, the sdpigm is written to this register.

The rear edge of the pulse at the output of the one-shot 35 is shifted in time relative to the rear edge of the pulse at the output of the one-shot 37.

The clock pulses from the generator 9, the passage through the trigger 32, the element IL11 15 and the bus driver 16, go to the synchronization line 26, and from it through the bus drivers 17, the elements AND 41 and OR 46 to the synchronous input of the shift register 28, producing the same word shift from register 28 shift device on the falling edge of the pulses; The word in the serial code from the serial output of the register 28 through the elements And 39, IIS 45 and the tire driver 16 enters the information line 27, which through the bus drivers 17 enters the serial inputs of the shift registers 28 of all devices 64. On the falling edge of pulses on the synchronization of the shift registers 28, the word is written into these registers. Sync pulses are also fed to the input of the counter 29. On the trailing edge of the pulse, its content increases by one. The first in the packet is the address word. If the module is addressable, a single potential appears at the output of the address decoder 8.

After receiving the word at the output of the counter 29, a negative impulse is formed, which is fed to the Sikh- input of the trigger 12, which translates it into a single state. This impulse also arrives through the element AND 40 to the synchronous input of the counting trigger 33, its transfer to the state of logical one, and to the synchronous input of the trigger 30, its translation to the state of logical zero. If device 64 is addressable, then a positive potential appears at the output of trigger 11, which is stored for the entire transmission cycle of the packet. When the word is received by devices 64, the addressable device 64: through elements AND 44, OR 45 and bus driver 16 exposes a single potential to the information highway 27. On the trailing edge of the transfer pulse of the counter 29 at the output of the element And 14, a positive differential appears, which initiates, if block 2 of the buffer memory of the device 64 is empty, the appearance at the output of the one-oscillator 36 negative pulses which initiates reading of the word from the shift register 28 in devices. e 64-w block 2 of buffer memory. Along the trailing edge of this pulse, the counter unit 4 is incremented and the flip-flop 33 switches to zero, so the positive potential is removed from the information line 27. The difference from one to zero on the highway 27 is fixed in the flip-flop 31 / device 64 as a sign of word reception confirmation device 64j and the permission to issue to the trunk 27 the next word of the packet, which is located at the front at the entrance of the Finger 37. If the block 2 of the buffer memory of the addressable device 64 i is not, then the output 23. Nya Ullevi level

After the transfer of the entire packet at the output of the negative transfer counter 3 devices. an impulse is formed, on the falling edge of which the trigger 5 of the status register is transferred to the state of logical zero, set the requirement for writing on line 21 to the logical level. In device 64; after receiving the first word in block 2 of the buffer memory, an impulse is formed at the output of the positive transfer of counter 4, which transfers the trigger 34 to a state of logical one. As soon as the packet is transmitted, output 48 of node 10 of device 64-j forms a negative impulse, which removes the level of the logical unit from output 47 confirming the evil 10 of all 64 devices and zeroed, em trigger 6 of status register 64- . Zero at the output of the trigger - 6 register of the state | and initiates the removal of the logical unit level from the output 24 of the node 10 of the device 64 .. The response time of the computer 63j to the logical unit on line 21 is significantly longer than the time for the release of the highway 27 On the falling edge at the output 47 of the confirmation of the node 10 of device 64. the value of the trigger 34 is rewritten into the trigger 7 of the register of the register, thereby setting the reading requirement on line 25.

COMPUTER 63: starts reading data from block 2 of its buffer memory

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439612 6

Devices When reading a word, the value of counter 4 decreases by one. tsu, After reading the packet at the output of the negative transfer of the counter 4 of the device 64; a pulse is generated, the trigger trigger 34 and the trigger 7 of the state register, thereby removing the unit potential from line 25 of device 64,

The node 10 of the seizure of the line (figure 2) Fu1gktsioniruet as follows. In the initial state, the clock pulses from the synchronization input 50 through element 15 and 60 are fed to the input of counter 55, the input of which contains the binary value specified by register 56. When a single potential from input 23 of a demand for zero input of trigger 58 arrives, this trigger in device 64 is pulsed the transfer from the output of the counter 55 switches to a state of logical one. The transfer impulses at the outputs of the 55-node nodes of the line capture-10 are shifted in time relative to each other due to the difference in the codes set on the registers 56 of the devices 64. The higher the priority of the devices 64, the greater the binary value is at the output of the register 56. The pulse from the output of the counter 55 through the output 51 of the establishment of the communication channel and through the highway 26 synchronization enters the inputs 49. Confirmation of nodes 10 of the capture of the trunk of all devices 64, the same set counters 54 in yule and transfer to. zero triggers 57 splices; the sync pulse passing from synchronization inputs 50 to the input of counters 54, setting counters 55 and setting the unit to outputs 47 confirming all devices 64, Counter 54 controlling the transfer of words by magic-, 27, followed by output signals 26. If during the time determined by the intervals from setting the counters to zero until a negative transfer pulse occurs, there is no data transmission on the information highway 27s at the output of the counters. Then the counters, which generated this pulse, switch to zero of the flip-flops 57, removing the level of the logical unit from the outputs 47 of the confirmation. This pulse is through the elements OR 62 and 61 in the device that captures the highway.

thirty

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SO

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7. 4

it is transmitted to the release 48 of release, thereby setting the trigger 6 of the status register and removing the logical unit from the input 23 of the requirement, thereby triggering the trigger 58, the trunk acquisition node 10, which is built according to this principle, eliminates; simultaneous seizure of a trunk by two or more devices. The loop mode is designed to ensure the control of the reliability of the device and is carried out by transferring data through the information line 27 transmitted from the buffer memory unit 1 of the device 64 to the buffer memory block 2 of the same device via a bus; 17.The introduction of this mode allows analyzing the quality of work of the transmitting / receiving circuits of devices. With

This is the address of the receiver 64

J

J

specified by the position code in the address word of each packet, which, by virtue of the same connection to line 27, of the devices of the system, allows simultaneous access to block 2 of the buffer memory of the receiver 64; and ne

64 devices.

Claims (2)

1. A device for interfacing a computer with a communication channel, which contains two blocks of buffer memory, two counters, three triggers of the status register, an address decompressor, a generator of impulses, a line capture unit, two triggers. Hera, two elements AND, the first element OR, two bus driver, the group of information inputs of the first block of buffer memory and the group of information outputs of the second block of buffer memory form a group of inputs-outputs of the device to connect to the group of information inputs-outputs of a computer, the first counting input of the first counter is connected to the recording inputs of the first block of the buffer memory .and is the input of the device for connecting to the computer recording step, the first counting input of the second counter is connected to the read input of the second block  the buffer memory is the input of the device for connecting to the output of reading the computer, the zero output of the first trigger of the status register and the sync input of the second trigger of the state register are the output and input 4396 Q d 20 25 thirty 35 45  , 50 55 128 the device for connecting the write request and the output of the computer capture request; the unit output of the third state register trigger is the output of the device for connecting the computer read request to the input; the first information output of the first bus driver and the first information input of the second bus driver form input-output device for connecting to the synchronous input-code of the communication channel, the second information output of the first bus driver and the second information input of the second bus the generator forms the input-output of the device for connecting to the information input-output of the communication channel, while the groups of the bit outputs of the first and second counter are connected respectively to the groups of address inputs of the first and second blocks of the buffer memory, the output of the first IZH element is connected with the first information input of the first bus driver, the output of the first trigger is connected to the first input of the first element AND, characterized by V in that, in order to increase the reliability of information exchange by providing These devices control the device, a shift register, a third counter, four flip-flops, three mono-vibrators, seven AND elements, two OR elements are entered into it, and the setup input of the first counter is connected to the setup input of the second counter, with zero input of the first state register trigger, with zero inputs of the second, third flip-flops, with a single input of the fourth flip-flop, with installation inputs of the capture unit Mages-i and the input of the device for connection to the output of the computer's initial setup, the output of the second The state register trigger is connected to the input of the requirement for the line capture unit, with the first input of the second element I, and is the output of the device for connecting to the computer interrupt input, the output of the pulse generator is connected to the synchronous input node for the highway triggering terminal, which connect tn with the first input of the first element ilH, the second input of which is connected by the I output of the second element I, the second input of which is connected to the output of establishing a communication channel of the line acquisition unit, the output of which is connected to the first input of the third element I and the first input of the fourth element I, the second input of which is connected to the output of the fourth J flip-flop, the zero input of which is connected to the output of the third flip-flop and the second input of the third element I, the output of which is connected to the zero input of the fifth trigger and the first input of the fifth element I, the second input of which is connected to the information output of the shift register, information input which is connected to the fourth sinhrrvhodom. trigger and with the first information output of the second bus driver, the second information output of which is connected to the first, the input of the sixth element And and to the input of the confirmation of the node of the seizure of the highway, the output ten which is connected to the first input of the eighth element And, the second input of which is connected to the output of the seventh trigger, the synchronous input of which is connected to the output of the ninth element And, the first input of which is connected to the synchronous input of the third trigger, with the output of the transfer of the third counter, to the second input of the first .I element and with the synchronous input of the sixth trigger, whose input is connected to the synchronous input of the first trigger, whose information input is connected to the output of the address decoder 4g, the information group of the inputs is connected to the groups th fifth informational outputs of the shift register and the group of information inputs of the second block of the buffer memory write input connected to the counting input vtorych second counter, a data input of the ninth flip-flop, with the output of the third odkozibratora with 20 the release of which is connected to well ™ 25 by the third input of the seventh element AND, the output of which is connected to the installation input of the third counter, the counting input of which is combined with the house of the sixth element I and the second the output of the first trigger register co. Q input of the second element OR, the output of the sync input and the single input of the fifth element And is connected to the first the left input of the second state register trigger, whose information input is connected to the third input of the fourth element AND and the c-unit not a hundred. which are connected respectively to the negative and positive transfer outputs of the first counter, the second counting input of which is connected to the third input of the third element I, to the first input of the seventh element I, to the unit input of the third trigger, to the output of the first odiovibrator, to the input of the operation of the shift register NS input reading the first block of buffer memory, the information information group of which is connected to the group of information inputs of the shift register, the synchronous input of which is connected to the output of the second element. OR, the first input of which is connected to the input of the first single vibrator and with the output of the second single vibrator, the input of which is connected to the output of the fourth And element, the fourth input of which is connected to the second input of the seventh element And,. sync input i of the third trigger of the state register, with the output of the confirmation of the main line gripping unit, with the second input of the sixth element I, with zero inputs of the sixth, seventh triggers, with zero input of the first trigger, output 40  the input of the third element OR, the second input and output of which are connected respectively to the output of the eighth element AND and the second information input of the first bus driver, the input of the third one-oscillator is connected to the output of the singing element AND the third input is connected to the key output of the third state trigger , the zero and informational inputs of which are connected to the tricks of the second trigger, the single input and synchronous input of which are connected respectively to the outputs of positive and negative transfer of the second / counter. 2. The device according to claim 1, characterized in that the gripper node of the main line contains two counters, two triggers, a register, three elements I., an element ИШ1, with the first input of the first element I connected to the first input of the second element And Synchronized input node 5, the first input and the stroke of the third element And are respectively the installation input and you release the node release, the installation input of the first counter is connected 45 50 which is connected to the first input of the eighth element And, the second input of which is connected to the output of the seventh trigger, the synchronous input of which is connected to the output of the ninth element And, the first input of which is connected to the synchronous input of the third trigger, with the output of the transfer of the third counter, to the second input of the first .I element and with the sync input of the sixth trigger, whose input is connected to the syncro; the input of the first trigger, the information input of which is connected to the output of the address decoder, the nformation group of the inputs is connected to the information group of the 5th outputs of the shift register and the information input group of the second block of the buffer memory, the recording input of which is connected to the second counting input of the second counter, with the information input of the ninth trigger, with the output of the third odometer 0 the input of the third element OR, the second input and output of which are connected respectively with the output of the eighth element AND and with the second information input of the first bus form; The third input one-shot is connected to the output of the output element I, the third input of which is connected to the Kula: the output output of the third state register trigger, the zero and information inputs of which are connected to the tricks of the second trigger, the single input and sync input are connected respectively to the positive outputs and negative second / counter carry. 2. The device according to claim 1, characterized in that the gripping node of the main line contains two counters, two triggers, a register, three elements I., an element ИШ1, with the first input of the first element AND connected to the first input of the second element AND synchronous input node 5, the first input and output of the third element And are respectively the installation input and you release the release node, installation. the first counter input is connected With the synchronous input of the first trigger and is the input of the node confirmation, the zero output of the first trigger is connected to the second input of the first element I and is the output of the node confirmation, the transfer output of the second counter is connected to the synchronous input of the second trigger and the zero input and the single output of the second trigger are, respectively, the input of the demand and the output of the node, while at the node for capturing the highway the zero output of the second trigger is connected to the first, input of the OR element, the output and the second input of which is connected to the second input of the third element I and the transfer output of the first counter, also connected to the second input of the second element I and to the single input of the first trigger, whose single output is connected to the installation input of the second counter and with the third input of the second element And, the output of which is connected to the counting input of the second counter, whose information input is connected to the output of the register, the output of the first element And connected to the counting input of the first counter. 1