SU1388883A1 - Inter-module communication device for a message switching system - Google Patents

Abstract

The invention relates to the field of computing and can be used in the construction of low-speed fault-tolerant communication lines. The aim of the invention is to simplify the device and increase the speed by implementing the direct memory access mode. Realization of direct memory access is achieved by changing the device scheme of the inter-modular communication and saves the computational resources of the module control processor. The device is designed for use of the in-car line according to OST 11.305-903-80. 2 з, п, ф-л, 5 Il.

Description

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The invention relates to computing and can be used in the construction of low-speed communication lines increased fault tolerance.

The aim of the invention is to control the device and increase speed by implementing a direct memory access mode.

Figure 1 shows the connection diagram of the message switching modules; na - block diagram of the module; Fig 3 is a functional diagram of an inter-module device; communication; on FIG4 - the functional scheme of the access arbiter to the highway; Fig 5 shows a functional scheme of the address register

The message switching system contains N modules l, oo ,, 4, ooo, N interconnected by the main 5 and reserve 6 communication lines. Each module contains an intermodule communication device 7, a processor 8, a memory device 9 and controllers 10 peripherals connected to the system backbone 11

The intermodular communication device contains transceivers 12 and 13, having linear outputs 14 and 5, elements AND 16 and 17, elements 18 and 19 matching, linear inputs 20 and 21, elements AND 22-25, a trunk access arbiter 26, node 27 interrupt the interface circuit 28, the element NOT 29, the circuit 30 of the address registers 1, the node 3 of the passive and the node 32 of the active interface of the interface circuit

Arbitrator of access to the highway contains the encoder 33 priorities, elements OR 34 and 35, the first 36, the second 37 and the third 38 inputs the arbitrator, the first 39 and the second 40 elements AND, the fourth nachy 41 of the arbitrator, the element NOT 42, five are 43 and the sixth 44 inputs of the arbitrator, the third 45 and fourth 46 elements And, the first output 47 arbiter, inverter 48, the second 49, third 50 and fourth 51 outputs of the arbitrator ,,

The address register circuit contains multiplexer 52, triggers 53 and 54,: 1 element NOT 55, element OR 56, single vibrator 57, element 5.8 of memory, element OR 59, counter 60 and has the first 61, second 62, third 63 and fourth 1 64 inputs, first 65 and second 66 outputs, as well as information input - output 67 „

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The device works as follows

Information intended for inter-unit communication is transmitted via the main inter-module communication lines 5, which form a unidirectional ring-shaped circuit for connecting modules. The presence of intermodular links 6 connected in this manner ensures the preservation of a closed link to the ring by transmitting information along the backup direction in the area of the failed module or link of the main direction of intermodular communication

The module (FIG. 2) operates as a single bus microcomputer. The exchange of information and all interactions between devices 7-10 are carried out using system bus 11 Processor 8 under the control of programs located in memory 9, performs the necessary computational processes and logical processing of information, as well as interaction with external devices and communication channels with the help of controllers 10. Intermodular interaction is carried out using an intermodular communication device 7 that performs high-speed information exchange by the method of direct memory access. s

Transmission and reception of information between modules is carried out by a serial code over two-wire communication lines 5 and 6 Independent transmission of information over two duplex channels of inter-module communication and exchange of an inter-module communication device with a memory device 9 (direct access method) is carried out in blocks of fixed length21y. Intermodular exchange is initiated by the transmitting module. The transfer of a block of information begins with the entry of the starting address of the transmitted block of information into the 30 address registers. The starting address is entered by a signal from the output of the passive interface node 31 of the interface circuit 28. .eleven. In this case, the arbitrator generates on the output 50 the initiation signal of the active interface reading node 32 — The active interface node 32 uses the system trunk 11 at the specified transmission address to read the byte of information on the memory and enter it into transceiver 12 or 13 through element 24 or 25 depending on the low-order bit of the transfer register address, in which the initial address of the transmitted block of information was recorded, in the receiving module, the received information byte through the arbiter 26. accessing the trunk initiates the node 32 of the active write interface The last writes the received byte of information into the allocated memory area, the starting address of which is determined by the receiving address of the 30 address register circuit. In this case, the received information byte from the corresponding transceiver is read by the output of the node. the active interface to the inputs of the element 22 and 23; the formation of the signal at the output of the element 22 and 23 depends on the signal determining the number of the receive register that is generated by the access magician 26 Stray and enters the inputs of the elements And 22 and 24 and the element: NOT 29 o The signal from the output of the element 22 (or 23) in the required phase of the interface exchange produces the information received by transceiver 12 (or 13) to the system trunk 11 and through matching element 18 (or 19) outputs to the input link as a feedback signal Ready to Receive, This signal is output to the transmitting module using AND 16 (or 17) and initiates a reading through the access trunk arbiter 26 and transmitting the next byte of the information block. Modification of the addresses of reception and transmission in the process of transferring the next bytes of information is carried out in the circuit 30 of address registers by the falling edge of the signal of address bump coming from the active interface node 32 in the address phase of the interface exchange with the storage device 9 via the system trunk 11 pattern 30. address registers, an overflow signal is generated. The end of the block, which enters the node 27 of the prereggany interface circuit 28 and causes the processor to close, notifies it of the end of the transmission of the information block

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Thus, the transfer of a block of information is carried out by direct access to the memory without software control. The computational resources of the module are used only when initiating the exchange (recording the initial addresses of information blocks) and when servicing the end-of-block interrupt

Trunk access arbiter 26 is designed to provide conflict-free access to the trunk in case of simultaneous requests for direct memory access while simultaneously receiving and transmitting information via inter-module communication channels and operates as follows

The basis of the arbiter is the priority encoder 33, which at outputs 47 and 48 forms a code corresponding to one of the signals (requests) received at the input in a sequence corresponding to the priorities of the inputs. At the same time, output 47 determines the direction of the exchange (read or write), which corresponds to the transmission or reception of information, and the output 49 is the number of the intermodular communication channel. The signal from the output of the priority selector 33, received by the 1st input of the And 45 and 46 elements, indicates the fact of any request for direct access and, using the signal of the exchange direction, the HE element 48 and the And 45 and 46 elements, initiates the active interface node by writing. or by reading at outputs 50 or 51, respectively. Direct access request signals by writing to inputs 36 and 37 of the trunk access arbiter 26, generated by transceivers 12 and 13, when receiving a byte of information, go directly to the priority encoder 33, and Direct read access request channels at inputs 38 and 44, allocated by AND elements 16 and 17 and being request signals by the receiving side of the next byte of information, arrive at the priority encoder 33 through ISh elements 34 and 35 respectively. Peg signals of exchange initiation are generated elements And 39 and 40 when a signal arrives at them, recording the initial address of the transmission from the output of node 31 of the passive

Interface. At the same time, the formation of a read access request signal for the corresponding transfer direction — the main one (element 39) or the reserve one (element 40} is determined by the state of the signal at input A3 of the arbiter 26, depending on the address of the transfer address register, c. which recorded the initial address of the transmitted block of information

The address registrar scheme is intended for storing and modifying the current addresses of the transmitted and received information according to the main one; and backup directions and works as follows.,

For storage of addresses for reception and transmission for two directions, SRI requires four registers, which are organized in memory element 58. The initial and current addresses are stored in memory element 58 from system master 11 via counter 60, the choice of one of four registers the current address is determined by the signals at the address inputs of the memory element 58, which are output from the multiplexer 52o. In the initial state, the multiplexer 52 ensures that the address values from the second inputs (the upper one) 6) directions connected to the outputs of the flip-flops 53 and 54, which, in turn, the value of the address bits that determine the address register number in memory element 5B, is entered from the system master 11 by the address tracking signal sent to trigger inputs 53 and 54, the entry of information (the starting address of receiving or transmitting a block of information) to memory element 58 at an address determined by the state of triggers 53 and 54. is effected by a recording signal from the output of the passive interface node 31 through the element OR 59 to the input recordings of the memory element 58 At the same time, the same recording signal through the OR element 56 permits the recording of information recorded in the memory element 58 into the counter 60, thereby ensuring its passage to the information inputs of the memory element 58 In the direct access mode (during transmission block of information; multiplex

The litter 52 performs the switching of the address of the required register from the first (lower according to the diagram in FIG. 5) direction, where it, in turn, comes from the output of the highway access arbiter 26. The address switching to the output of the multiplexer 52 from the second direction is performed by the address output signal. the input 64 of the address register circuit 30, coming from the output of the node 3.2 of the active interface a, which also blocks the first direction of the multiplexer 52 with the help of the element HE 55, uses the element OR 59 to output the current value of the address of the required register to the trunk and with the help of the element OR 56 passing the output value of the address to the input of the memory element 58 through the counter 60. The one-shot 57 is triggered by the back edge of the address output signal, the signal from the output of which performs modification (increment by one) ad ENA recorded in the counter 60, and recording via OR gate 59 the new address value in the memory element 58

The transceivers 12 and 13 used in the inter-module exchange device are parallel-to-serial converters designed for byte-by-byte serial transmission of information with start-stop synchronization.

Formula

the invention

Claims (3)

1 "An inter-module communication device for a message switching system comprising two transceivers and an interface circuit, the line inputs of the first and second transceivers being the first and the second inputs of the link, respectively, the line outputs of the first and second transceivers being the first and second outputs the communication lines of the node, respectively, the information input-output of the interface circuit is the information input-output of the node, characterized in that, in order to simplify the device and improve speed due ReA mode dp tion of forward access to the memory incorporated therein schest elements and two elements matching element NOR circuit address registers and the access arbiter, where the outputs of the first and second matching elements are connected to the line inputs of the first and second transceivers, respectively, the inputs of the first and second matching elements are connected to the outputs of the first and second I elements and to the read inputs of the first and second transceivers, respectively; the inputs of the entry of the first and second transceivers connected to the outputs of the third and fourth elements And, respectively, the first input of the first element And is connected to the first input of the third And, with the first output of the access arbiter, with the first input of the interface circuit, with the input of the element NOT and with the first input of the address registers circuit, the second input of the first element And connected with the first input of the second element, And with the output of the interface circuit recording, output the reading of which is connected to the first input of the fourth and the second input of the third And elements, the output of the element is NOT connected to the second inputs of the second and fourth And elements, the outputs of the indication of the reception of the sign of the first and second transceivers are connected to the first and second The inputs of the access arbiter to the trunk, respectively, the inputs for registering the reception phase of the sign of the first and second transceivers are connected to the first inverse inputs of the fifth and sixth elements And, respectively, whose second direct inputs are connected to the linear outputs of the first and second transceivers, respectively, the fifth and sixth inputs elements And are connected to the third and fourth inputs of the access arbiter to the highway, respectively, the second output of the access highway arbiter is connected to the second inputs of the address register circuit strov and. interface circuit, the fifth input of the access arbiter the trunk is connected to the first output of the address register circuit, the sixth input of the access arbiter is connected to the third input of the address register circuit and the passive interface of the interface circuit, the third and fourth outputs of the access arbiter are connected to the read and write inputs of the interface circuit, respectively output 0 five 0 Q five 0 five five 0 five which is connected to the fourth input of the address register circuit, the second output of which is connected to the third input of the interface circuit, information inputs - outputs of both transceivers are connected to the information input / output circuit of the address register and information input-output of the interface circuit, 2, The apparatus according to claim 1, wherein the access arbiter contains 1 priority priority, four AND elements, two liHH elements and two NO elements, the first and second inputs of the priority encoder being the first and second inputs of the arbiter respectively, the first inputs of the first and second OR elements are the third and fourth inputs of the arbiter, respectively, the third and fourth inputs of the priority encoder are connected to the outputs of the first and second OR elements, respectively, the second inputs of which are connected to the outputs of the first and of the second element And, respectively, the first inputs of which are connected to the sixth input of the arbiter, the second input of the second element. And connected to the output of the first element NOT, the input of which is connected to the second input of the first element And and the fifth input of the arbiter, the first and the second outputs of the priority encoder are the first and second outputs of the arbiter, respectively, the third output of the encoder. Priorities are connected to the first inputs of the third and fourth And elements, the outputs of which are the third and fourth outputs of the arbitrator, respectively, the second input of the fourth And element connected to the output of the element NOT, the input of which is connected to the second input of the third AND element and to the first input of the priority encoder. 3. The device according to claim. 2, wherein the address register circuit comprises a multiplexer, a memory element, a counter, two triggers, two W1I elements, a single vibrator and an element NOT, and the information input of the counter is connected to the information output of the memory element and with the information input-output of the circuit, the information output of the counter is connected to the information input of the memory element, the address inputs of which are connected to the outputs of the multiplexer, the first and second information inputs of the first direction of which are first and second in The first and second information inputs of the second direction of the multiplexer are connected to the outputs of the first and second flip-flops, respectively; the output of the first flip-flop is connected to the first output of the circuit; the first inputs of the OR elements are connected to the third input of the circuit; with the fourth input of the circuit, with the BXoftoM control of the first direction of the multiplexer, with the input of the one-shot and with the input of the read of the memory element. five the recording input of which is connected to the output of the second OR element, the second input of which is connected to the output of the one-shot and the clock input of the counter, the recording input of which is connected to the output of the first OR element, the information inputs of the first and second triggers of the information input- the output of the circuit, respectively, the trigger synchronization inputs are connected with the bit accompanied by the address of the information input / output circuit, the counter overflow output is the second output of the circuit, the output is ementa is coupled to the control input of the second multiplexer direction of FIG. P Fig2 fie.Z Editor E. Kopcha Compiled by I. Andreev Tehred M. Khodanych. Order 1582/51 Circulation 704 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 srigL .E Proofreader S. Shekmar Subscription