JP2629027B2 - Interface method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding an interface system for performing data communication using a bidirectional bus, a three-state buffer is provided between a device and a bidirectional bus, and is driven by a read signal and terminated. The other device captures data from a bidirectional bus using a write signal with a shorter length, and uses a bidirectional bus to connect two devices having different operation timings for communication. A bidirectional bus provided between the devices to be connected, a bidirectional three-state buffer provided between the own device and the bidirectional bus, and a termination of a write signal transmitted from the own device and used by a partner device. And a write signal shaping circuit for shortening the portion. When reading, the own device sends a read signal to the partner device to send data to the bidirectional bus and raises the read signal. The data input to the 3-state buffer and sent to the bidirectional bus are taken into the device itself. On the other hand, at the time of writing, the device inputs a write signal to the state buffer to transfer data to the bidirectional bus (1). )
And the other device takes in the data from the bidirectional bus by a write signal whose write signal shaping circuit shortens the end portion of the write signal.

[Industrial applications]

The present invention relates to an interface system for performing data communication using a bidirectional bus.

[Problems to be solved by the prior art invention]

Conventionally, when, for example, the device A and the device B mutually communicate data using a bidirectional bus as shown in FIG. 1 (c), FIGS. 4 (a), (b), (c) and As shown in FIGS. 5 (a), 5 (b) and 5 (c), if the operation timings of the interfaces to be interfaced are different, they cannot be connected to each other and cannot communicate. there were. More specifically, the apparatus B to the apparatus A
In FIG. 4 (b), when data communication was performed, data was output too much for, for example, 63 ns. When data communication is performed from the device A to the device B, for example, 7 ns in FIG.
Data retention time was insufficient during the period.

According to the present invention, a three-state buffer is provided between a device and a bidirectional bus, and is driven by a read signal. At the same time, a partner device fetches data from the bidirectional bus by using a write signal whose terminating is shortened. Two different
It is intended to communicate between two devices by using a bidirectional bus.

[Means to solve the problem]

 Means for solving the problem will be described with reference to FIG.

In FIG. 1, a bidirectional bus 1 transfers data bidirectionally between devices.

The three-state buffer 2 is a buffer provided between the device and the bi-directional bus 1.

The write signal shaping circuit 3 sends out a write signal shaped by shortening the end of the write signal.

[Action]

According to the present invention, as shown in FIG. 1, a three-state buffer 2 is provided between a device A and a bidirectional bus. The data output to the directional bus 1 is fetched (read). On the other hand, at the time of writing, the processor A outputs the data to the bidirectional bus via the three-state buffer 2 and the write signal shaping circuit 3 shortens the termination. The processing device B takes in (writes) data from the bidirectional bus 1 using a write signal.

Therefore, by providing the three-state buffer 2 and the write signal shaping circuit 3, it becomes possible to mutually exchange data via the bidirectional bus 1 between the devices A and B having different operation timings.

〔Example〕

 First, the overall configuration will be described with reference to FIG.

In FIG. 1 (c), the devices A and B are devices (IO ports and the like) having different operation timings, for example, having operation timings shown in FIGS. 4 and 5 (described later). .

The bidirectional bus 1 is a bus for transferring data bidirectionally.

▲ and ▼ are read signals and write signals to be transmitted in response to the determination of the direction of the bidirectional bus 1 by the device A. Apparatus A has the configuration shown in FIGS. 1A and 1B. The write signal shaping circuit 3 may be included in the receiving device B.

Next, the configuration and operation at the time of reading, that is, when data communication is performed from the device B to the device A, will be described in detail with reference to FIGS. 1A and 2A.

In FIG. 1A, the three-state buffer 2 is included in the device A. When an L-level read signal is input from the device A (when reading), data is transferred from the bidirectional bus 1. The data is taken into the device A. When an H-level read signal is input to the three-state buffer 2 (at the time of writing), data is output from the device A to the bidirectional bus 1.

Therefore, as shown in FIG. 2 (a), when data communication is performed from the device B to the device A via the bidirectional bus 1, the device A notifies the device B of a read signal and transmits the read signal to the device B.
When the output data is taken in through the three-state buffer 2, it disappears as shown by the solid line at the rising edge of the end of the read signal in FIG. Can be prevented. This enables data communication from the device B having different operation timing to the device A via the bidirectional bus 1 in FIG. 4 (to be specifically described later with reference to FIG. 4).

Next, the configuration and operation at the time of writing, that is, when data communication is performed from the device A to the device B will be described in detail with reference to FIGS. 1 (b), 2 (b) and 3.

FIG. 1 (b) The write signal shaping circuit 3 is included in the device A, and when an L level write signal is input from the device A (when writing), as shown in FIG. 2 (b). And sends a write signal having a shorter end to the device B. This is because the end of the input original write signal is shortened by a predetermined clock pulse by using the shift register 3-1 as shown in FIG. A write signal is generated.

Therefore, as shown in FIG. 2 (b), when data communication is performed from the device A to the device B via the bidirectional bus 1, the device A notifies the device B of a short-terminating write signal to the device B, and When the data output to the bus 1 is taken inside the device B, by shortening the portion ', it is possible to solve the problem of insufficient data retention time shown in FIG. 5 (b). . Thereby, it becomes possible to perform data communication from the device A having different operation timing to the device B via the bidirectional bus 1 in FIG.

Next, a specific example of a solution to the difference in operation timing when reading the device A and the device B (when transferring data from the device B to the device A via the bidirectional bus 1) will be specifically described with reference to FIG. I do. Here, the fourth (a) is the device A
FIG. 4 (b) shows the output timing of the device B (data output timing to the bidirectional bus 1), and FIG. 4 (c) shows the explanation of each operation. FIG. 4 (d) shows the conditions necessary for performing communication via the bidirectional bus 1.

For the devices A and B having the operation timings shown in FIGS. 4A and 4B to communicate via the bidirectional bus 1, the conditions shown in FIG. 4D are required.

The condition (a) is originally satisfied as shown in FIGS. 4 (a) and 4 (b).

In the condition (b), <is not satisfied, and in this example, 63 ns data is output too much as shown in
As described above, FIG. 1 (A) is provided with the 3-state buffer 2 in the device A, and the end of data to be driven by the read signal and taken into the device A from the bidirectional bus 1 is cut as shown in FIG. 2 (A). Then, apparently from the apparatus A, it is forcibly set to $ 0. As a result, the condition (b) is satisfied from the viewpoint of the apparatus A.

The condition (c) is originally satisfied as shown in FIGS. 4 (a) and 4 (b).

As described above, by providing the three-state buffer 2 in the device A at the time of reading and driving by the read signal, it becomes possible to satisfy the condition for performing the communication shown in FIG.

Next, with reference to FIG. 5, a specific example of a solution of the difference in operation timing between the device A and the device B at the time of writing (when data is transferred from the device A to the device B via the bidirectional bus 1) will be specifically described. I do. Here, the fifth (a) is the device A
5 (b) shows the read timing of the device B, FIG. 5 (c) shows the description of each operation, and FIG. 5 (d) shows the output timing via the bidirectional bus 1. Indicates the conditions required for communication.

In order for the devices A and B having the operation timings shown in FIGS. 5A and 5B to communicate via the bidirectional bus 1, the conditions shown in FIG. 5D are required.

The conditions (a) and (b) are originally satisfied as shown in FIGS. 5 (a) and 5 (b).

Since the condition (c) is not satisfied and the data retention time of 7 ns is not enough in this example as shown in (1), the write signal shaping circuit 3 described above in FIG. The write signal is notified to the device B, and the end of the read timing of the device B is shortened as shown in FIG. 2 (b), that is, the end of FIG. The top is shifted to the left to solve the problem of insufficient 7ns data retention time. As a result, the condition (c) is satisfied when viewed from the device B.

As described above, when the write signal shaping circuit 3 is provided in the device A or the device B at the time of writing, and the device B takes in the data by the write signal whose terminal is shortened, the condition for performing the communication shown in FIG. It is possible to satisfy.

〔The invention's effect〕

As described above, according to the present invention, when data communication is performed between devices via the bidirectional bus 1, the three-state buffer 2 and the write signal shaping circuit 3 are provided to absorb a difference in operation timing. Therefore, efficient and high-speed data communication can be performed by directly connecting devices having different operation timings, for example, between IO ports using a bidirectional bus.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2, 4, and 5 are explanatory diagrams of an interface, and FIG. 3 is a waveform diagram of FIG. In the figure, 1 is a bidirectional bus, 2 is a 3-state buffer, 3
Denotes a write signal shaping circuit, and 3-1 denotes a shift register.

Claims (1)

(57) [Claims] An interface system for performing data communication using a bidirectional bus, comprising: a bidirectional bus (1) provided between devices to perform data communication; 3
A state buffer (2) and a write signal shaping circuit (3) for shortening the end portion of a write signal sent from the own device and used by the other device, and the own device sends a read signal to the other device at the time of reading. To send data to the bidirectional bus (1) and input a read signal to the three-state buffer (2) to fetch the data sent to the bidirectional bus into its own device. A device inputs a write signal to the state buffer (2) and transfers data to the bidirectional bus (1).
And the other device takes in data from the bidirectional bus (1) by a write signal whose write signal shaping circuit (3) shortens the end of the write signal by the write signal shaping circuit (3).