JPS6361533A - Serial data transfer device - Google Patents

Abstract

PURPOSE:To transfer data and confirm data transfer only with two signal lines, namely, a clock line and a data line by providing a master station as well as a slave station with a means which outputs a reception confirmation signal to the data line and a means which detects this signal. CONSTITUTION:When a serial clock source flag 350 is set, a pertinent serial data processor 300 is the master station An ACK control circuit 355 of the master station 300 has the function to confirm that the reception confirmation signal is outputted onto a serial data line 320 and the function to output the reception confirmation signal by driving the line 320 to the low level. A slave station 310 has the same constitution as the processor 300, and its ACK control circuit 365 has the function to output the reception confirmation signal to the line 320 similarly to the circuit 355 of the master station 300 and the function to detect the reception confirmation signal (in the low level) inputted through the line 320. Thus, data transmission and reception are confirmed by two lines, namely, the serial data line 320 and the serial clock line 321.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that has a plurality of semiconductor chips, such as a microcomputer, and performs serial data transfer with each chip. The present invention relates to a serial communication device that uses one data line to transmit and receive serial data in synchronization with a clock.

[Conventional technology]

Data can be transferred between multiple semiconductor processing chips (hereinafter referred to as LSI chips) by using an 8-bit or 16-bit data bus, or by using one data line in a time-sharing manner to transfer data one bit at a time. There is a method of serial transfer.

The latter is the simplest method for connecting LSI chips because it requires only two signal lines, a data line and a clock line, to connect the chips.

[Problem that the invention seeks to solve]

However, conventionally proposed serial data transfer devices cannot completely perform serial transfer using only two signal lines, a clock line and a data line. In other words, serial transfer is performed using one data line.
In addition to being able to correctly detect the start and end of transfer, it is also necessary to confirm whether the data sent from the transmitting side has been correctly received by the receiving side. Therefore, conventionally, another signal line had to be used for this confirmation. Therefore, serial transfer cannot be performed using only two signal lines, a clock line and a data line.

Therefore, the present invention has two clock lines and a data line.
An object of the present invention is to provide an improved serial transfer device capable of transferring and confirming serial data using only real signal lines.

〔Example〕

FIG. 1 shows a configuration diagram of a serial data transfer device according to an embodiment of the present invention. In addition, the serial data transfer device is 1
A plurality of slave stations can be multi-connected to one master station, but in order to simplify the explanation, serial transfer between one master station and one slave station will be described here.

The first serial data processing device (master station) 300 is
There is a shift register 301 inside. Serial clock generation circuit 302. Serial data terminal 303, serial clock terminal 304. Data processing unit 306. It has a serial clock source flag 350° ACK control circuit 355.

The shift register 301, data processing unit 306, and serial clock source flag 350 are connected by an internal data bus 305 consisting of a plurality of bits. Data processing section 30
6 is a process of reading and writing transmitted and received data to the shift register 301 via the internal data bus 305;
and sets and clears the serial clock source flag 350.

The output end of the shift register 301 is connected to an output line driver 352 for driving the serial data line 320.
It is connected to the serial data terminal 303 via.

An external serial data line 320 is connected to the serial data terminal 303. The serial data terminal 303 is connected to the shift register 3 via an input line buffer 353.
Connected to the input terminal of 01.

Thus, serial data can be transmitted and received.

Serial clock generation circuit 302 generates a serial clock and is connected to serial clock terminal 304 via clock driver 354 . The serial clock source flag 350 is a flag for selecting a serial clock source, and when this serial clock source flag 350 is set, the serial data processing device 300 is a serial clock supply source, that is, a master station. Become. Master station is clock driver 3
54 to output the output of the serial clock generation circuit 302 from the serial clock terminal 304. on the other hand,
When the serial clock pulse flag 350 is cleared, the serial data processing unit 300 becomes a slave station that receives a serial clock from another device and performs transmission/reception processing. In this example, it is a 300t master station,
310 is assumed to be a slave station. The master station and slave station may have the same circuit configuration. The serial clock selected under the control of the serial clock flag 350 or the serial clock input from the outside is used as a shift clock for the shift register 301.

The ACK control circuit 355 connects the serial data line 320
It has a function of fully confirming that a reception confirmation signal has been output on the serial data line 320, and a function of outputting a reception confirmation signal by driving the serial data line 320 to a low level.

Second serial data processing device (here slave station)
310 has the same Ω configuration as the first serial data processing device 300, and includes a shift register 311 and a serial clock generation circuit 312. Serial data terminal 313. Serial clock terminal 314. Data processing unit 316. Serial clock source flag 360. It has an ACK control circuit 365.

The shift register 311, data processing unit 316, serial clock, and cross flag 360 are connected to the internal data bus 315.
connected with. The data processing unit 316 performs reading and writing of data transmitted and received from the shift register 311 via the internal data bus 315, and sets and clears the serial clock source flag 360. The output end of the shift register 311 is connected to a line driver 3 for driving the serial data line 320.
62 to the serial data terminal 313. Serial data terminal 313 is serial data line 3
20.

Also, the serial data terminal 313 is connected to the line buffer 36
3t[ is connected to the input terminal of the shift register 311. Serial clock source flag 360 is cleared and set to operate as a slave station. In this state, it receives the serial clock from the master station 300 and performs transmission and reception processing.

The ACK control circuit 365 has a function of outputting a reception confirmation signal onto the serial data line 320 similarly to that of the master station 300, and a function of detecting a reception confirmation signal (L level) input via the serial data line 320. have

The serial data terminal 303 and the serial clock terminal 304 of the first serial data processing device 300 are connected to the serial data terminal 303 and the serial clock terminal 304 of the second serial data processing device 310 via one serial data line 320 and one serial clock line 321, respectively. It is connected to a data terminal 313 and a serial clock terminal 314.

Next, referring to FIG. 2, the first serial data processing device 3
The synchronization relationship between the serial data and the serial clock when 8-bit data is continuously transferred from 00 to the second serial data processing device 310 will be explained. Here, since the first serial data device 300 is a master station,
The serial clock source flag 350 is set in advance by software;
10 is a slave station, so the serial clock pulse flag 360 is cleared in advance by software.

The serial clock line 321 is set to a high level during non-data transfer. Data processing unit 306 transfers transmission data to shift register 301 via internal data bus 305 at timing 10. The serial clock generation circuit 302 starts generating a serial clock at the timing of <1+ and sends the clock onto the serial clock line 321. Furthermore, the shift register 301 performs a 1-bit shift operation in synchronization with the falling edge of the serial clock signal generated by the serial clock generation circuit 302 at the edge t1, and also shifts data for 1 bit in the final stage. It is output onto the serial data line 320 via the serial data terminal 303. Subsequently, the shift register 301 is on the falling edge of the serial clock'! +LS+i7s tis tlls 113s
The shift operation is sequentially repeated in synchronization with each timing of jlfi, and at the same time, one bit of the final stage of the shift register 301 is sequentially sent onto the serial data line 320.

The second serial data processing device 310, which is the receiving side,
In synchronization with the rising edge t2 of the serial clock input from the serial clock line 321 via the serial clock terminal 314, the serial data line 320
The serial data adjusted to one bit above is shifted into the shift register 311 via the serial data terminal 313t-i. Subsequently, the serial receiving device 310 receives the rising edge of the serial clock j4+t6+
j 8 * 110 * j 12 + i 14 s
Serial data line 32 sequentially in synchronization with i ill
The serial data above 0 is shifted into the shift register 311.

When the reception of the 8-bit serial data is completed at the final timing of tis, the data processing unit 316 reads the contents of the shift register 311 via the internal data bus 315, and proceeds to necessary data processing.

The ACK control circuit 365 outputs a low level signal onto the serial data line 320 in synchronization with the timing of the falling edge of the next serial clock at the 9th edge t1γ, and outputs a low level signal to the first serial data processing device on the transmitting side. A reception confirmation signal is issued to the recipient.

A of the first serial data processing device 300 on the transmitting side
The CK control circuit 355 samples the serial data line 320 at the timing of tts of the next rising edge of the serial clock, checks the low level signal which is the reception confirmation signal from the second serial data processing device 310, and Confirm that the byte worth of serial data transfer is completed.

As explained above, after receiving the serial data, the second serial data processing device 310 on the receiving side returns a confirmation signal in synchronization with the falling edge of the clock, and the transmitting side latches this at the rising edge of the next clock. By doing so, confirmation processing can be performed using the data line.

Note that according to this example, when the last data bit is received, t
Next tlr' from 16! clock half period (T100
) it is necessary to output a confirmation signal.

If the serial clock cycle is long enough and the serial data transfer rate is low enough, it is possible for the data processing unit 316 to process data for reception confirmation within this T100 period, but if the serial clock cycle is short enough, As the serial data transfer speed increases, within the T100 period,
Since the process of determining whether or not to output a reception confirmation signal cannot be completed, there is a problem in that the serial clock cannot be increased in speed (that is, data cannot be transferred at a higher baud rate). In particular, the first. When a large number of serial data processing devices are connected to the serial data line 320 and the serial clock line 321 in addition to the second serial data processing device, the period of the serial clock, that is, the transfer rate of serial data is The serial clock is determined according to the serial data processing device with the lowest data processing ability for reception confirmation in the system, so a serial clock with the shortest cycle is used, which is most suitable for serial data processing devices that can perform high-speed serial data transfer. This will reduce the efficiency of serial data transfer.

A second embodiment of the present invention that solves the above problems will be described with reference to FIG.

The first serial data processing device 100 includes shift registers 301 . Serial clock generation circuit 302, serial data terminal 303. Serial clock terminal 304. Internal data bus 305. Data processing unit 3G6. Input line buffer 353° Output line driver 158. Serial clock source flag 350. Serial clock control circuit 151, ACK detection circuit 155. ACK detection flag 157. Clock driver 354. ACK output circuit 35
6. ACK) has a trigger flag 359 and an ACK output driver 378.

Among these, shift register 301. Serial clock generation circuit 302. Serial data terminal 303. Serial clock terminal 304. Internal data bus 305, data processing section 306. The functions of the line buffer 353 and serial clock source flag 350 are the same as those shown in FIG. 1, and detailed explanation will be omitted.

Serial clock control circuit 151 outputs ACK sampling signal 101 to ACK detection circuit 155. The serial clock control circuit 151 activates the ACK sampling signal 101 after receiving data of a predetermined length, and specifies the sampling period of the reception confirmation signal to the ACK detection circuit 155.

The ACK output circuit 356 includes an ACK trigger flag 359, and when a logic "1" is written there via the internal data bus 305 under the control of the data processing unit 306, a reception confirmation signal ( L level)
is output, and the ACK trigger flag 359 itself is cleared again in synchronization with the output of the reception confirmation signal. The ACK output driver 378 is a driver for driving the serial data line 320 to L level, and outputs the ACK trigger flag 35.
Controlled by 9. On the other hand, the ACK detection circuit 155
It includes a detection flag 157, which is set when it is confirmed that a reception confirmation signal has been output on the serial data line 320 under the control of the ACK sample signal 101, and is cleared in synchronization with the start of serial transmission. Also, the contents of this ACK detection flag 157 are the internal data (
It can be read out via the bus 305. The line driver 158 is a driver for driving the serial data line 320 and is controlled by the ACK detection circuit 155.

The second serial data processing device 110 has the same configuration as the first serial data processing device 100, and has shift registers 311. Serial clock generation circuit 312. Serial data terminal 313. Serial clock terminal 314. Internal data bus 315. Data processing unit 316. Line buffer 363. Line driver 168. Serial clock source flag 360. Serial clock control circuit 161.
ACK detection circuit 165. ACK detection flag 167° clock driver 364. ACK output circuit 366 has an ACK trigger flag 369 and an ACK output driver 388.

Among them, shift register 311. Serial clock generation circuit 312. Serial data terminal 313° serial clock terminal 314. Internal data bus 315, data processing section 316. The functions of the line buffer 363 and serial clock source flag 3600 are the same as those in 100 in FIGS. 1 and 3, and detailed description thereof will be omitted.

The serial clock control circuit 161 activates the ACK sampling signal 111 after receiving data of a predetermined length, and specifies the sampling period of the reception confirmation signal to the ACK detection circuit 165. ) ICK output circuit 366 is
It includes an ACK trigger flag 369, and when a logic "1" is written there via the internal data bus 315 under the control of the data processing unit 316, a reception confirmation signal (L level) is output on the serial data line 320, and an ACKI -I
The J-ga flag 369 itself is cleared again in synchronization with the output of the reception confirmation signal. The ACK output driver 388 is a driver for driving the serial data line 320 to L level, and is controlled by the ACK trigger flag 369. A
The CK detection circuit 165 includes an A CK detection flag 167, which is set when it is confirmed that a reception confirmation signal has been output on the serial data line 320 under the control of the ACK sampling signal 111, and is cleared in synchronization with the start of serial transmission. Ru. Furthermore, the contents of this ACK detection flag 167 can be read out via the internal data bus 315.

Line driver 168 connects serial data line 320
This is a driver for driving the ACK detection circuit 165 and is controlled by the ACK detection circuit 165. Note that when both the ACK output drivers 378 and 388 are off, the serial data line 320 is brought to a high level by the line drivers 158 and 168.

Next, referring to FIG. 4(a), the serial data on the serial data line 320 when 8-bit data is continuously transferred from the first serial data processing device 100 to the second serial data processing device 110. The synchronization relationship between the serial clock and the serial clock on the Klein 321 will be explained. The serial clock pulse flag 350 of the first serial data processing unit 100 is set in advance by software, and serves as the serial clock supply source (master station) and also as the second serial data processing unit [110
It is assumed that the serial clock source flag 360 of is cleared in advance by software and set for each side (slave station) to which the serial clock is supplied from the serial clock terminal 315. The serial clock line 321 remains at a high level during non-data transfer.

When the data processing unit 306 transfers the transmission data to the shift register 301 via the internal data bus 305 at a timing of t10G, the ACK detection flag 157 is set to t.
The serial clock generation circuit 302 starts outputting the serial clock from the timing <t+ot, and sends it onto the serial clock line 321. Furthermore, the shift register 301 performs a 1-bit shift operation in synchronization with the falling edge of the serial clock generated by the serial clock control circuit 151 at a shift edge t 101 , and also transfers 1-bit data at the final stage to the line driver 158 . and serial data line 320 via serial data terminal 303
Output on top. Subsequently, the shift register 301 receives the falling edge of the serial clock, teaa l
ttos t '107 * ttos l
The shift operation is repeated in sequence in synchronization with each timing of 1llll * F1m+t 115 , and at the same time, one bit of the final stage of the shift register 301 is sequentially sent onto the serial data line 320 . When the transmission of 8 bits of serial data is completed in synchronization with the timing of t115, the falling edge of the serial clock t1 continues.
In synchronization with timing 17, the ACK detection circuit 155 puts the line driver 158 in a pull-up state.

This causes the serial data line 320 to go to a high level state.

The serial clock control circuit 151 of the first serial data processing device 100 activates the ACK sampling signal 101 in synchronization with the timing of the movement t 117 . The serial clock control circuit 151 continues to output the serial clock, and the ACK detection circuit 155 detects ttts, which is the rising edge of the serial clock.
* In synchronization with each timing of t120, sensing of an L level signal output as a reception confirmation signal from the second serial data processing device 110 on the serial data line 320 is started.

The second serial data processing device 110 receives the rising edge t1 of the serial clock input from the serial clock line 321 via the serial clock terminal 314.
02, serial data corresponding to one bit on the serial data line 320 is shifted into the shift register 311 via the serial data terminal 313. Subsequently, the serial receiving device 110 receives the rising edge of the serial clock, FO4+110g+
jloll + ttto + t112 * Sumire 14
+ Serial cheater line 3 in sync with jllg
The serial data on 20 is shifted into the shift register 311. When the reception of the 8-bit serial data is completed at the timing of the last ttta, the data processing unit 3
16 transfers the contents of the shift register 311 to the internal data bus 3.
15, and proceed to necessary data processing.

When the data processing unit 316 completes the necessary data processing for this received data, it writes X'1'' into the ACK trigger flag 369 via the internal data bus 316 in synchronization with the timing t 20G.

The ACK output circuit 366 controls the ACK output driver 388 for one serial clock in synchronization with the timing <t201, and outputs an L level signal as a reception confirmation signal onto the serial data line 320. At this time, if the data line 320 is pulled up to the power supply via a resistor (not shown), the open drain transistor of the line driver is turned on and the data line 320 is pulled up to the power supply through a resistor (not shown).
20 should be connected to GND.

The ACK detection circuit 155 in the first serial data processing device 100 detects the serial data line 3 at timing t202, which is the rising edge of the serial clock.
20 goes to L level and confirms that a confirmation signal has been output from the serial receiving device 110, the ACK detection flag 157 is set.

The serial clock control circuit 302 stops outputting the serial clock in synchronization with the timing of the subsequent rising edge t 203 of the serial clock, and at the same time, the data processing unit 306 confirms that the ACK detection flag 157 is set. Yop serial data processing device 11
It is determined that all processing related to data reception at 0 has been completed, and the transmission/reception processing of 1 byte of serial data is completed.

Data processing section 3 of first serial data processing device 100
06 transfers the next transmission data to the shift register 301, thereby starting the above-described serial data transmission/reception process again.

Data processing section 3 of first serial data processing device 100
By managing the time of the confirmation signal in step 06, if the confirmation signal is not output from the second serial data processing device 110 even after the predetermined time T2, the second serial data processing device 110 side Upon determining that an abnormal situation has occurred, the first serial data processing device 100 can stop transmitting the remaining serial data. That is, when transferring multiple bytes of data, the data processing unit 316 of the second serial data processing device 110 may be unable to receive the remaining data after receiving several bytes due to an emergency situation caused by a factor other than serial reception processing. If processing is impossible or it becomes necessary to interrupt the continuing reception processing, the first
By suspending the output of the confirmation signal to the serial data processing device 100, the suspension of the serial data transmission process can be notified.

Next, referring to FIG. 4(b), the serial data on the serial data line 320 when 8-bit data is continuously transferred from the second serial data processing device 110 to the first serial data processing device 100. The synchronization relationship between the serial clocks on the serial clock line 321 will be explained. It is assumed that the first serial data processing device 100 operates as a master station, and the second serial data processing device 110 operates as a slave station. The serial clock line 321 maintains a high level during non-transfer.

The serial clock generation circuit 302 of the first serial data processing device 100 starts outputting the serial clock at timing t 301 and sends it onto the serial clock line 321 . The serial clock on the serial clock line 321 is input to the serial molock control circuit 161 via the serial clock terminal 314.

The shift register 311 of the second serial data processing device 110 performs a 1-bit shift operation in synchronization with the 9th edge tzo+ of the serial clock generated by the serial clock control circuit 161. The data corresponding to the number of minutes is outputted onto the serial data line 320 via the line driver 168 and the serial data output terminal 313. Next, shift register 31
1 is 130 when the serial clock falls on the 9th edge.
3+j3G! + j307 + t3o* l '3
1! +F13+'315, the shift operation is repeated in sequence, and at the same time, one bit of the final stage of the shift register 311 is sequentially sent onto the serial data line 320. When the transmission of 8 bits of serial data is completed in synchronization with the timing of t315, the subsequent falling edge of the serial clock is the edge t317.
The ACK detection circuit 165 puts the line driver 168 in a pull-up state in synchronization with the timing. This causes the serial data line 320 to go to a high level state.

The serial clock control circuit 161 of the second serial data processing device 110 activates the ACK sampling signal 111 in synchronization with the timing of movement t3!7.

The serial clock control circuit 151 of the first serial data processing device 100 continues to output the serial clock, and the AC
The K detection circuit 165 detects j318*! which is the rising edge of the serial clock. In synchronization with each timing 3201, sensing of an L level signal output as a reception confirmation signal from the first serial data processing device 100 on the serial data line 320 is started.

The first serial data processing device 100 outputs serial data corresponding to one bit on the serial data line 320 in synchronization with the rising edge t 302 of the serial clock output from the serial clock control device 151. It is shifted into the shift register 301 via the serial data terminal 303. Subsequently, the first serial data processing device 100 receives the rising edge of the serial clock, t304 * t30g + '308.
t t310 + t312! 1314, t31
6, the serial data on the serial data line 320 is sequentially shifted into the shift register 301.

When the reception of the 8-bit serial data is finished at the final timing t 316 , the data processing unit 306 reads the contents of the shift register 301 via the internal data bus 305 and proceeds to necessary data processing. When the data processing unit 306 completes the necessary data processing for this received data, an ACK trigger flag 359 is sent via the internal data bus 306 to the ACK trigger flag 359 in synchronization with the timing t400.
" is written. The ACK output circuit 356 continues < t401
ACK for 1 serial clock in synchronization with the timing of
Controlling output driver 378 to output serial data line 3
A low level signal, which is a reception confirmation signal, is output on 20.

Second serial data processing device 100 side K detection circuit 16
7 is the rising edge of the serial clock t4
When it is confirmed that the serial data line 320 is at the L level at the timing of .degree. 2 and that a confirmation signal has been output from the first serial data processing device 100, the ACK detection 7 lag 167 is set.

The serial clock control circuit 151 performs the following serial clock,
The data processing unit 316 stops the output of the serial clock in synchronization with the timing of the rising edge t403 of the first serial clock, and at the same time, the data processing unit 316 confirms that the ACK detection flag 367 is set. It is determined that all processing related to data reception in the data processing device 100 has been completed, and the transmission/reception processing of 1 byte of serial data is ended.

The first serial data processing device 100 outputs the serial clock to start the above-described serial data transmission/reception process again.

Data processing section 3 of second serial data processing device 110
By managing the time of the confirmation signal in step 16, if the confirmation signal is not issued from the first serial data processing device 100 even after the predetermined time T3, the first serial data processing device 100 side Interpreting that an abnormal situation has occurred, the second serial data processing device 110 can stop transmitting the remaining nine serial data. In other words, when transferring multiple bytes of data, the data processing unit 306 of the first serial data processing device 100 receives several bytes due to an emergency situation caused by factors other than serial reception processing, and after receiving the remaining υ data. If processing becomes impossible and it becomes necessary to interrupt the continuing reception processing,
By suspending output of the confirmation signal to the second serial data processing device 110, interruption of the serial data transmission process can be notified.

〔Effect of the invention〕

As described above, the serial data processing device according to the present invention can confirm data transmission and reception on the transmitting side and the receiving side using two lines, the serial cheater line and the serial clock line.

Furthermore, since the reception confirmation signal can be generated at any timing after receiving the predetermined data, it is possible to speed up the serial clock. Also, 1st. In addition to the second serial data processing device, the serial data line 32
0 and the serial clock line 321, the period of the serial clock, that is, the transfer rate of serial data, is the maximum of the data processing ability for confirmation of reception on the receiving side. There is no need to configure settings to suit low-speed serial data processing devices, and a serial clock with a short cycle that is suitable for serial data processing devices capable of high-speed serial data transfer can be used, maximizing the efficiency of serial data transfer. It is possible to do so. Furthermore, since the confirmation signal output circuit and the confirmation signal detection circuit can be realized with a small amount of hardware, the present invention is very useful as a serial data processing device between LSIs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a serial data transfer device according to an embodiment of the present invention, FIG. 2 is a timing chart of serial data transfer in FIG. 1, and FIG. 3 is a serial data transfer according to another embodiment of the present invention. Block diagram of the device, Figure 4(a)
and (b) are their timing charts. 100.300... Serial transmitter, 110
゜310... Serial receiving device, 301, 31
1...°...Shift register, 302, 312...
...Serial clock generation circuit, 303, 313...
...Serial data terminal, 304, 314...
・・Serial clock terminal, 305.315・・°・・
・Internal data bus, 306.316...Data processing unit, 101, 111...A(, sampling signal, 151.16]°...Serial clock control circuit, 158 ,168°352.362...
・・Line driver, 155, 165・・・・AC
K detection circuit, 157, 167...ACK detection flag, 355.365...ACK control circuit, 3
56.366...°...ACK output circuit, 353,3
63... Line buffer, 378, 388...
...ACK output driver, 359.369...
...ACK trigger flag, 320... Serial cheater line, 321... Serial clock line. Agent Patent Attorney Uchihara St-゛.日゛・7′

Claims (2)

[Claims] (1) In a serial data transfer device in which a master station and a slave station are interconnected by a single data line and a single clock line, the master station and slave station each output a reception confirmation signal on the data line. and reception confirmation signal detection means for detecting the reception confirmation signal on the data line, and executes data transfer confirmation processing in synchronization with a serial clock output on the clock line. A serial data transfer device characterized by: (2) The serial data transfer device according to claim 1, wherein the reception confirmation signal detection means detects the reception confirmation signal within an arbitrarily determined sampling period.