SU1614016A1 - Data input device - Google Patents

Abstract

The invention relates to computing and can be used to input initiative signals in communication devices with an object. The aim of the invention is to expand the field of application of the device due to the programmability of the choice of input channel numbers and the number of consecutive changes in input information. The device contains a control unit 1, a switching unit 2, a multiplexer 3, a block of bus drivers 4, the first element And 5, the second register 6, the second element And 7, the third register 8, the interrupt unit 9, the first 10 and the second 11 elements OR, the first register 12, comparison unit 13, element block AND 14, delay element 15, first 16 and second 17 one-shot, third 18 element AND 18, counter 19, third OR element 20. A positive effect is the possibility of functional diagnostics of the device and continued operation with the device case of failure of part of the scheme. 1 hp f-ly, 2 ill.

Description

The invention relates to computing technology and can be used to input initiative discrete signals in communication devices with an object used in automated process control systems (ACS TP).

The purpose of the invention is to expand the field of application of the device due to the programmability of the choice of input channel numbers and the number of consecutive changes in input information .:

Fig, 1 shows the block diagram of the input device; Fig. 2 is a functional block diagram of the control unit.

The device for entering information contains a control unit 1, a switching unit 2, a multiplexer 3, a bus driver unit 4, the first element AND 5 the second register 6, the second element 7 and the third register 8, the interrupt unit 9, the first 10 and the second 11 elements OR, the first register 12, comparison unit 13, unit 14 elements AND delay element 15, first 16 and second 17 one-shot, third element 1/1 18, counter 19, third element OR 20.

The control unit (Fig. 2) contains the decoder 21, the first 22 and second 23 elements And, the repeater 24, the third element And 25 one-shot 26.

The input device works as follows.

The signal from the Reset line resets the programmable multiplexer 3 register 6, register 8, block 9 interrupts

the counter 20.3 then the computer performs the programming of the multiplexer 3 and register 6 to record the necessary information in them Further operation of the device is determined by the modes specified by the computer by writing information to the register 8 and the counter 19. To write information to the register B and the counter 19 Command Register and Signal Output. At the same time, at the fourth output of the address decoder 21 (FIG. 2), a signal appears, opening element 25 on the first input. To the second input of which an output signal arrives, after which the output of the element 25 acquires a signal to write information to register 8 coming from the output of control block 1 to the clock inputs of register 8 and counter 19. If zero is recorded in register 8, then the change information latching mode is set at the inputs Information from the device inputs is fed to the register 12 inputs through block 14 in accordance with the formula

Yi

where Yi is the 1st bit input signal reg register re

. 5 s

..,

ma i input signal i-ro bit information i i 1 input signal i-ro bit register

 gtr / rb i-bit de register 6 is written O, then it permits the passage of information to the i-th input of register 12. If the input and output information of register 12 do not match, a mismatch signal appears on the output of the 13 10 comparison unit, which triggers the one-shot 16 pulse duration of which corresponds to the duration of the transition process at the input of the device. After the end of operation of the single-15 vibrator 16 with the falling edge of its output signal, the one-shot 17 is triggered. It produces a short pulse producing through the element OR 21 overwriting the information in the register 12. After the re-recording of the 20, the discrepancy signal is removed and the circuit returns to its previous state. Pu / 1cc from the output of the one-shot 17 also goes to the clock input of the counter 19. If counter 19 is preliminarily recorded through a parallel recording, information from a computer about the number of cycles of the circuit after which a request must be issued interrupt, then for each pulse from the single-oscillator 17, the contents of the counter 19 will decrease by one. When it becomes zero, the next pulse will be a signal at the output of the transfer of counter 19, which will cause the ready signals to be set and (if there is a pre-junction interrupt from the JBM) an interrupt request, which is transmitted to one of the LINE COMPUTER INTERFACE. The enable interrupt is done by writing. 0 information from one computer data bus line to interrupt unit 9. For this, the computer provides the device with information on the corresponding data line, the address of the command register, the output signal. The recording of the interrupt enable 5 is made by the write signal to the output register of the control unit 1. The readiness signal can be read by the computer through the 4 bus driver unit. For reading information about the readiness of the computer, the device gives the device the address of the status register, the signal. In this case, the signals from the output of the address decoder 21 and from the output of the repeater 24 cause the output signal 23 to appear at the output of the output signal control block 1 to the input of the block 4 bus formers and opens for the transfer bus formers, through which the RM f ° state is transmitted to, the readiness is reset through

the element OR 10 according to the general reset signal or reading the information of the output register 12c of the control unit 1. To read information from the register 12, the computer outputs the address of the data register (the Input signal), and the output of the address decoder 21 (Fig. 2) is a signal arriving at the input of the bus driver unit and opening them. The bus drivers for the data from block 4 are switched on by transmitting the input signal to the input of the block 4 bus drivers. In addition, a signal appears on the output of address decoder 21, opening programmable multiplexer 3 through the input, and a signal from the output of repeater 24 produces switching of programmable multiplexer 3 through the input to read information. Depending on the value of the information at the lower bits of the address supplied to the inputs of the programmable multiplexer 3, it outputs to the block 4 bus drivers for transmitting to the computer one or another part of information from the register 12. When reading information in the data register in the control unit 1 at the output of the element And 27, a signal is generated, which is fed from the output of the control unit 1 to the element OR 10 to reset the readiness. The readiness signal from the output of interrupt unit 9 is fed to the reset input of counter 19 through the element OR 11, blocking its operation in all subsequent pulses of the one-shot 17. This prevents further counting, which would result in the appearance of zero, 14, and t .d (if it is four-fold). The presence at the reset input of the counter 19 of the signal blocking the account does not prohibit the occurrence of a signal at the counter transfer output for each pulse arriving at its clock input. Thus, if all zeros are recorded in the counter 19, then for each change in the input information of the device, a readiness setting and interrupt request pulse will be sent to the input of the interrupt unit 9.

In order to prohibit the latching mode of data on changes in the input information of the computer, it is necessary to record 1 into the first register bit 8, the input of which receives a signal from one of the data bus lines through the 4-bus driver unit, and the clock input-recording signal from the control unit 1 . The signal from the first output of the register 8 blocks the one-shot 16 to the R-input. If in the second digit of the register 8 is recorded zero, then it prohibits the passage of the sync signal from one of the information inputs of the device to the second input of the one-vibrator 17 through the element E 18.

In this mode, data fixation in register 12 can be performed only by a signal from a computer. When issuing a latching signal by one of the data bus lines, it is fed to the first input of the element 7, and the enable signal to write to the command register from the output of control unit 1 to the second input of the element 7, the output of which through the element OR 20 goes to clock input register 12 and produces a commit data. If a unit 8 is recorded in the second digit of register 8, the signal from its output allows passing through an AND 18 clock signal from one of the information inputs of the device to the one-shot 17 input, which for each clock signal will pulse through the OR 20 element to the clock input of the register 12. The mismatch signal from the output of the comparison unit 1 is fed through element I 5 to the input of the block 4 bus drivers, through which it can be read by the computer along with the readiness information (in this case, the enabling signal to the second input element 5 A and is output from the control unit 1). If the scheme operates incorrectly in the commit mode, the input information changes due to the failure of one of its computer elements in this way can receive information about it and issue a data commit command via element 7. If after this the mismatch signal remains and the information in the register does not change, then register 12 is faulty and the i-device is down. If the information in register 12 is changed, and the "Compair" signal is saved, then the comparison unit 13 is faulty and you can continue to work in the latching mode by a computer command. If the information in register 12 is changed and the mismatch signal is removed, then a write pulse shaping circuit is faulty (delay element 15 — single-oscillator 16 — single-oscillator 17 — element OR 20). Thus, reading this computer signal enables the program to perform functional diagnostics of the device during operation and continue working with the device in the event of a part of the circuit failure.

Claims (2)

Claim 1. An information input device comprising a control unit, the first group of inputs of which are device address inputs, and the first and second inputs are respectively input and output devices of the device, the fourth and fifth outputs of the control unit are connected to the third and fourth inputs respectively the bus driver unit, the first group of information outputs of which is a group of information outputs of the device, the output is connected to the fifth input of the interrupt unit, the first and second outputs of which are Dineny respectively with the sixth and seventh inputs of the bus driver unit, the third output of the interrupt unit is connected to the control input of the switching unit, the first group of outputs of which is the output of the device interrupt, and the second group of outputs is connected to the second group of inputs of the control unit whose eighth output is connected to the third the input of the interrupt unit, the second input of which is the device reset input of the comparison unit, the first group of inputs of which is connected to the outputs of the first register, the information inputs of which connected to the second group of inputs of the comparator unit, the output of which is connected to the input of the delay element, the output of which is connected to the first input of the first one-shot, the second one-shot the first, second and third elements AND, that, in order to expand the field of application due to the programmable selection of input channel numbers and the number of consecutive changes in input information, the second and third registers are entered into the device, the first, second and third elements of the ILI counter, the block of elements And, the first the input group of which is the information inputs of the device, the second group of inputs is connected to the outputs of the second register, and the outputs are connected to information inputs of the first register, the outputs of which are connected to the input group of the multiplexer, whose output group is connected to the group of input-output blocks of the I bus driver, the information-: inputs of the second register and the counter whose overflow output is connected to the first input of the interrupt unit, the control input of the counter is connected to the clock input of the third register a, the second input of the second element And the eighth output of the control unit, the first to the third outputs of which are connected respectively to the third to fifth inputs of the multiplexer, the first and second inputs of which are connected respectively to the first and second inputs of the second register and to the corresponding address inputs of the device, and the sixth input is connected to the reset inputs of the interrupt unit, the second register, the third register information inputs of which are connected to the corresponding inputs-outputs of the bus driver unit, the first output q third register coupled to a second input of the first monostable multivibrator, the output koto l 5 but The first input is connected to the second output L of the third register, the output of the second one-shot is connected to the clock input of the counter and the second input of the third element OR is connected to the first input of the first register, and the first input is connected to the 1U output of the second element I, the first input of which is connected to the corresponding input-output of the bus driver unit, the first input of which is connected to the first input of the bl control, the sixth and fifth seventh outputs of which are connected respectively to the fourth and fifth inputs of the first register, the fifth output of the control unit is connected to the first input of the first element And, the second input of which is connected to the output of the comparison unit, and the output to the fifth the input of the bus driver unit, the seventh input of which is connected to the first input of the second element OR whose output is connected to the reset input of the counter, and the second input to the second input of the interrupt unit and the second input of the first OR element whose output is connected to The Fourth interrupt input unit, and the first. input from nine to one output of the control unit, 2. The device according to claim 1, wherein the control unit contains a decoder, two groups of inputs of which are the first and second groups of address- J5 inputs of the unit, the first output of the decoder is connected to the first output of the block and the first input of the first element And whose output is connected to the ninth output of the block, and the second input to the second input of the second 40 element I, the third output of the block and the output of the repeater, whose input is connected to the first input of the block, the second output of the decoder connected to the fourth output of the control unit, the seventh the stroke of which 5 is connected to the third output of the decoder and the first input of the second element And the output of which is connected to the fifth output of the control unit, the sixth output of which is connected to the second input of the fourth element And and. one-shot output, the input of which is connected to the second input of the control unit and the second input of the third element I. the first input of which is connected to the fourth output of the decoder, and the output to the eighth 5th output of the control unit, the second output of which is connected to the output of the fourth element I, the first input of which is connected to the corresponding input of the first group of address inputs of the decoder Figg