KR950002316B1 - Data transmission device for fax - Google Patents

Abstract

The circuit for transmitting an image data read from an image input board to a central control board in a G4 facsimile, includes a first processor board (26), a second processor board (27) and a data transmitter (6). The transmitter (6) includes an AND gate (16) for receiving a DMA starting signal from the board (20), a 2nd D flip-flop (14) for outputting a data request signal (DREQ), a 1st OR gate (15), a 2nd OR gate (17), a 1st inverter (18) for inverting an adress enable (AEN) signal from the board (27), an OR gate (19), a 1st D flip-flop (13) for outputting a memory data request signal (MDREQ), a latch (11), a buffer (12), a 2nd inverter (21), OR gates (20,22,25,24) and a 3rd D flip-flop (23) for outputting an interrupt request signal (IRQ).

Description

Board-to-board data transfer device using 1 byte latch

1 is a block diagram of the present invention.

2 is a timing diagram of the present invention.

3 is a detailed configuration diagram of a data transmission unit.

* Explanation of symbols for main parts of the drawings

1, 7 CPU 2, 8 ROM

3, 9 RAM 4, 10 DMA controller

5 input / output unit 6 data transmission unit

11: latch 12: buffer

13, 14, 23: D flip-flop 15, 17, 19, 20, 22, 24, 25: OR gate

16: end gate 18, 21: inverter

26, 27: processor board

The present invention relates to a board-to-board data transfer apparatus using a one-byte latch that transfers image data read from an image input unit board to a central control unit board in a group 4 facsimile apparatus.

In the conventional data transfer method, a memory sharing address is provided between two boards or data is transferred using dual port RAM. In order to speed up data transfer, direct memory access (hereinafter, referred to as DMA) is used. I'm using.

However, this transfer method is not only complicated in circuit, but also uses block transfer DMA, so it can't do anything else during DMA operation. In 4 facsimile and other devices, the drive pulse of the motor should be given uniformly so as not to affect vibration, image quality, etc In the case of transmitting a lot of data by block transmission, the driving pulse to the motor is not uniform, which causes problems in vibration and image quality.

In order to solve the above problems, the present invention simplifies the circuit for data transfer between boards by using a 1 byte latch, and enables to perform other tasks at the same time during DMA. The purpose is to provide a transmission device.

In order to achieve the above object, the present invention provides a board-to-board data transfer apparatus using a one-byte latch comprising a first processor board, a second processor board and a data transfer unit; The first processor board receives an AND gate having a DMA start signal as one input terminal, an output value multiplied by the AND gate as a clock terminal, and a D input terminal is connected to a power supply, and a data request signal DREQ is output to the output terminal Q. A first OR gate for inputting a second D flip-flop, a chip select signal (/ PCS) to one input terminal, and a write (/ WR) signal as a type force and sending an output to the second D flip-flop; A second OR gate for inputting the output of the OR signal to the type force terminal of the AND gate from the second processor board as a data response signal (/ DACK) as one input and the type force terminal as an input / output read (/ IOR) signal; A first inverter for inverting an address enable (AEN) signal from the second processor board, an output of the first inverter as one input, and an output of the second OR gate as an input to a type force terminal A first D flip-to-OR for inputting an OR gate and an output of the second OR gate, and receiving an output of the first OR gate as a clock terminal and outputting a memory data request signal MDREQ to an output terminal Q; A flop, a latch for inputting an output from the first processor board to a D input terminal and an output from the first OR gate to a clock terminal, and an output from an output terminal Q of the latch as an input. A buffer configured to receive an output of a 3 OR gate and receive an input from the second processor board, and to direct an operation; a second inverter to invert an address signal A0 from the first processor board; A fourth OR gate which uses a chip select signal (/ PCS) from one processor board as one input and a logic OR by inputting the output of the second inverter to the type force stage; A fifth OR gate configured to logically combine the output of the fourth OR gate as one input and a write (/ WR) signal from the first processor board as a type force, and a chip select signal (/ CS) from the second processor board ) Is the one input, and the sixth OR gate for performing logical OR using the address signal A0 from the second processor board as a type force, and the output of the sixth OR gate as one input, is input from the second processor board. A seventh OR gate that is logically ORed using an input / output read (/ IOR) signal as a type force, and an output of the seventh OR gate is input to a clock terminal, and an output of the fifth OR gate is input to interrupt the output terminal Q. And a third D flip-flop for generating the request signal IRQ.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of the present invention, 1, 7 is a CPU, 2, 8 is a ROM, 3, 9 is a RAM, 4, 10 is a DMA controller, 5 is an input / output unit, 6 Denotes a data transfer section, and 26 and 27 denote processor boards, respectively.

As shown in the figure, a CPU 1 for controlling the entire data transmission and reception, a ROM 2 and a RAM connected to the CPU 1 by a data bus and having a program for executing the CPU 1 are embedded therein. A processor board 26 having an input / output unit 5 for adding a DMA controller 4 to a board composed of (3) and transmitting a DMA start signal to the data transfer unit 6, a CPU 7, A processor board 27 configured to perform the same function as the processor board 26 by the ROM 8, the RAM 9, and the DMA controller 10, and data of the processor board 26 and the processor 27. It consists of a data transmission part 6 for transmission.

Referring to the operation having the above configuration, when it is determined that the data generated from the processor board 26 is a predetermined amount or more, the input / output unit 5 sends a DMA start signal to the data transfer unit 6. The data transfer section 6 receives this DMA start signal and generates a data request signal to the DMA controller 4 of the processor board 26. Upon receipt of this signal, the DMA controller 4 sends data in the RAM 3 of the processor board 26 to the data transfer unit 6 by one byte to generate a data response signal (/ DACK). The data transfer unit 6 generates a memory data request (MDRQ) signal for taking data to the DMA controller 10 of the processor board 27 when the data response (/ DACK) signal is received. Upon receipt of this signal, the DMA controller 10 generates a memory data response (/ MDACK) signal while bringing 1 byte of data in the data transfer section 6. When one byte of data is transferred from the processor board 26 to the processor board 27, the data transmitter 6 transmits the next byte of data to the DMA controller of the processor board 26. 4) generate a data request (DREQ) signal; As described above, when the set number of bytes is transferred from the processor board 26 to the processor board 27, the DMA controller 4 of the processor board 26 generates an interrupt to the CPU 1. When an interrupt occurs, the interrupt routine sets the DMA start signal low so no more data is transferred.

2 is a timing diagram of the present invention, (A) is a DMA interrupt timing diagram, (B) is a DMA start signal timing diagram, (C) a data request signal timing diagram, (D) a data recognition signal timing diagram, ( E) denotes a memory data request signal, and (F) denotes a memory data response signal timing diagram, respectively.

3 is a detailed configuration diagram of the data transmission unit 6 according to the present invention, in which 11 is a latch, 12 is a buffer, 13, 14, 23 is a D flip-flop, 15, 17, 19, 20, 22, 24, 25 denotes an OR gate, 16 denotes an AND gate, and 18 and 21 denote an inverter.

As shown in the figure, the processor board 26 receives the AND gate 16 having the DMA start signal as one input terminal, and the output value multiplied by the AND gate 16 as the clock stage, and the D input terminal is connected to a power supply. As the output terminal Q, the D flip-flop 14 for generating the data request signal DREQ and the chip select signal / PCS are input to one input terminal, and the write (/ WR) signal is used as a type force. OR gate 15 to the D flip-flop 14 and the data response signal (/ DACK) from the processor board 27 as a single input and the input signal terminal is a logical sum of the input and output (/ IOR) signal OR gate 17 for inputting the output of the AND gate 16 to the type force terminal of the AND gate 16, an inverter 18 for inverting an address enable (AEN) signal from the processor board 27, and the inverter 18. The output of the OR gate 17 is used as the one input and the type force stage. OR gate 19 to be ORed with the input as the input, and the output of the OR gate 17 as the input, and the output of the OR gate 15 as the clock terminal, and receives the memory data request signal MDREQ to the output terminal Q. D flip-flop (13) outputting the D flip-flop (11) to receive the output from the processor board 26 to the D input terminal and the output from the OR gate 15 to the clock terminal And to input an output from the output terminal Q of the D flip-flop 11, receive an output of the OR gate 19, and receive an input from the processor board 27 to determine an operation direction. The buffer 12, the inverter 21 for inverting the address signal A0 from the processor board 26, and the chip select signal / PCS are input as inputs, OR gate 20 for ORing the output as an input, and the OR OR gate 22 which uses the output of byte 20 as one input and logically writes the write (/ WR) signal from the processor board 26 as a type force, and the chip select signal from the processor board 27. OR gate 25 for performing logical OR with (/ CS) as one input and address signal A0 from the processor board 27 as a type force, and the output of the OR gate 25 as one input. OR gate 24 for ORing with the input / output read (/ IOR) signal from the processor board 27 as a type force, and the output of the OR gate 24 being input to the clock terminal, and the output of the OR gate 22. Is configured as a D flip-flop 23 which outputs an interrupt request signal IRQ to the output terminal Q as an input.

Referring to the operation of the data transfer unit 6 having the above configuration, when the DMA start signal is input high from the processor board 26, the output of the AND gate 16 becomes high. When the output of the AND gate 16 changes from low to high, the output data request signal DREQ of the D flip-flop 14 also changes from low to high. When the data request signal is transmitted to the DMA controller 4 of the processor board 26, the DMA controller 4 takes one byte of data from the RAM 3 and transfers the latch 11 to the DMA controller. When the data is transmitted to (4), the output of the OR gate 15 goes low while writing data to the latch 11 in one byte of the DMA controller 4 so that the output data request of the D flip-flop 14 (DREQ) To bring the signal low. When the DMA operation of the DMA controller 4 is completed, the output of the OR gate 15 is changed from low to high. At this time, one byte of data transmitted from the processor board 26 is stored in the latch 11 and At the same time, the output memory data request (MDRQ) signal of the D flip-flop 13 is changed from low to high so that the data transfer unit 6 sends a DMA request signal to the DMA controller 10 of the processor board 27. .

When the DMA controller 10 receives the memory data request (MDRQ) signal, the DMA controller 10 reads one byte of data stored in the latch 11 and stores the data in the RAM 9. If the output of the AND gate 16 goes low while the DMA controller 10 reads the data, the D flip-flop 13 is reset and the output memory data request MDRQ goes low. When the DMA controller 10 finishes reading 1 byte of data into the DMA, the output of the AND gate 16 goes from low to high again, and an output data request signal (DREQ) of the D flip-flop 14 is received. Going low in row requires the next one byte of data transfer. By repeating the above operation, data on the processor board 26 is transmitted to the processor board 27, and when the data amount reaches a preset amount, the DMA controller 4 generates an interrupt to the CPU 1 This informs the end of data transfer. When the interrupt signal is input, the CPU 1 sets the DMA start signal low to block the transmission of the next byte. The processor board 26 sends an interrupt request signal IRQ to the processor board 27 to notify the completion of the transfer when the predetermined amount of data transfer is completed. When the processor board 27 recognizes the interrupt, the output of the D flip-flop 23 is made low.

Therefore, by using the data transfer unit 6 operating as described above, not only the data can be transferred by a simple circuit but also other simple operations can be performed between the DMA operations. The effect of solving the problem can be obtained.

Claims (1)

In a board-to-board data transfer apparatus using a 1-byte latch composed of a first processor board 26, a second processor board 27, and a data transfer unit 6, the first processor board 26 receives a DMA start signal. A second D for inputting an AND gate 16 serving as an input terminal and an output value logically multiplied by the AND gate 16 as a clock terminal, the D input terminal being connected to a power supply, and outputting a data request signal DREQ to the output terminal Q. A first OR gate that inputs a flip-flop 14 and a chip select signal (/ PCS) to one input terminal and sends an output to the second D flip-flop 14 with a write (/ WR) signal as a type force (15) and the data response signal (/ DACK) from the second processor board 27 as one input, and the type-power stage is an input / output read (/ IOR) signal to output the output of the logical sum of the AND gate 16. From the second OR gate 17 and the second processor board 27 to input the type force stage The first inverter 18 which inverts the address enable (AEN) signal, the output of the first inverter 18 as one input, and the output of the second OR gate 17 as the input to the type force stage, the logic sum. The OR gate 19 and the output of the second OR gate 17 are input, and the output of the first OR gate 15 is input to the clock terminal, and the memory data request signal MDREQ is output to the output terminal Q. A first D flip-flop 13 for outputting a first output, a latch for receiving an output from the first processor board 26 to a D input terminal and an output from the first OR gate 15 to a clock terminal ( 11) and an output from the output terminal Q of the latch 11 as an input and an output of the third OR gate 19 and an input from the second processor board 27 to receive an input direction. From the first processor board 26 and the buffer 12 The second inverter 21 which inverts the response signal A0 and the chip select signal / PCS from the first processor board 26 are input as inputs, and the output of the second inverter 21 is input to the type force stage. The fourth OR gate 20 to be ORed as an input and the output of the fourth OR gate 20 are one input, and the write (/ WR) signal from the first processor board 26 is used as a type force. The fifth OR gate 22 to be ORed together with the chip select signal / CS from the second processor board 27 as one input, and the address signal A0 from the second processor board 27 is inputted. A sixth OR gate 25 that is logically summed as an input and an output of the sixth OR gate 25 are one input, and an input / output read (/ IOR) signal from the second processor board 27 is used as a type force. Receiving the OR of the seventh OR gate 24 and the output of the seventh OR gate 24 to the clock terminal And a third D flip-flop 23 for outputting the interrupt request signal IRQ to the output terminal Q as an output of the fifth OR gate 22 as an input. Data transmission device.