KR930011348B1 - Interface circuit between scsi and decoder ic - Google Patents

Abstract

The circuit comprises a gate for gating CPUS1 signal for making HRD port of IC memory as initial step after usual and last byte transfer, invertered signal of DDRQ port to transfer DMA determine level of HRD port of decoder IC by passing input signals of SDRQ and DACK port through the gate to transfer DMA transfer of SCSI IC, and a pulse width generating part for providing active time of SCSI IC and DACK by output of DDRQ port of decoder IC, and active time of SCSI IC. The circuit provides accurate data transfer without data loss.

Description

Interface circuit between decoder IC and SCSI IC

1 is an embodiment of an interface circuit between a decoder IC and a SCSI IC according to the present invention.

2 is an operational waveform diagram of each part in FIG.

* Explanation of symbols for main parts of the drawings

10: Decoder IC (LS8951) 20: SCSI IC (KS53C80)

30: gate portion 40: pulse width generation portion (74LS123)

G1: Oagate G2, G3, G4: Endgate

1n: Inverter CPUS1, CPUS2: CPU control signal

The present invention relates to an interface circuit between a decoder IC and a small computer system interface (SCSI) IC. More specifically, the present invention provides a direct memory access (DMA) transfer of data such as a CD-ROM. The present invention relates to an interface circuit between a decoder IC and a SCSI IC for accurate transmission.

In general, in the case of reading and transferring data in memory by operating a program by a microcomputer, since the main clock of the microcomputer is used, the processing speed of the data is reduced. The DMA transfer method is to solve this problem.

On the other hand, inside the computer, when a CD-ROM processor transfers data to a personal computer at high speed, a CD-ROM processor, an interface circuit, a DMA processor, an auxiliary circuit, and a DMA card are required.

Here, the auxiliary circuit is a circuit that operates by assisting the DMA processor to perform DMA transfer, and the DMA card is a kind of adapter for applying the DMA transferred data to the personal computer. There is also a standardized integrated device that contains both the functionality of a DMA processor and an auxiliary circuit, which is a SCSI IC. The SCSI IC will be described later.

This DMA transfer allows data to be transferred at high speed by means of a predetermined control signal regardless of the clock signal of the microcomputer. When data is DMA transferred between the CD-ROM decoder IC and SCSI IC for data transfer, several control signals for DMA transfer of data are transferred by the handshake method. The time required for the interchange of signals is in tens of nanoseconds (nS).

Therefore, if an error occurs in the control time between the control signals exchanged with each other, the data is corrupted or lost, so that the accurate transmission of the data is not performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to control the mutual control signals so that the control time between the signals is accurately controlled when DMA transfers data between the decoder IC and the SCSI IC of the CD-ROM. The present invention provides an interface circuit between a decoder IC and a SCSI IC that facilitates exchange so that DMA transfer of data is performed accurately so that there is no corruption or loss of data.

A feature of the interface circuit between the decoder IC and the SCSI IC according to the present invention for achieving the above object is an interface circuit circuit for performing DMA transfer between the decoder IC and the SCSI IC; After the HRD stage (/ HRD), which is the signal stage for the decoder IC to read the data picked up from the memory, is activated, the DRCK stage of the SCSI IC, which is the signal stage for transferring data between the decoder IC and the SCSI IC to the main computer ( / DACK) is to have the logic to be active.

Hereinafter, one preferred embodiment of the interface circuit between the decoder IC and the SCSI IC according to the present invention will be described in detail with reference to the accompanying drawings.

1 is an embodiment of an interface circuit between a decoder IC and a SCSI IC according to the present invention, and FIG. 2 is an operation waveform diagram of each part in FIG.

First, the IC IC LC8951 is applied to the decoder IC according to the embodiment of the present invention and the IC name KS53C80 is applied to the SCSI IC. Here, the reason for using the SCSI IC is that, when using a general DMA processor, an adapter installed between the personal computer and the DMA processor in the latter stage, that is, the number of CD-ROM drives required for the DMA card, is used in the latter case. This is because the adapter installed between the personal computer and the SCSI IC, that is, the SCSI IC card, can be used by connecting up to eight CD-ROM drives with one card.

In the HRD stage (/ HRD), which is the host lead signal terminal of the decoder IC 10, the HRD stage (/ HRD) is normally maintained at logic HH, and the logic byte H at the last byte after data transfer is made. The CPUS1 signal, which is the control signal of the CPU for giving, the signal of the DDRQ stage DRQ1, which is the DMA request stage of the decoder IC 10, and the signal of the SDRQ (DRQ2), which is the DMA request stage of the SCSI IC 20, are inputted. The gate part 30 is connected so that it may be.

은 SCSI IC(20)의 DMA 어크날리지단인 DACK단(/DACK)에 연결되고 또한 앤드게이트(G4)를 통해 SCSI IC(20)의 IOW단(/IOW)에 연결되었다. 상기 펄스폭 발생부(40)는 일예로 IC명 74LS123을 적용할 수 있으며, 출력단(

의 펄스폭을 결정하는 저항(R1)과 콘덴서(C1)로 구성된 시정수 회로를 구비하였다.On the other hand, a pulse width generator 40 for inputting the output of the DDRQ stage DRQ1 of the decoder IC 10 is provided, and the output terminal of the pulse width generator 40 (

Is connected to the DACK stage (/ DACK) which is the DMA acknowledgment stage of the SCSI IC 20, and is connected to the IOW stage (/ IOW) of the SCSI IC 20 through the AND gate G4. The pulse width generator 40 may apply the IC name 74LS123 as an example, and the output terminal (

A time constant circuit composed of a resistor (R1) and a capacitor (C1) for determining the pulse width of the circuit was provided.

의 출력을 양입력으로 하는 앤드게이트(G3)와, 데코더 IC(10)의 DDRQ단(DRQ1)의 출력을 반전하는 인버터(In)와, 상기 앤드게이트(G3)와 인버터(In)의 출력을 입력으로하는 앤드게이트(G2)와, 상기 앤드게이트(G2)와 CPU의 CPUS1 신호를 입력으로 하는 오아게이트(G1)의 접속으로 이루어졌다.On the other hand, the gate portion 30 is the output of the SDRQ stage (DRQ2) of the SCSI IC 20 and the output terminal of the pulse width generator 40 (

The output of the AND gate (G3) and the inverter (In) which inverts the output of the DDRQ stage (DRQ1) of the decoder IC 10, the output of the AND gate (G3) and the inverter (In). An AND gate G2 serving as an input and an OR gate G1 serving as the input of the AND gate G2 and the CPUS1 signal of the CPU were formed.

This embodiment of the present invention is such that the DACK stage (/ DACK) of the SCSI IC 20 is activated after the HRD stage (HRD) is activated (low active) in order to read data by pickup. The detailed operation of the present invention and its effect will be described based on the operation waveform of FIG. First, the CPU generates a start signal for setting a handshake between the decoder IC 10 and the SCSI IC 20 to operate an internal register of the SCSI IC 20. That is, the control signal is generated so that the SDRQ stage DRQ2 becomes the logic 'H' and the CPUS1 signal is made the logic 'L'. After that, the DDRQ stage DRQ1 of the decoder IC 10 becomes a logic ＂H＂ to start data transfer.

은 로직 ＂L＂로 되고, 상기 펄스폭 발생부(40)의 출력이 SCSI IC(20)의 DACK단(/DACK)에 입력되어 DACK단(/DACK)이 엑티브되며, 앤드게이트(G4)를 통해서 IOW단(/IOW)에는 로직 ＂L＂이 인가되어 엑티브되게 된다.As the DDRQ stage DRQ1 of the decoder IC 10 becomes the logic ＂H 입력, the input of the pulse width generator 40 becomes the logic＂ H ＂, so the output stage (

Becomes the logic ＂L＂, and the output of the pulse width generator 40 is input to the DACK terminal (/ DACK) of the SCSI IC 20 so that the DACK terminal (/ DACK) is activated, and the AND gate G4 is turned on. Through this, the logic 'L' is applied to the IOW stage (/ IOW) to be activated.

On the other hand, since the DDRQ stage DRQ1 of the decoder IC 10 is logic 반전 H ＂, it is inverted and input to the logic＂ L 에 of the AND gate G2 of the gate part 30 through the inverter In. As a result, the output of the AND gate G2 becomes logic ＂L 게이트 and is applied to the OR gate G1, so that the HRD terminal (/ HRD) of the decoder IC 20 becomes logic＂ L ＂and 1 in the decoder IC 10. Read bytes of data.

This data is transferred to the SCSI IC 20 when both the DACK stage (/ DACK) and the IOW stage (/ IOW) of the above-described SCSI IC 20 become logic VL. In Fig. 2, the section A is in such a state, that is, the data between the decoder IC 10 and the SCSI IC 20 is transferred to the data bus between the SCSI IC 20 and the main computer (not shown). It shows the interval. Then, the ACK terminal (/ ACK) of the SCSI IC 20 is transferred to the logic ＂L＂ to transfer data on the bus between the decoder IC 10 and the SCSI IC 20 on the bus between the internal adapters of the main computer. Become active. The data transferred on the bus between the SCSI IC 20 and the internal adapter of the main computer is transferred to the main memory of the main computer when the REQ stage (/ REQ) of the SCSI IC 20 is activated by logic ＂L＂, thereby transferring 1 byte. Minute data transfer is complete.

On the other hand, if one byte of data is read out from the decoder IC 10 and data is transferred on the bus between the SCSI ICs 20 before data is completely transferred to the main computer, the data transfer error occurs. There is a problem that the first data is lost or the data is corrupted. This problem can be prevented by making the REQ stage (/ REQ) of the SCSI IC 20 active before the ACK stage (/ ACK). . In the internal logic configuration of the SCSI IC 20, the REQ stage (/ REQ) turns to logic ＂H＂ after the ACK stage (/ ACK) turns to logic ＂L＂, and this REQ stage (/ REQ) turns to logic ＂H＂. Data transmission is performed in the section B until the completion, and the transmission of one byte is completed.

은 최초에 SCSI IC(20)의 DACK단(/DACK)을 엑티브시키기 위해 로직 ＂L＂을 유지한 후 다시 로직 ＂H＂로 반전 복귀되어 SDRQ단(DRQ2)이 로직 ＂H＂일때 데코더 IC(10)의 HRD단(/HRD)이 로직 ＂H＂로 된다.Thereafter, the SDRQ stage DRQ2 becomes a logic HH by the internal circuit configuration of the SCSI IC 20 so that data on the bus between the decoder IC 10 and the SCSI IC 20 can be changed. Accordingly, since the DDRQ stage DRQ1 is logic ＂H＂, logic is applied to the HRD stage (/ HRD) of the decoder IC 10 through the AND gates G3, G2 and OA gate G1 of the gate unit 30. ＂H＂ will be applied. Here, the output terminal of the pulse width generator 40 which provides the other input of the AND gate G3 (

In order to activate the DACK stage (/ DACK) of the SCSI IC 20 first, the logic IC maintains the logic L and then inverts the logic to H. The decoder IC (DQ2) is the logic IC. The HRD stage (/ HRD) of 10) becomes logic ＂H＂.

In this manner, after one-byte data is transferred to the main computer, the data is ready for the next one-byte data transfer. Since the HRD stage (/ HRD) has become logic ＂H＂, the DDRQ stage (DRQ1) of the decoder IC 10 becomes logic H, and DMA transfer is performed again, and the inverted DDRQ stage ( The signal of DRQ1) is gated to activate the HRD stage (HRD) again with logic 'L'. Therefore, the same operation as that of the above-described one-byte data transfer is performed, so that a new one-byte data transfer is performed.

When the repetitive circuit operation is performed and one block of data (usually 2048 bytes) is transferred, the HRD stage (/ HRD) of the decoder IC 10 is maintained at logic HH and the CPUS1 signal of the CPU The logic goes to " H " to terminate DMA transfer of one block. When this DMA transfer is not carried out, the DACK stage (/ DACK) of the decoder IC 20 becomes a logic HH, so the IOW stage (/ IOW) stage is determined by the CPUS2 signal of the CPU. In this case, the SCSI IC ( 20) to control the internal register.

In this way, the signal level of the HRD terminal (/ HRD) of the decoder IC 10 is determined by the gate unit 30 and the CPUS1 signal, and the pulse width generating unit 40 determines the DACK terminal of the SCSI IC 20 ( / DACK) and the signal level of the IOW stage (/ IOW) is determined, the signal of the HRD stage (/ HRD) to read data from the decoder IC (10), and the data between the decoder IC (10) and the SCSI IC (20) The condition of the DACK terminal (/ DACK) signal for transmitting to the main computer, that is, the condition that the DACK terminal (/ DACK) is activated after the HRD terminal (/ HRD) is activated.

As described above, according to the interface circuit between the decoder IC and the SCSI IC according to the present invention, the data on the bus between the decoder IC and the SCSI IC is hosted after the signal at the HRD stage, which is a signal for reading the data of the decoder IC, is activated. Since the DACK signal, which is a signal to be transmitted to the computer, is activated in a logic structure, when the data picked up from the memory is transferred to the DMA, accurate data transfer is performed without data loss or alteration. Has the effect of being done.

Claims (2)

An interface circuit for performing DMA transfer between a decoder IC and a SCSI IC; Logic that enables the DRCK stage of the SCSI IC, the signal stage for transferring data between the decoder IC and the SCSI IC, to the main computer after the HRD stage, the signal stage for the decoder IC to read the data picked up from the memory, is activated. An interface circuit between a decoder IC and a SCSI IC. 2. The logic of claim 1, wherein the logic is further configured to execute a CPUS1 signal for making the HRD stage of the decoder IC into an initial stage after the normal and last byte transfer, the inverter signal of the DDRQ stage for DMA transfer, and the DMA transfer of the SCSI IC. A gate unit for gating and outputting input signals of the SDRQ stage and the DACK stage to determine the level of the HRD stage of the decoder IC; Interface circuit between the decoder IC and the SCSI IC, which is composed of a pulse width generator which provides the active period of the DACK stage of the SCSI IC by the output of the DDRQ stage of the decoder IC and at the same time provides the active period of the SCSI IC.

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