JPS61253555A - Transaction analyzer - Google Patents

Abstract

PURPOSE:To attain application of a transaction analyzer to various microprocessors without changing the hardware by setting a logic circuit in a programmable state. CONSTITUTION:A transaction analyzer contains a random access memory (logic circuit) 88 and a state machine 80 having a state register 94. The address of the memory 88 is controlled by a control line selected from a microprocessor and the data stored in a state register. The present output state of the machine 80 including the state of the fetch control signal is decided from the contents of the register 94. The contents of the register 94 are controlled by the data stored previously in the memory 88. Therefore the transaction analyzer can be easily programmed by loading previously the proper data to the memory 88.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention monitors the control lines of a computer processor to control the data acquisition by a logic analyzer, particularly the logic analyzer. Transaction analyzer that determines the format of the transaction and generates the appropriate signal.

[Prior Art and Problems] The typical function of a logic analyzer, which is a data acquisition device, is to monitor the address path, data bus, and control lines from the pins of a microprocessor chip; The purpose of the present invention is to display on the screen a history of microprocessor operations, including the status of the address bus and data path lines. Typically, a logic analyzer accesses the address, data, and control lines of a system-under-test microprocessor through a probe inserted between the microprocessor and its socket. The probe typically consists of a set of probe pins that match the pinout of the microprocessor and a probe socket into which the microprocessor can be inserted.

The probe's internal wiring connects the microprocessor pins inserted into the probe socket to the appropriate probe pins inserted into the motherboard.

This allows address, data and control lines to be routed to buffers, which transfer the data to the logic analyzer's circuitry.

Typically, the data acquisition portion of a logic analyzer processes each microprocessor's transactions (tr
transaction: a read or write cycle, or an interrupt, etc.) is stored in a random capture memory, where the data represents a series of transactions that are stored sequentially at a series of addresses. Because the state of the microprocessor's data and address buses is only valid during a transaction cycle, a transaction analyzer is provided to monitor selected control lines of the microprocessor to determine when a valid transaction has occurred, and to determine when a write strobe has occurred. Signals are provided to the capture memory to store current data on the microprocessor's data, address and control lines.

In the prior art, most data acquisition portions of logic analyzers, including processors, transaction analyzers, and other devices, were designed for use with only one type of microprocessor. Because different microprocessors require different pin outs, different types of control lines, different types of transactions, and different timing, a different data acquisition device was required for each type of microprocessor under test. Retarget tab/l/ (retargeta
ble) A probe has been proposed whose pin and socket parts can be exchanged to accommodate different types of microprocessors. cross connection
-connect) circuits are also interchangeable and can route control, data and address lines to the rest of the capture device so that they can be applied in the same general arrangement regardless of the type of microprocessor under test.

[Object of the invention] Therefore, the object of the present invention is to use such a probe to
An object of the present invention is to provide a transaction analyzer that can be applied to many different types of microprocessors without changing the hardware and that can control the fetching operation of a fetching memory at high speed.

SUMMARY OF THE INVENTION In accordance with the present invention, a transaction analyzer is capable of identifying many signal state patterns appearing on a selected set of microprocessor control lines accessed by a logic analyzer probe. It has a logic device. Upon identifying any one of the signal state patterns representative of a transaction occurring within the microprocessor, the transaction analyzer generates a clock signal. This clock signal causes the logic analyzer to begin capturing data occurring at the microprocessor's terminals into the capture memory. The transaction analyzer can be programmed to identify control line patterns that occur during transaction generation by different microprocessors. Thus, it can be used with retargetable probes to access data appearing on pins of a variety of different microprocessors.

Also in accordance with the invention, the transaction analyzer includes a state machine having a random access memory (logic circuit) and a state register. Selected control lines from the microprocessor and data stored in status registers control the addressing of the random access memory. The current output state of the state machine, including the state of the acquisition control clock signal, is determined by the contents of the state register. This content is then controlled by data previously stored in random access memory. Thus, the transaction analyzer can be easily programmed by preloading the random access memory with appropriate data.

Further, in accordance with the present invention, the state machine is asynchronous and performs random access operations based on changes in the state of control lines, without depending on a clock signal from the microprocessor.
Accumulates the current output data of the memory in the status register.

This allows the transaction analyzer to provide a timing interface between data acquisition devices and various different microprocessors without changing the timing interface hardware.

Additionally, in accordance with the present invention, the transaction analyzer generates a "transaction tag" consisting of binary coded data representing the type of transaction to be executed by the microprocessor.

The logic analyzer can capture and store this transaction tag in place of data obtained directly from the selected control line, allowing transaction data to be stored more compactly.

Further, in the present invention, the generated transaction tag is
Since it is generally independent of the type of microprocessor, the software used to access the data captured for different microprocessors can be standardized.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a logic analyzer incorporating the present invention. Data capture device 10 captures data, addresses, and a series of states of selected control line outputs of a microprocessor operating within device under test 14 and stores them in random access capture memory 12 . The apparatus 10 includes a probe 16 that connects data lines from pins of the microprocessor under test through internal buffers and interconnect wiring.
The address line and selected control line portions are connected to data latch 18, address latch 20, and control latch 22, respectively. The probe 16 also connects other selected control lines from the microprocessor pins to the transaction analyzer 2 via line 34.
Connect to the input terminal of 6. This probe 16 can be "retargeted" to a different microprocessor by replacing the pins and sockets inserted between the microprocessor and the socket of the device under test 14 and changing the interconnect wiring.

Transaction analyzer 26 provides appropriate latch control signals to latches 18.20 and 22 via control output lines 28.30 and 32 at appropriate times depending on the state of selected control line data on line 34. This controls the storage of data, address and control information from probe 16 in latches 18, 20 and 22. The interconnect wiring of probe 16 allows the appropriate microprocessor control signals to appear on line 34 so that transaction analyzer 26
can determine the type and stage of microprocessor transactions that are occurring. latch 18.20
and 22 are transferred from these latches to the data input terminals of acquisition memory 12 via data bus 36, address bus 38, and control bus 40, respectively.

Transaction analyzer 26 determines device under test 14 from the state of selected control line data on line 34.
Upon determining the type of transaction, such as a read or write operation, that the microprocessor is performing, transaction analyzer 26 generates a binary encoded tag signal on bus 42 representative of the type of transaction. This bus 42 connects the acquisition memory 12
and to the input of the acquisition state machine 46. Transaction analyzer 26 also generates a clock signal that causes latches 18, 20 and 22 to store new data from probe 16. This clock signal is on line 4
8 to the input of the acquisition state machine 48.

Acquisition state machine 46 transfers a write signal to the write control input of acquisition memory 12 via line 50, increments the current address of memory 12 by one, and writes the current address to lines 36, 38 and 38. 4
The data storage operation of the capture memory 12 is controlled so that data of 0 is stored. When the current memory address passes the maximum number and is further incremented, this address ie resets to the minimum number and writes the current data over the previously stored data at this address in memory.

Acquisition state machine 46 also generates and transfers qualifying bits to memory 12 via line 52. In order to ensure that the series of data stored in memory 12 includes gathers, each time a clock signal from transaction analyzer 26 is received, a state
Capture state machine 46 may be programmed such that machine 46 does not generate a write signal.

Here, data representing one or more consecutive microprocessor transactions was not stored in memory 12. Lines 36, 38, 40 and 4 when a gather occurs in the data accumulation immediately before accumulating the current data.
The qualifier bit is set and stored with the current data of 2.

Word recognizer 54 can be programmed to detect line 5 when a particular pattern of data or address bits occurs on lines 36, 38 or 40.
The state machine 46 receives the instruction signal through the state machine 46.
Transfer to. programming the capture state machine 46 to begin generating write signals upon receipt of a selected instruction signal from the word recognizer 54 or upon receipt of a selected tag signal from the transaction analyzer 26; Or it can be stopped.

Additionally, the acquisition state machine 46 can be programmed to use control lines 60 to set and initiate the operation of the counter and timer 58. When the counters and timers reach predetermined limits, the appropriate limit signals are captured and transferred to state machine 46 via line 62. The state machine 46 then uses this limit information to start or stop the write signal. For example, it may be desirable to stop saving data in acquisition memory 12 for 100 microprocessor transactions after the selected address appears on line 38.

In this case, one word line is activated to recognize the selected address on line 38 and provide an indication signal to state machine 46 when this selected address appears.
Program the recognizer 54. Also, line 60
One counter 58 is programmed to generate a limit signal on line 62 after detecting 100 pulses of . When the state machine 46 receives the instruction signal,
Each time a clock pulse is received, the transfer of count pulses over line 60 is initiated. Also, state machine 4
6 detects the limit signal on line 62, and the memory 12
Since the write signal is supplied to , data storage is completed.

In addition to generating write signals through selected logic combinations of tag signals, clock signals, limit signals, and word recognizer 56 indication signals, acquisition state machine 46 also generates one or more signals on lines 63 from device under test 14 . It is programmed to generate a write signal depending on the state of an external input. These inputs may be digital signals representing the status of various events occurring within the device under test 14, such as push buttons or relay operations. This feature allows the capture device 10 to capture data that occurs within a selected number of cycles before or after the external event occurs in the memory 10.
It can be stored in 2.

The data acquisition device 10 further includes an I10 (input/output) memory map 68 which registers the data lines of the microprocessor under test when a selected address is accessed during a read operation. Output the selected data.

Therefore, the I10 memory map 68 is
It may also be used to simulate a keyboard or other input device that does not exist in the computer. A data bus from the device under test 14 is connected to a bidirectional buffer in the probe 16 so that the data bus from the device under test 14 is connected to the device under test 1 through the buffer in the probe 16.
Data from the I10 memory map 68 may be passed from the I10 memory map 68 through the probe buffer to the data bus of the device under test 14 in the reverse direction. Good too. Signals from transaction analyzer 26 via control line 72 based on the type of microprocessor transaction occurring control the direction sensing of the bidirectional buffer within probe 16.

Before starting data capture, the word recognizer 54, state machine 46 and transaction
All of analyzer 26 may be programmed by program controller 64.

The program controller 64 may comprise a microprocessor system having control lines, address lines, and data lines coupled to each of the controlled blocks.

Transaction analyzer 26 is a programmable logic device capable of performing the functions described below.

In the preferred embodiment, transaction analyzer 26 includes an asynchronous state machine 80 as shown in the block diagram of FIG.

It is equipped with The operation of this type of asynchronous state machine is disclosed in US Patent Application No. 730,920, filed May 6, 1985.

The state machine 80 shown in the block diagram of FIG.
A selected new machine state (Sn+1) in response to a change in input state l during the current machine state (Sn)
Changes to Therefore, Sn+1 is a function of I and Sn, ie, Sn+1 = f (S n , I ).

The current machine state Sn is state machine “80”.
is a binary number stored in machine state register 82 of Sn, where each bit of Sn represents a binary machine state variable. Each bit of status register 82 is connected to status register output bus 84.
appears in a separate line. Similarly, the input state I is also 2
A base number, each bit of which represents the state of an independent control line on input bus 34 from probe 16.

The signals on both output bus 84 and input bus 34 are provided as inputs to combinational logic circuit 88.

This combinational logic circuit @SS may be any programmable device capable of generating the appropriate S n + 1 output derived from Sn and ■. However, in the preferred embodiment, combinational logic circuit 88 comprises random access memory (RAM). Then, Sn and I are supplied to address this RAM. Also, when any possible combination of Sn and I addresses this RAM, the data output bus 90 of the combinational logic circuit 88
Sn+1 is composed of data stored in the RAM so that an appropriate Sn+1 appears in the .

Combinatorial logic circuit 88 generates machine state variables S n
In addition to + 1, by the function On + 1 = g (S n , I),
An output variable On+1 is also generated. Each On+1 is stored in the same RAM storage location as its corresponding Sn+1 and appears on output data bus 92 at the same time that Sn+1 appears on data bus 90.

Data bus 90 is connected to the input gate terminal of status register 82 so that when the clock terminal of status register 82 is strobed by a transition pulse, the contents of data bus 90, Sn+1, become Sn+1 on the trailing edge of such pulse.
It is stored in the status register 82 as . Therefore, the state of state machine 80 advances by one step. Similarly, data bus 92 is connected to the input gate terminal of output status register 94, so that when the clock terminal of this register 94 is strobed by a change pulse, the contents of data bus 92, On+1, are set as On to the output status register. Accumulated. Tag signal line 42, clock signal line 48, latch control lines 28, 30 and 32 of FIG.
Alternatively, the direction control lines 72 can be arranged as desired to form each bit stored in the output status register 94 on a separate register output line along with grouped output lines.

The change pulse is generated by an asynchronous timing circuit 96.

This timing circuit 96 monitors the input state I of the state machine 80 appearing on the bus 34 and supplied to the input terminal of the timing circuit 96, and outputs a change pulse after an appropriate delay time after detecting a change in . Occurs and advances the state of the state machine. This time delay is necessary to some extent to allow combinational logic circuit 88 sufficient time to generate a new Sn+1 output in response to a 1 change. The access cycle time of logic circuit 88 is D2
Indicated by

A time delay associated with timing circuit 96 is also required to ensure that the change in ■ is completed before strobing registers 82 and 94. State machine 80 is a multi-input changing state machine, in which several binary variables of ■ may change over a period of time denoted Dl, and still require "simultaneous input" to determine the next state of the state machine. ” shall be treated as having occurred. Therefore, ■
After detecting the first change in any variable of , timing circuit 96 operates for at least a period of time t = D 1 before generating a change pulse to advance the state of the state machine.
+D You have to wait 2.

In this application, the minimum waiting time D1 required to ensure that the change in ■ is completed may vary depending on the current state Sn of the state machine, and for different microprocessor transactions, the first and last There are various delay times between control line changes. According to the present invention, the multi-input change waiting time of the timing circuit 96 is not constant but variable and changes the current state Sn.

Therefore, the combinational logic circuit 88 of FIG.
A binary output variable T is also generated from bus 98 to register 99. When the change pulse is received from the timing circuit 96, the T variable of is clocked into the register 99 and supplied to the timing circuit 96. The delay time t=D1+D2 is changed depending on the current state Sn of the state machine using a variable T which is a function of Sn.
Any change in causes the combinational logic circuit 88 to change T appropriately so that the delay time D1 sets the minimum required time for proper operation in the current state. Thus, it is possible to advance from each machine state to the next possible state at the fastest possible speed.

Furthermore, state machine 80 allows the sequence of machine states Sn and output states On to follow a single input I state change. The sequential output feature of asynchronous state machine embodiment 80 allows transaction analyzer 26 to determine the sequence of operations, e.g.
First, it can be controlled as a sequence consisting of latch control and tag signal generation. Note that these signals are transmitted to the latch 18.
20 and 22 to store the current probe output.

To obtain a series of output characteristics, logic circuit 88:
a single-bit state variable SE that is a function of the current state Sn
Generate Q. When the sequence variable bit is logic 1, this indicates that the current state Sn is part of a sequence and other states of this sequence will continue even without a change in input state I. When the sequence variable is logic 0, this indicates that the current state Sn is not part of the sequence, or is the final state of a sequence of states, and will not continue until the input state I changes. .

This sequence variable is applied to the J and input terminals of the JK flip-flop 100. This flip flop 1
00 is clocked by a change pulse from timing circuit 96. If the sequence variable is a logic 1, then on the trailing edge of the transition pulse the output of flip flop 100 changes state. If the sequence variable is a logic O, the output of flip-flop 100 will not change state upon receiving a change pulse. The timing circuit 9 uses the output of the flip-flop 100 shown as Off as another input.
Supply to 6.

When input I changes state, timing circuit 96 detects this state change and then generates a change pulse to advance the state Sn of the state machine. If this state is the first of the sequence, the sequence state variable generated by logic circuit 88 is a logic one. Thus, the falling edge of the state pulse applied to flip-flop 100 causes the output of flip-flop 100 to change state. Utilizing the falling edge of the change pulse ensures that status register 82 stores a new Sn before flip-flop 100 is turned off and that asynchronous timing circuit 96 is ready to receive the output of flip-flop 100. Can be done. Timing circuit 96 detects this change in the flip-flop output Off state and generates the next change pulse, thus advancing the sequence of Sn states to the second state.

The state machine continues to advance through the state sequence and sets the sequence variable to logic 0 until it reaches the final state sn of the sequence. If this logic 0 is applied to the J input of flip-flop 100, the output state of flip-flop 100 will not change on the trailing edge of the transition pulse.

Therefore, timing circuit 96 does not detect a change in the Off input, and state machine 80 remains dormant until it detects a change in input state I.

FIG. 3 is a block diagram of an embodiment of the asynchronous timing circuit 96 of FIG. 2, which is comprised of a change detection circuit 104 and a variable time delay circuit 106. Change detection circuit 10
4 detects any change in the input state I or the output state Off of flip-flop 100 and generates a logic 1 (high) output signal DIFF on line 108 coupled to the input of delay circuit 106. The change detection circuit 104 maintains the DIFF input from the change detection circuit 104, regardless of any next change of ■ or Off, until the delay circuit 106 receives the generated high change signal. After a selected delay time after the signal goes high, delay circuit 1
The change signal, which is the output signal of 06, switches high. When the change signal goes high, the DIFF output of change detection circuit 104 is reset to logic 0 (low), causing change detection circuit 10
4 remains low until it detects the next change in I or Off.

When the DIFF signal returns to 0, the change signal of the delay circuit 106 immediately becomes 0. Therefore, the change pulse generated by the delay circuit 106 is relatively narrow, and its width is determined by the reset time of the change detection circuit 104 when receiving the leading edge of the change pulse and the delay circuit 106 when receiving the trailing edge of the DIFF signal. Determined by glue setting time. In the prior art, a topology similar to that shown in FIG. 3 was used, but because the delay circuit 106 delayed both the leading and trailing edges of the DIFF signal by the same fixed delay time, the state machine Response time has increased. In this embodiment, delay circuit 106 delays only the leading edge of the DIFF signal and not the trailing edge. Additionally, as discussed above, the leading edge delay time is variable depending on the state of the timing input variable T generated by the combinational logic circuit 88 and transferred to the delay circuit 106.

The delay of the leading edge of the DIFF signal is such that the leading edge of the transition pulse occurs at a time t=D1+D2=D3+D4 after the leading edge of the DIFF signal.

Note that Dl is the time when the input I changes as described above, and D2
is also the cycle time of the combinational logic circuit 88 described above, D3 is the variable delay of the delay circuit 106, and D4 is the fixed pulse width of the changing pulse.

Since time D3 is suitably controlled by a time variable T provided by logic circuit 88 and D4 is fixed, time t is the minimum time for each machine state Sn.

FIG. 4 is a block diagram of an embodiment of the change detection circuit 104, including the j+1 bit latch circuit 110 and the G1ψGj
j+1 sets of exclusive OR (XOR) gates 11 denoted by +1
2 and an or gate 114. The variable j is
is the number of binary state variables forming input state ■. Each input variable Ix is supplied to a corresponding input terminal Ax of the latch circuit 110 and one input terminal of a corresponding XOR gate Gx.

Similarly, Cf from flip-flop 100 of FIG.
The f variable is connected to the Aj+1 input terminal of the latch circuit 110 and the XOR
Gj+1. Each output Bx of the latch circuit 110 is
All outputs of XOR gate 112 are connected to respective inputs of OR gate 114. Delay circuit 106
A change signal from the latch circuit 110 controls the clock input of the latch circuit 110.

The latch circuit 110 transfers the input signal to the output when the clock is high and fixes the output signal when the clock is low. Therefore, when the change signal goes low, the final states of ■ and Off will be stored in the latch circuit, and these final states will remain at the output B until the leading edge of the other change signal reaches the clock input.
It appears in x.

When any Ix or Off changes, the corresponding XO
Since the inputs of the R gates are different, the outputs of the XOR gates switch to logic 1 and the DIFF signal, which is the output of OR gate 114, goes high. When the leading edge of the change signal reaches the clock edge of latch circuit 110, Ix and Off
transfer the current state of the latch circuit to the output terminal of the latch circuit, and transfer the current state of
2 inputs, so both inputs of all XOR gates are equal. This switches the output of all XOR gates to 0, so OR gate 114
The DIFF output also returns to 0. Thus, delay circuit 106 drives the change signal low, thus ending the input detection cycle and beginning a machine state change. After that, ■ or Of
Any subsequent change in f initiates another detection cycle.

FIG. 5 is a block diagram of an embodiment of the delay circuit 106 of FIG. It is equipped with A DIFF signal is provided to the reset input (R) of shift register 116 and a logic 1 is provided to the data input (D). Oscillator 120 clocks shift register 116 .

The output of shift register 116, designated B1ψBi, is connected to the corresponding input A1ψAi of multiplexer 118. Additionally, the DIFF signal is provided to the enable input (EN) of multiplexer 118 and the T variable from logic circuit 88 of FIG. 2 is provided to the switching control input (SEL) of multiplexer 118.

Upon receiving the leading edge of the DIFF signal, shift register 11
All outputs Bx of 8 are reset to 0. Thus, on each clock cycle from oscillator 120, shift register 116 shifts the logic 1 provided at the data input to successive outputs Bx, so that the first clock cycle after reset causes B1 to go high. , the second clock cycle after reset causes B2 to go high, and the Xth clock cycle after reset causes B2 to go high.
x becomes high. When the DIFF signal applied to the enable terminal of shift register 116 is low, the change signal, output B of multiplexer 118, is always low. D.I.
When the FF signal goes high, output B of multiplexer 118 is connected to one selected input Ax. In addition,
This selection is controlled by a variable T applied to the selection control input.

In the preferred embodiment, oscillator 120 operates at 100 MH2. Thus, successive output Bx of shift register 116 goes high every 10 nanoseconds. Multiplexer 1
18 is a variable T such that the appropriate x output of shift register 116 is passed across the output of multiplexer 118.
The variable delay time D3 of the delay circuit 106 is set by adjusting Je.

When the number of stages i of the shift register 116 is 16, the delay time D3 changes from lθ nanoseconds to 160 nanoseconds in steps of 10 nanoseconds. By changing the number of stages i of shift register 116 and adjusting the oscillator 12(1) frequency, the range and resolution of B3 can be changed.

Upon receiving the leading edge of the DIFF pulse, shift register 1
All 16 outputs are set to O and multiplexer 118 is enabled. Successive output Bx of shift register 116 goes high on each cycle of oscillator 120. Selected Ax from shift register 116
goes high, the transition output of multiplexer 118 goes high after a selected time D3. Next, this change output signal causes the change detection circuit 104 in FIG. 3 to change the DIFF signal to 0.
Reset to . Since the DIFF signal goes to O, shift register 106 is cleared and multiplexer 118
Since the enable input of multiplexer 11 becomes 0,
The change output signal of 8 is reset to 0 to complete the change detection cycle and initiate a machine state change.

Only those combinations of selected control signals on lines 34 from probe 16 that represent logical microprocessor transactions cause a transaction to occur such that a clock signal, I10 direction control signal, tag signal, or latch control signal changes state. Data may be loaded into the random access memory of the combinational logic circuit 88 of FIG. 2 so that a change in the state of the analyzer occurs. Thus, transaction analyzer 26 is programmable and can load different data into the RAM of logic circuit 88 depending on the type of microprocessor under test. Therefore, as mentioned above, using programmable transaction analyzer 26
Most preferably with the use of retargetable probe 16, the selected control signal can be varied to appear on line 34 regardless of the type of microprocessor associated with device under test 14.

However, the tag signals generated by the transaction analyzer can be standardized to the extent that these tag signals represent the same type of transaction for all microprocessors. Additionally, when standardized in this manner, the tag signals generated by transaction analyzer 26 may cause data stored in memory 12 to be stored in memory 12 such that acquisition memory 12 can store data related to the type of transaction in a more compressed form. It is possible to increase the degree of standardization of software that uses This is because no software is required to examine the type of microprocessor under test to determine the type of transaction to be executed.

Transaction analyzer 26 indicates I on line 72.
Capable of generating 10-way signals, such a transaction analyzer can utilize the I10 memory map 68 described above, and when used in conjunction with probe 16 having a bidirectional data buffer, can simulate an input device into device 14. You can

To take advantage of the asynchronous timing of the transaction analyzer 26 without changing the timing hardware as is sometimes required when utilizing a transaction analyzer having an asynchronous state machine clocked by a clock signal received from the device under test. allows you to program the transaction analyzer for different microprocessors under test.

[Effects of the Invention] As described above, according to the present invention, since the logic circuit is programmable, a transaction analyzer can be applied to a basic microprocessor without changing the hardware. Further, the timing circuit operates asynchronously, and the delay time from detecting a change in input data to generating a change signal changes optimally depending on the current state, so high-speed operation is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the transaction analyzer and data acquisition device of the present invention, FIG. 2 is a block diagram of the transaction analyzer used in FIG. 1, FIG. 3 is a block diagram of the timing circuit used in FIG. Figure 4 is a circuit diagram of the change detection circuit used in Figure 3, and Figure 5 is a circuit diagram of the change detection circuit used in Figure 3.
FIG. 3 is a circuit diagram of a delay circuit used in the figure. In the figure, 10 is a data acquisition device, 26 is a transaction analyzer, 82 and 94 are registers, and 8
8 is a logic circuit, and 96 is a timing circuit.

Claims (1)

[Scope of Claim] A transaction analyzer used with a data capture device that captures input data, comprising: a register that accumulates current state data representing a current state; and a register that stores current state data that represents the current state, and the current state data accumulated in the register and the input data or the input. a programmable logic circuit that generates next state data representing a next state in response to data associated with the data, and generates delay time control data in response to at least the current state data; and a timing circuit that generates a change signal after a delay time corresponding to the delay time control data from the logic circuit has elapsed after detection, and the register receives the next state data from the logic circuit in response to the change signal from the timing circuit. A transaction analyzer that stores current state data and controls the fetching operation of the data fetching device according to the current state data.