JP2692469B2 - Data controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data control device for controlling peripheral devices by a CPU.

[0002]

2. Description of the Related Art A conventional data controller, as shown in FIG. 7, is a series of pre-programmed control data,
CPU 1 for generating arithmetic control signals and input / output control signals
, A data bus 2, an arithmetic unit 3, a general-purpose register 4 for holding an arithmetic result, and control registers 5a, 5b for coupling the CPU 1 and peripheral devices 7a, 7b, 7c via an input / output control signal via the data bus. , 5c and a status register 6. In such a data control device, the CPU
Inputting / outputting 1 data is performed in parallel for a plurality of data. For example, 1 byte of control data is set in parallel in the peripheral device 7a via the control register 5a. On the other hand, when setting the control data in bit units, the control register 5
After transferring the contents of b to the general-purpose register 4, the arithmetic unit 3 performs a logical operation to set or reset a predetermined bit and transfer it to the control register 5b again.

[0003]

In such a conventional example, since the control register is read and written via the data bus when controlling the bit-by-bit peripheral device, the control is performed in comparison with the byte-by-byte control. There is a drawback that the processing time becomes long. In addition, a normal bit-unit process requires a few instructions for reading, computing, and writing, which has a drawback of consuming a large amount of program memory.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a data control device having means for performing control in bit units at high speed.

[0005]

According to the present invention, there is provided a CPU for generating a series of preprogrammed control data and input / output control signals, and a data bus for transmitting a plurality of bits of control data in parallel according to the program. In a data control device comprising a control register for coupling a CPU and a controlled device via this data bus according to an input / output control signal, the control register is a set signal and a clock among the input / output control signals. A first AND gate to which a signal is applied to the input terminal, a second AND gate to which a reset signal and a clock signal of the input / output control signals are applied to the input terminal, and 1 bit of control data is applied to the input terminal. A first clocked inverter controlled by the output signals of the first AND gate and the second AND gate, and the first clocked inverter An output terminal of the inverter is connected to an input terminal, and an output terminal is an output terminal of the control register related to the 1 bit, and an output terminal of the inverter is connected to an input terminal. A second clocked inverter, which is controlled by the output signal of the AND gate and has an output end connected to the input end of the inverter, is provided for each bit of control data.

[0006]

The byte-wise writing to the control register is performed by setting the input / output control signal C to "1" while the control data is output to the data bus, and the bit-wise setting to the control register is performed by the data bus. It is performed when the input / output control signal S is set to "1" while "1" is output to the corresponding bit.
Resetting in bit units is performed by setting the input / output control signal R to "1" while "0" is output to the corresponding bit of the data bus.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. The CPU 1 is pre-programmed to control the peripheral devices 7a, 7b, 7c and sends a series of control data via the data bus 2 to the peripheral devices 7a, 7b,
7c. The peripheral device 7a is controlled by inputting control signals in byte units. The peripheral device 7b is controlled by inputting a plurality of control signals in bit units. The peripheral device 7c receives a control signal in byte units, and
The status data read by the CPU 1 is output. CPU
The control data output by 1 is held in bit units in the control register 5b selected by the input / output control signal and transmitted to the peripheral device 7b.

FIG. 2 is a block diagram of the control register 5b. The data bus 2 has terminals D0, D1, D2,
It is connected to D3 and input to the wiring logic circuit 8, respectively.
The flip-flop 9 holds a control signal for each bit, and terminals Q0, Q1, Q2 and Q3 are connected to the peripheral device 7b. The output of the flip-flop 9 is input to the data of the flip-flop 9 after being logically operated with the bit of the data bus.

FIG. 3 is a logic circuit diagram of the 1-bit portion of the control register 5b. Outputs of the clocked inverters 11 and 12 each having the CMOS structure shown in FIG. The inverter 13 and the clocked inverter 12 form a flip-flop, which holds the control signal and outputs it to the terminal Q. The input / output control signal output from the CPU 1 is input to the terminals C, S and R of the AND gate 14 and the NAND gate 15.

That is, this embodiment is shown in FIGS.
As shown in FIG. 1, a CPU 1 that generates a series of preprogrammed control data and input / output control signals, a data bus 2 that transmits a plurality of bits of control data in parallel according to the program, and an input / output control signal CP
The control registers 5a, 5b and 5c are provided to connect U1 and the controlled device via the data bus 2. Further, the control registers 5a, 5b and 5 are provided as a feature of the present invention.
Each of c is inputted with an AND gate 14 which is a first AND gate to which the set signal and the clock signal of the input / output control signals are applied to the input terminals, and the reset signal and the clock signal of the input / output control signals. A NAND gate 15 which is a second AND gate applied to the end, a clocked inverter 12 to which one bit of control data is applied to the input end and which is controlled by the output signals of the AND gate 14 and the NAND gate 15, and the clocked inverter 12 The output terminal of the inverter 13 is connected to the input terminal, the output terminal of which is the output terminal of the control registers 5a, 5b, 5c related to the 1 bit, and the output terminal of the inverter 13 is connected to the input terminal of the AND gate. 14 and Nand Gate 15
And the clocked inverter 12 whose output end is connected to the input end of the inverter 13 for each bit.

Next, the operation of this embodiment will be described. FIG.
Shows a truth table of the logic circuit of FIG. Control register 5a
Writing in byte units is performed by setting the input / output control signal C to "1" while the control data is output to the data bus 2. The bit-wise setting to the control register 7b is performed by setting the input / output control signal S to "1" while "1" is output to the bit of the data bus 2, and the bit-wise resetting is performed by the data bus. The input / output control signal R is set to "1" while "0" is output to the relevant bit of
Is done by. FIG. 6 is a circuit diagram of an input / output unit for a data bus of the data control device according to the second embodiment of the present invention. The difference from the first embodiment is that the data bus 2 performs a wired operation between the data held in the control register and the CPU output data. The clocked buffer 20 and the inverter 21 are the data bus output circuits of the CPU 1, the clocked buffer 22 and the inverter 23 are the data bus output circuits of the control registers 5a, 5b, 5c,
The flip-flop 24 is a control register 5a, 5b, 5c.
It is. In this embodiment, the control registers 7a, 7b and 7c are
There is an advantage that the stored data of 1 can be read from the CPU 1 as needed.

[0012]

As described above, the present invention provides a CPU.
Since a register having a wiring logic circuit of the held data and the data bus can be used as the peripheral device control register of, the data can be set in the control register bit by bit without reading the control register via the data bus. The peripheral device can be controlled bit by bit in a short time, and the reading means of the control register and the arithmetic circuit for bit arithmetic are unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a control register included in FIG.

FIG. 3 is a circuit connection diagram showing a configuration of a 1-bit portion of the control register shown in FIG.

FIG. 4 is a circuit connection diagram showing the configuration of the clocked inverter included in FIG.

5 is a truth table showing the operation of the control register included in FIG. 1. FIG.

FIG. 6 is a circuit connection diagram showing a configuration of an input / output circuit for a data bus.

FIG. 7 is a block configuration diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 CPU 2 Data Bus 3 Arithmetic Unit 4 General-purpose Register 5a, 5b, 5c Control Register 6 Status Register 7a, 7b, 7c Peripheral Device 8 Wiring Logic Circuit 9, 24 Flip-Flop 11, 12 Clocked Inverter 13, 21, 23 Inverter 14 AND gate 15 NAND gate 20, 22 Clocked buffer

Claims (1)

(57) [Claims] 1. A CPU for generating a series of pre-programmed control data and input / output control signals, a data bus for transmitting control data of a plurality of bits in parallel according to the program, and a CPU for input / output control signals. In a data control device comprising a CPU and a control register for coupling a controlled device via this data bus, the control register is provided with a set signal and a clock signal of input / output control signals at its input end. A first AND gate; a second AND gate to which a reset signal and a clock signal of the input / output control signals are applied to the input terminal; and 1 bit of control data to the input terminal, The first clocked inverter controlled by the output signal of the second AND gate and the output terminal of the first clocked inverter are An inverter that is connected to the output terminal and whose output terminal is the output terminal of the control register relating to the 1 bit, and the output terminal of this inverter is connected to the input terminal, and the output of the first and gate and the second and gate A data control device comprising: a second clocked inverter, which is controlled by a signal and whose output end is connected to the input end of the inverter, corresponding to each bit of control data for 1 byte.