SU1594552A1 - Device for controlling data exchange between control processor and peripheral - Google Patents

Abstract

The invention relates to computing and is intended to control the exchange of information in computing systems that can be used to control technological processes, automatic lines, robotic complexes. The aim of the invention is speed improvement and simplification. The device contains a control unit, a decoder, a multiplexer, a bus driver. 1 hp f-ly, 2 ill.

Description

The invention relates to computing and is intended to control the exchange of information in computing systems that can be used to control technological processes, automatic lines, robotic complexes.

The aim of the invention is to improve speed and simplify the device.

FIG. a block diagram of the interface device is presented; Fig. 2 is a block diagram of an exchange control unit.

The device contains (figure 1) the input-outputs 1 of the address data, the control inputs-outputs 2, the control unit 3, the decoder 4, the multiplexer 5, the bus driver 6, the inputs and outputs 7-10.

The exchange control unit 3 (Fig. 2) contains one-shot and J2, elements AND 13-17, block trigger 18, module trigger 19, elements OR 20-21, and a bus driver 22.

The interface device operates as follows.

The exchange of information between the processor (not shown) and external devices, which can be input-output blocks (not shown),. occurs in asynchronous mode. The information exchange cycle starts with the address being entered.

The processor outputs the Signal Address (VA) signal and the Input-Output (BB) signal, indicating that information is being exchanged between the processor and the input-output blocks, and to the input-output 1. address data is given

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pei-H (ie. word that is fed to the input of the multiplexer 5.

The signal VA is fed to the input element AND 16 of the control unit 3, and the signal BB is supplied to the other input. The output signal of the element And 16 removes the blocking of the first 11, second 12 one-shot, trigger block 18 and trigger module 19.JQ

The launch of the first 11 one-shot is carried out by the synchronization signal (CB), which accompanies the address word provided by the control processor. 15

At the direct output of the first 11 single-vibrator, a pulse appears, which with its leading edge sets the trigger 18 of the block to state 1. The signal from the direct output of the trigger 18 of the block goes to the inputs of the element OR 20, element 13 and the first: the input of multiplexer 5, on the group of inputs of which there is already an important word.

According to the signal, the block number multiplexer 5 selects from the address word from the sixth to ninth bits corresponding to the number of the selected

processor and the selected I / O unit. Thereafter, a receive synchronization signal (SP) is generated in the selected I / O unit, which is fed to the input of block trigger 18 and returns it to its original state. In this case, blocking is removed from multiplexer 5, AND 13 is blocked, the block number signal is removed, and hence the SP signal. The choice of block I / O made.

The signal from the inverted output of the trigger 18 of the block triggers the second single vibrator 12, the pulse at the forward output of which, with its leading front, sets the trigger 19 of the module to state 1. The output from the output of the trigger 19 of the module enters the inputs of the elements OR 20, 14 and 15 and on watts, the second input of multiplexer 5, which selects from the third to fifth bits of the address word, respectively. As for the block number selection cycle, the signal from the output of the element OR 20 allows decryption of information sent to the address inputs of the decoder

block. Selected information from the outputs of JQ ra 4. From the output of the decoder 4 signal

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multiplexer 5 is fed to the inputs of the decoder 4, the control input of which receives a signal from the output of the element OR 20, enabling the decryption of information. From the output of the decoder 4, the signal carrying the information about the number of the selected unit is sent to the corresponding input-output unit number. I / O blocks are connected in such a way that each block with a specific number from 0 to 15 is connected to the corresponding outputs of the decoder 4, having the same number. The block selection signal is fed to the input of a trigger for connecting an input / output block (not shown). The sync input of this trigger receives a signal block number from the element 13, while the signal delay block number relative to the signal carrying the information about the block number is determined by the duration of the blocking pulse received at the input of the element 13 from the inverse output of the first single-vibrator 11. of these two signals at the inputs of the block connection trigger

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With the decoded module number, it enters the selected input-output block at the input of the module number register (not shown). The information in the module number register is recorded with the arrival of the signal on the module's synchronous input. The module number is coming from the output of the AND 14 element. Signal delay The I / O unit generates the SP signal indicating that the module is selected. This signal is fed to the exchange control block 3 at the input of the AND element 15, which outputs the SP signal, notifying the control processor about that the issuance of the address is over.

The SP signal generated by the input-output block after receiving the block number is blocked by the signal from the trigger of module 19 because the selection of the block number is not the end of the ad delivery cycle

I / O sets it to state 1, thereby giving permission for the exchange of information between the control-

processor and the selected I / O unit. Thereafter, a receive synchronization signal (SP) is generated in the selected I / O unit, which is fed to the input of block trigger 18 and returns it to its original state. In this case, blocking is removed from multiplexer 5, AND 13 is blocked, the block number signal is removed, and hence the SP signal. The choice of block I / O made.

The signal from the inverted output of the trigger 18 of the block triggers the second single vibrator 12, the pulse at the forward output of which, with its leading edge, sets the trigger 19 of the module to state 1. The output from the output of the trigger 19 of the module enters the inputs of the elements OR 20, 14 and 15 and per watt, the second input of multiplexer 5, which selects from the third to fifth bits of the address word, respectively. As for the block number selection cycle, the signal from the output of the element OR 20 allows decryption of information sent to the address inputs of the decoder

Q ra 4. With the output of the decoder 4 signal

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With the decoded module number, it enters the selected input-output block at the input of the module number register (not shown). The information in the module number register is recorded with the arrival of the signal on the module's synchronous input. The module number coming from the output of the And 14 element. Signal delay The module number relative to the information signal is determined by the duration of the blocking pulse, the post; the input element AND 14 from the inverse output of the second one-oscillator 12. The I / O unit generates a SP signal indicating that the module is selected. This signal is fed to the exchange control unit 3 on the input of the AND element 15, which outputs the SP signal, notifying control processor that the issuance of the address is over.

The SP signal generated by the input-output block after receiving the block number is blocked by the signal from the module trigger 19, since the selection of the block number is not the end of the ad delivery cycle

After receiving the SP signal, the control processor removes the address word and the signals BA and CB. The disruption of the signal BA blocks the first 11 and second 12 one-shot, trigger 18 of the block, trigger 19 of the module and element 15. At the same time, the signals of the module number and SP are removed. After the end of the address issuing cycle, a cycle of writing information into the selected module or reading cycle of information from the selected module follows.

Claims (2)

Invention Formula 1 o Device for information exchange between a control processor and an external device, comprising a control unit, a decoder, a multiplexer, a bus driver, the first and second input-output groups of the logical condition of the control unit form the input-output groups of the device dp connected to the input groups respectively - the synchronization outputs of the control processor, the first, second outputs of the control unit are the outputs of the device for connection respectively to the first, second command input am external device, inputs the first logic c Uppal conditions g--: control unit with a group Sodin 0 bus driver input / output terminals are connected with a group of information outputs of the decoder and form a device input / output group for connecting to a group of information and address inputs and outputs of an external device, while the group of information outputs of the multiplexer is connected to the group of information inputs of the decoder. 2. The device according to claim 1, characterized by e. by that. the control unit contains a block trigger, a trigger module, a bus driver, two single vibrators, five elements AND, two elements. OR, the first group of information inputs-outputs of the bus driver, the output of the first element AND, and the first start input of the first single-oscillator form the first group of inputs-outputs of the logic condition of the block, the second group of information inputs-outputs of the bus driver, the synchronous input of the block trigger, connected to the first input of the first element I, form the second group of inputs-outputs of the logic block catch block, the first input of the second AND element is connected to a first input of the third AND gate and is input to a logic block conditions, the second input of the second AND gate, the first, second inputs of first OR form 0 five WITH the input direction of the exchange bus form, a group of inputs logical condition -Jw the generator and forms a group of device inputs for connecting to the group of command outputs of the control processor; the input of the logic condition of the control unit is connected to the enabling input of the bus driver and is the device input for connecting to the command output of the control processor; the block, the outputs of the fourth, fifth, and AND are the first, second outputs of the block, the output of the second OR element, respectively, is a third d (the block output, the single output of three blocks of the block, is connected to the first inputs of the fourth AND element, the second OR element, and Fourth output block, single output three the third, fourth and fifth outputs of the block 45 P module is connected to the first input the controls are connected respectively to the permitting input of the decoder and to the first, second control inputs of the multiplexer, differing; Now with the aim of raising VIA of speed and simplification, the group of information inputs of the multiplexer is connected to the first group of information inputs-outputs of the bus driver and forms the group of input-output devices for connection to the group of information and address inputs-codes of the control processor, the second group of information , the block, the outputs of the fourth, fifth AND elements are respectively the first, second outputs of the block, the output of the second element OR is the third step of the block, the unit output of the block trigger is connected to the first inputs of the fourth element AND, the second OR element and is the fourth output of the block the single output of the trigger element AND, with the second inputs of the first element AND, the second element OR is the fifth output of the block, while in the control unit the output of the second element And is connected to the zero inputs of the module and block triggers, with the first launch input of the second one-shot and the second start input of the first one-shot, the first the output of which is connected to the unit input of the block trigger, the zero output of which is connected to the second start input of the second one-shot, the first output of which is connected to the second The input of the fifth element I and the third input of the first element I and the second outputs of the first AND second one-oscillators are respectively connected with the second input of the fourth element I and with the single input of the module trigger, the output of the first element OR is connected to 1 the second input of the third element And, the output of which is connected to the control input of the bus driver, the information inputs of the block and module triggers and the synchronous input of the module trigger are connected to the device potential zero bus