SU1405042A1 - Data input device - Google Patents

Description

resetting the address counter, the fourth to eighth keyboard block outputs are connected to the third and fourth inputs of the zone search block, to the sixth input of the synchronization block, to the third and fourth inputs of the shaper of cleaning commands, respectively.

2, The device according to claim 1, characterized in that the field border former contains the first and second single vibrators, a generator of rectangular impulses, an inverter, the first and second elements OR, six elements AND, two triggers, a counter and a delay element, the input of the first the one-shot is the first input of the shaper, the first input of the first element AND connected to the input of the inverter is the second input of the shaper, the first input of the second element OR is the third input of the shaper, the first input of the sixth element AND is the fourth input the former, the output of the sixth And element is connected to the first inputs of the second and fifth And elements and is the first output of the former, the outputs of the first And element and the first inverter are connected respectively to the installation and reset inputs of the first trigger, the output of which is connected to the input of the square pulse generator and the first input of the first element OR, the output of the first element IL11 is connected to the second input of the first element I, the installation input of the second trigger and is the fifth output of the former, the output of the first one-oscillator connected to the first; at the input of the third element AND and the second input of the second element AND, the output of which is connected to the second input of the first element OR, the output of the third element AND is connected to the reset input of the second trigger and is the fourth output of the driver, the output of the second trigger is connected to the first the input of the fourth element And the input of the delay element connected to the output of the second gatherings of the third and sixth elements And the output of the generator of rectangular pulses connected to the second input of the fifth element And the counting input of the counter connected by the output to the second input of the fourth element AND, the output of which is the second output of the imaging device and connected to the second input of the second element OR, the third input of which is connected to the output of the fifth element AND, the output of the second element OR is connected to the input of the second single-oscillator, the output of which is a third party shaper output.

3. The device according to claim 1, DIFFERENCE, m e e so that the zone search block contains a single vibrator, an OR element, an AND element and a trigger, the inverse output of which is the left output of the block, the inverter input is the first input of the block, the inverter output connected to the first input of the AND element, the second input of which is connected to the reset input of the trigger and is the second input of the block, the first input of the OR element is the third input of the block, the input of the one-shot is the fourth input of the block, the inverse output of the one-shot is connected to the second input of the IL element And, the output of which is the second output of the block, the trigger setup input is connected to the direct output of the one-shot.

4. The device according to claim 1, about tl and the fact that the shaper of the cleaning commands contains a D-flip-flop, a delay element, an AND element, a one-shot, the OR element and a code generator, the output of which is the first output of the cleaning command shaper , the clocked input of the D-flip-flop is the first input of the AND element, the information input of the D-flip-flop and the first input of the OR element are the inputs of the shaper of the cleaning commands from the first

the fourth, respectively, the output of the element OR is central with the input of the code generator and is the second output of the cleaning command generator, the output of the D-flip-flop is connected via the delay element to the second input of the AND element whose output is connected to the input of the one-oscillator, the direct output of which is connected to the reset input D trigger, the one-shot inverse output is the third output of the cleaning command generator and is connected to the BTopbEvi input of the OR element and the third input of the I.

5. The device according to claim 1, about tl and - so that the synchronization unit contains AND, the first and second elements OR, an inverter, a trigger and a one-shot, the output of which is connected to the first inputs of the fourth and n In addition, the output of the fifth element of AND is the second output of the block, the first input of the second element of AND is the first input of the block, the first input of the third element of AND is the second input of the block, the first input of the first element of AND is connected to the first input of the first element OR with the input of the inverter, with the second input quarter th element is D and the third input unit, the second input of the third AND gate is a fourth block input, a second input of the first AND element is connected to the second input of the second AND gate and is the fifth input unit, the second input of the first

405042

element 1-SHI is the sixth input of the unit, the output of the first element OR is connected to the reset output of the trigger, the output of which is connected to the input of the one-oscillator, the output of which is connected to the second input of the fourth element And, and the first input of the fifth element And is the first. the output of the block, the second input of the fifth element And is connected to the output of the inverter, the output of the fifth element And is the second output of the block, the input of the trigger installation is connected to the output of the second element OR, whose inputs from the first to the third are connected respectively to the outputs of the first, second and third elements And,

one

The invention relates to automation and computing and can be used in data preparation devices for input into a computer.

The aim of the invention is to reduce power consumption by more efficiently using the storage capacity of the device.

FIG. 1 is a block diagram of the proposed information input device; in fig. 2 - the functional diagram of the field floor imager; in fig. 3 - functional block diagram for ska zone; in fig. 4 — shaper of cleaning commands; in fig. 5 is a functional diagram of the synchronization unit in FIG. 6 is a functional block diagram.

In FIG. 1, there are: keyboard 1, encoder 2, multiplexer 3,; memory unit 4, indication unit 5, synchronization unit 6, control unit 7, address counter 8, checkpoint counter 9, shaper 10, field boundaries, decoder 11, zone search unit 12, shaper 13 cleaning commands, buffer register 14, input 15 locks of the keyboard unit 1 and nine of its outputs 16-24, six inputs 25-30 and two outputs 31-32 of the synchronization unit 6, six inputs 33-38 and five

0

five

outputs 39-43 of control unit 7, four inputs 44-47 and five outputs 48-52 of a generator 10 slots. a floor, four entrances 53-56 and two exits 5 57-58 blocks. 12 search zones, four inputs 59-62 and three outputs 63-65 of the cleaning command generator.

The shaper 10 of the field boundaries contains (Fig. 2) the first it second 66-67 one-shot, the generator 68 rectangular pulses, first to six, the sixth elements And 69-74, inverter 75, s, the first to second elements IL11 76-77, the first and second triggers 78-79, score 80, element 81 zad kki.

The zone search unit 12 (FIG. 3) contains a one-shot 82, an inverter 83, an element OR 84, an element AND 85, and a trigger 86.

The shaper of the cleaning instructions (FIG. 4) contains a D-flip-flop 87, a delay element 88, an AND element 89, a one-shot 90, an IDN element 91, and a code generator 92.

The synchronization unit (FIG. 5) contains AND 93-97, first to second elements OR 98-99, an inverter 100, a trigger 101 and a one-shot 102.

The control unit 7 (FIG. 6) contains first to second inverters 103-104, first to fifth elements.

0

thirty

 105-109, trigger 110, generator AND 1 rectangular pulses, counter it decoder 112, from the first to the second elements And 113-114. A: Keyboard 1 contains the keypad for data set and control, bounce protection circuit. When you press any data key, a parallel binary and a symbol is formed at the outputs of the encoder 2, which is fed to the information returns of the first group of multiplex 3. Memory block 4 records or reads the input character. 15 Using the display unit 5, the visual control of the entered characters is carried out. The synchronization unit 6 performs synchronization control of the control unit 7 upon the arrival of 20 synchronization pulses from the keyboard 1.

The field boundary generator 10 is used to determine the time when the separator codes appear at the beginning and end of the field, which makes it possible to use the memory block capacity more efficiently by using a non-fixed data recording format. In addition to JToro, the field boundary generator 10 is used to control the counters 8 and 9 and the control unit 7 to provide a dynamic display. For this, address counter 8 operates in two modes: forward counting with a low frequency f / k, where k is the frequency division factor, and reverse counting is done with a high frequency f.

The decoder 11 is used to control the shaper 10 of the field boundaries by the zone search unit 12 and the shaper 13 of the cleaning commands, as well as to reset the 9-character counter to the zero state at the moment when the device for the field separator code appears at the output.

The zone search block 12 provides after each pressing of the Start of zone key on the keyboard 1 the setting of the counter 8 addresses and the initial data field, or the installation of the counter 8 addresses on the Last field after pressing the End key.

The shaper 13 of the cleanup commands sequentially writes the gg code of the field divider to the place of the previously typed characters according to the field end signals received continuously from the shaper of 10 field boundaries.

U050424

The buffer register 14 is designed to temporarily store one character after it is read from block 4. memory

The input device works as follows

The preparation of the device for data recording, starting from the starting address (first field), is accomplished by filling all the cells of the memory unit with field separators. When you press the Clear key on the keyboard 1, the output 24, a signal appears, which is fed to the input 62 of the imaging unit 13 of the cleaning commands. From the output of the OR 91 element, this signal arrives at output 64 and input of shaper 92, at output 63 of which the field separator code appears, which is fed through multiplexer 3 to the data input of memory block 4. The signal from the output 64 is fed to the input 36 of the control unit 7, where it goes through the OR element 105 and enters the input of the AND element 114 and allows the generation of recording signals at the output 39, since the trigger 110 switches the output of the generator 111 through the OR 106 element the counter input with decoder 112 receives continuous pulses. At the first clock of the generator, through the elements AND 113 and OR 108 a pulse passes to output 42 and from it to the counting input of the counter 8 addresses. Then | At 2-4 clock cycles of the generator through the elements OR 109 and AND 114, the recording signal is generated at the output 39, and the pulse from the output 3 of the decoder 112 is fed to the output 40 of block 7 and from it to the input of the block 4 of memory. Thus, while the key is pressed, the sequential filling of all the cells of the block 4 with the divider floor takes place. To completely clear the memory block 4, the time for pressing the Cleaning key must be at least C / F, where C is the capacity of the block 4 in characters, F is the frequency of the generator 111. After clearing the memory block 4 by pressing the Start button on the output 20 keypad 1, a signal is generated, which is fed to input 55 of zone search 12, where through the element RtM 84 it is fed from output 58 to the reset input of address counter 8, from output 50 of the former 10 field boundaries to input 34 of block 7 continuously

35

40

50

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50

five

g

The preparation of the device for data recording, starting from the starting address (first field), is accomplished by filling all the cells of the memory unit with field separators. When you press the Clear key on the keyboard 1, the output 24, a signal appears, which is fed to the input 62 of the imaging unit 13 of the cleaning commands. From the output of the OR 91 element, this signal arrives at output 64 and input of shaper 92, at output 63 of which the field separator code appears, which is fed through multiplexer 3 to the data input of memory block 4. The signal from the output 64 is fed to the input 36 of the control unit 7, where it goes through the OR element 105 and enters the input of the AND element 114 and allows the generation of recording signals at the output 39, since the trigger 110 switches the output of the generator 111 through the OR 106 element the counter input with decoder 112 receives continuous pulses. At the first clock of the generator, through the elements AND 113 and OR 108 a pulse passes to output 42 and from it to the counting input of the counter 8 addresses. Then | At 2-4 clock cycles of the generator through the elements OR 109 and AND 114, the recording signal is generated at the output 39, and the pulse from the output 3 of the decoder 112 is fed to the output 40 of block 7 and from it to the input of the block 4 of memory. Thus, while the key is pressed, the sequential filling of all the cells of the block 4 with the divider floor takes place. To completely clear the memory block 4, the time for pressing the Cleaning key must be at least C / F, where C is the capacity of the block 4 in characters, F is the frequency of the generator 111. After clearing the memory block 4 by pressing the Start button on the output 20 keypad 1, a signal is generated, which is fed to input 55 of zone search 12, where through the element RtM 84 it is fed from output 58 to the reset input of address counter 8, from output 50 of the former 10 field boundaries to input 34 of block 7 continuously

five

0

0

pulses are given, but since in the memory block 4, only field separators are recorded, from block 4 to the data input of the buffer register 14, field separator codes are received, which, using the decoder 11, reset the counter of 9 characters and the indicators in block 5 to the zero state The device is ready for a data set.

When manually typing data on the keyboard 1, the parallel binary code of the characters from the output of the encoder 2 through multiplexer 3 is fed to the input of memory block 4. At the same time, at output 19 of keyboard 1, a synchronizing pulse (FID) is received at input 27 of synchronization unit 6, where it takes signal 1 through element OR 98 from the reset input of trigger 101 and through inverter 100 from input And 97. At the same time, the FID comes to inputs And 93 and 96 elements. As soon as the output signal 51 of the former 10 appears at the end-of-field signal, the flip-flop 101 is switched by a pulse arriving at its installation input through the elements AND 93 and OR 99. The single-vibrator 102 starts and generates at its output floor divider then through A decryption signal with a single pulse, which, through rator 11, counter 9, resets AND element 96 to output 31 and from it to block 33 of block 7, the control state, in the driver 10 at output 51, the end-of-field signal appears, and At outputs 49 and 50 are set in the cleaning mode, a single high frequency pulse is generated. From the recorded write pulse and in block 4, instead of block 4 of the memory, it is read again.

laziness in which similarly as

splitter floor is typed character. This symbol, even before the keyboard key 1 is lowered, is immediately read and reproduced for visual control in block 5. Since from the output 50 of the imaging unit 10, the signals in the form of one after the other pulse bursts continuously arrive at the input 34 of the control unit 7

the typed character code, and then the field separator code, according to which the driver 10 at its output 52 40 generates a start field signal and then the reading process is repeated, thus providing a dynamic indication of the data.

45

A set of subsequent symbols is implemented with the frequency f and f / K, where f - the frequency stays the same until generator 68 and K is the coefficient from the second counter output 9 dividing characters of counter 80 in the shaper does not receive a signal at the input 15 blocks 10. When generating pulses for the keyboard to close, at which a signal arrives at frequency 48, any data key will not 50 minutes, which will set the mode of the FIS signal and, following the count of the address 8, and at high frequency - countdown mode.

When the first low-frequency pulse is output from output 49 to the counting gg input of the 9-character counter, a signal arrives at the connection in block 5 of the first

In fact, the maximum number of characters typed in the field will not exceed the number of indicators in block 5.

If five characters were written in the first field, then the dynamics of the change of addresses of counter 8 looks like this:

direct my account and 3 4 5

indicator. Simultaneously through the element OR 77 and the second one-shot 67

the pulse arrives at output 50, and from it to input 34 of block 7, where, according to this, pulses generate only the counting signal, since the signal from input 34 through the element OR 106 switches only trigger 110. At the first clock of the generator 111 at the first output a counter with a decoder 112, a pulse appears, which, through elements AND 113 to the IPI 107, resets to the zero state

buffer register 14, and through the element OR 108 the counter 8 switches by one step. The character code from block 4 is read in the third clock of the generator 1 1 1 and through the buffer register 14

enters the input of the display unit 5. The trigger 11 1 is set to zero at the seventh clock of the oscillator 111. When the second low frequency pulse arrives, the pulses are generated along the outputs 49-50 along with the counter 9 characters in- transition. the second indicator in block 5 switches on and connects. But since at this moment from memory block 4 it is read

the typed character code, and then the field separator code, according to which the driver 10 at its output 52 generates a start field signal and then the reading process is repeated, thus providing a dynamic indication of the data.

45

50

A set of subsequent characters is done in the same way until the second output of the counter 9 characters receives a signal at the keyboard lock input 15, which, when you press any data key, will not generate a signal of FIR and, subsequently,

In fact, the maximum number of characters typed in the field will not exceed the number of indicators in block 5.

If five characters were written in the first field, then the dynamics of the change of addresses of counter 8 looks like this:

countdown 5 4 C D

direct account 1 2, etc.

After typing all the field symbols, in order to switch to the next field, you must press the Shift key on the keyboard 1, From the output 17, the signal is fed to the input 25 of the synchronization unit 6, and simultaneously the sync pulse of the command (SIK) appears at the output 22 of the keyboard 1. at input 30 and through element 1-ШИ 98 removes the prohibition from trigger 101. When a signal appears at output 51 of the driver, 10 signals End of the floor through elements AND 94 and OR 99 of starting the reverse

score 6 7

The device is ready to record data of the second and subsequent fields.

If after the visual control an incorrect data record is found in any field, then it can be erased by pressing the Erase floor key. At the same time, from the output 23 of the keyboard 1 to the input 61 of the generator 13 of the cleaning commands, a signal arrives and as soon as a pulse of the end of the field at the input 59 from the generator 10 appears, then D - the flip-flop switches through the delay time of element 88 at the second input of element 89 is the signal 1. The delay time of the element 88 is chosen longer than the duration of the eighty clock cycles of the generator 110 in the control unit 7 with the condition that the first pulse arriving at the input 60 of the generator 13 of the cleaning commands from the output 43 of the unit 7 is not passed to the output of the elements 89 and which is formed on the sixth clock generator 111 shifted by two clock cycles after a read pulse from the output 40, at which the leading edge with a slight delay (caused mainly by the time switching transients cell memory unit 4) is formed by the end of pulse floor. From the output 50 of the imaging unit 10, high-frequency pulses are received in the control unit 7, and by a signal from the output 48 the counter 8 of the address is set to the countdown mode. Therefore, in the 4-memory block, characters are read, starting from the end to the beginning. After reading the most recent symbol, the floor at the 6th cycle of the generator 111 to the input 60 of the driver

trigger 101 and a one-shot 102, the pulse from the output of which through element I 97 is fed to output 32, and from it to input 35 of block 7. The pulse from the output of element WIT 108 is fed to output 42, and from it to counting input of counter 8 and switches it to 6d1-1n step to the right. The display goes out, since now only the floor separators are removed from memory block 4. The dynamics of changing the address of the counter 8 will be as follows:

direct my account

0

35

brotherly

score

7, etc.

13 cleaning commands receive a pulse, 0 which, through element I 89, triggers the one-shot 90, the pulse from the direct up-slope of which is reset (2m trigger 87 to the initial state. The pulse from the inverse output of the one-pass 5 of 90 provides through the shaper 92 and multiplexer 3 feed

- a code for separating the field to the data input of the memory block 4. At the same time, from output 64, a pulse arrives at input 36 of control unit 7, where a recording pulse is generated at output 40. Then, similarly, the second and subsequent characters are erased automatically from the end of the floor until all the characters of the floor are erased. After that, it is possible to carry out a manual set of reliable characters of the field, the number of which in the new field should not exceed their number in the erased field.

When interruptions occur, the main power supply (not shown) should be turned off. When it is next turned on, it is necessary to find the end of the zone to continue recording. For this purpose, in Block 1, the End Zone key is pressed and from output 21 to input 56 of Zone Search 12, a signal is received that triggers the single-vibrator 82, the output single pulse of which through the OR 84 element enters output 58 and resets the address counter 8 to zero state (first field). At the same time, the trigger 86 is switched. The signal from the output 57 is fed to the input 38 of the unit 7 to form the reference signals in it and to the input 47 of the generator 10, where the signal

0

45

0

55

1 from the input of the AND 74 element. Thus, at the output 48, a signal 1 is set, which transfers the counter 8 of the address to the countdown mode. From the memory block 4, in the direction from the end to the beginning, the field separators all the time are removed, which each time remove the resolving potential from the first input of the element. And 85 So it goes on until the last character of the previously recorded last field of the data array appears from the buffer register 14 instead of the field delimiter. At this moment, the pulse of the field separator does not arrive at the input 53, therefore, when the pulse of the read end pulse is detected at the input 54 of the block 7 at the output of the AND 85 element, a pulse is generated that switches the trigger 86 to the initial state and the search process for the end of the zone ends and block. 5, the last field of the zone is displayed.

Information control during editing is carried out by a quick review of the data in memory block 4 by pressing the Shift Left or Shift Right key. So, when pressing the Shift key to the left, at the output 18 of the keyboard 1, a signal appears that is fed to the input 26 of the synchronization unit 6. Once from shaper 10 on

input 28 receives a start signal field 35 of the zero state. Level 1 signal

At the output of element 95, an impulse appears, which through element OR 99 switches the trigger 101, which triggers the one-shot 102. A single impulse from the generator through element 97 connects to output 32, and from it to input 35 of block 7, where it forms element output OR 108 pulse arriving at output 42 and switching the 1st counter to the 8 address one step to the left. In block 5, the previous field is induced. Moving the counter one step to the right (in the next field) is done pressing the clave

Shea Shift to the right and occurs analog-50 high frequency f with the output element

It is logical, but only now the pulse to the counting input of the counter 8 arrives at the moment of occurrence at time 29 from the shaper 10 of the field end signal.

The information recorded in memory block 4 can be output to external devices (computers, NML, etc.) at any time for further processing or accumulation of data. For this

The address counter 8 is reset to the initial state by pressing the Start Zone key, and then sequentially from the external device to the shaper 10, a constant level 1 signal and pulses with a period of more than 6 clock cycles of the generator 111 in block 7 are respectively fed to inputs 45 and 46. In this case, the generation of pulses with a frequency f in the shaper 10 is stopped and the indication goes out.

Extra clock pulses through the former 10 are fed into block 7

control for the subsequent sequential reading of data, starting with the first character of the first field. The end of the output can be determined automatically, for example, by counting an external device with 3-4 fields continuously separating one after another and then removing signals from the first input of the device Output and pulses from the second input of the device. External clock pulses.

Shaper 10 boundaries floor works in the same way.

In the initial state, through the inverter 75, a level 1 signal is applied to the input of the zero setting of the trigger 78, and the trigger is in the initial state.

the inverted output of the trigger 78 is fed to the control input of the generator 68, at the output of which high-frequency pulses f are generated.

These pulses are fed directly to the input of the element And 73 and through the counter 80 operating in the frequency splitter mode with a division factor K to the input of the element 72. When the trigger 79 is in the zero state at the output of the element 74 and accordingly there is Potential 1 and counter 8 addresses are in the countdown mode. Burst with

And 73 through the element OR 77 and the second one-shot 67 is fed to the code 50 and from it to the input 34 of the control unit 7, where signals 55 are generated for reading characters from the memory block 4, starting from the end to the beginning of the field. The display of characters does not occur, since the counter of 9 characters is reset, and the input pulse on its cqeTHbm

eleven

from the output of the element And 72 do not come. As soon as the symbol of the splitter field is read, a signal appears at the input 44 which, at the output of the first one-shot 66, will form a single short pulse that switches the trigger 79 into one state through the elements AND 70 and OR 76. Next to this, at the output 52, a start field signal is generated. Through the delay time of the element 81 at the output of the element 74, the level O is established and the address counter 8 goes into the direct counting mode. At the output of the element 72, a burst of pulses with a low frequency f / K is impressed. These pulses from output 49 are fed simultaneously to the counting input of the counter 9 characters, and from output 50 to input 34 of the control unit 7 for the sequencer for reading the characters of the field from the memory 4, starting with the first character. On the light panel block 5

Indicadia each character pic pedovatel-25 de element And 74 and respectively

but is displayed during the K / f time, where K is chosen equal to 8-10, and f is usually a few cGd in order to ensure reliable visual reading in the dynamic display mode. As soon as after the last character, the separator field symbol is read, then again, similarly, at the output of the generator 68, a pulse is generated, which, through the element 71, forms the output signal Ko42

12

The low field switches the trigger 79 to the initial zero state. After the delay time of the element 81 at the output of the element 74, the potential 1 is set to 1, the counter 8 of the address goes to the countdown mode, and further the work is repeated.

To output information from memory block 4 to an external device, an output is sent to input 45. The output by which inverter 75 removes the signal 1 from the input to the zero setting of the trigger 78. As soon as the output of the element OR 76 appears, the signal starts through the element And, 69 trigger 78 is switched to one state. At the control input of generator 68, a level O signal appears and generator 68 stops generating pulses at a frequency f. At the same time, through the OR element 76, the trigger 79 is set to one state, and at the exit 48 of the driver, a level signal O appears, which switches the address counter 8 to direct counting mode. For the subsequent reading of data: from block 4 of memory it is necessary to send clock signals from input device 46 to input 46, which, via OR 77 and generator 67, go to control unit 7 to form pulse and inversion for memory block 4.

60

FIG. 2

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FIG. five

Claims (5)

1. 'DEVICE FOR INFORMATION INPUT, containing a keyboard, the group outputs of which are connected to the inputs of the encoder, the outputs of which are connected to the information inputs of the first group of the multiplexer, the outputs of which are connected to the information inputs of the memory block, the address inputs of which are connected to the outputs of the address counter, character counter, the group outputs of which are connected to the address inputs of the display unit, the output of characters is connected to the keyboard input, the first, second, third outputs of which are connected respectively to the first, second and the network inputs of the synchronization unit, the first output of which is connected to the first input of the control unit, the first and second outputs of which are connected to the write-read and access inputs of the memory unit, respectively, characterized in that, in order to reduce power consumption, a field boundary generator, a decoder, a block are introduced zone search, a shaper of cleaning commands and a buffer register, the outputs of which are device outputs and are connected to information ones. the inputs of the display unit and the inputs of the decoder, the output of which is connected to the reset input of the character counter, with the first inputs of the zone search unit and the field boundary generator, the second and third inputs of the field boundary generator are the first and second inputs of the device, respectively, the outputs of the field boundary generator from the first to fifth connected to the input of the reverse of the address counter, with the counting input of the character counter, with the second input of the control unit, with the input of the formulator of the cleaning commands and the sixth input of the synchronization unit, with the fifth input synchronization eye, respectively, the second output of the synchronization unit is connected to the third input of the control unit, the third output of which is connected to the reset input of the buffer register, the information inputs of which are connected to the outputs of the memory unit, the fourth output of the control unit is connected to the counting input of the address counter, the fifth output to the second the inputs of the zone search unit and the cleanup command generator, the first output of which is connected to the information inputs of the second group of the multiplexer, the second output is to the fourth input of the control unit, the third output is to the fifth input of the control unit, the sixth input of the control unit is connected to the fourth input of the ZfQQQfl OS of the field boundary equalizer and the first output of the zone search block, the second input of the zone search block is connected to the address counter reset input, the outputs of the fourth to eighth keyboard block are connected respectively to the third and fourth inputs of the zone search block, to the sixth input of the synchronization block, to the third and to the fourth inputs of the cleanup command generator. 2. The device according to claim 1, characterized in that the field boundary generator comprises a first and second one-shot, a rectangular pulse generator, an inverter, a first and a second OR element, six AND elements, two triggers, a counter and a delay element, the input of the first one-shot is the first input of the shaper, the first input of the first element And connected to the input of the inverter, is the second input of the shaper, the first input of the second element OR is the third input of the shaper, the first input of the sixth element And is the fourth input driver, the output of the sixth element And is connected to the first inputs of the second and fifth elements And is the first output of the driver, the outputs of the first element And and the first inverter are connected respectively to the inputs of the installation and reset of the first trigger, the output of which is connected to the input of the square-wave generator and the first input of the first OR element, the output of the first OR element is connected to the second input of the first AND element, the input of the installation of the second trigger and is the fifth output of the driver, the output of the first one-shot switch en to the first. the input of the third element And and the second input of the second element And, the output of which is connected to the second input of the first element OR, the output of the third element And is connected to the reset input of the second trigger and is the fourth output of the driver j output 'of the second trigger is connected to the first input of the fourth element And and the input a delay element connected by the output to the second inputs of the third and sixth AND elements, the output of the square pulse generator is connected to the second input of the fifth And element and the counting input of the counter connected by the output to the second input of the fourth AND element, the output of which is the second output of the driver and connected to the second input of the second OR element, the third input of which is connected to the output of the fifth AND element, the output of the second OR element is connected to the input of the second one-shot, the output of which is the third output of the driver. 3. The device according to claim 1, characterized in that the zone search unit contains a single vibrator, an inverter, an OR element, an AND element, and a trigger whose inverse output is the first output of the block, the inverter input is the first input of the block, the inverter output is connected to the first input of the element And, the second input of which is connected to the trigger reset input and is the second input of the block, the first input of the OR element is the third input of the block, the input of the single vibrator is the fourth input of the block, the inverse output of the single vibrator is connected to the second input of the OR element, Exit which is a second output, the input coupled to the trigger setting direct access monostable. 4. The device according to claim 1, wherein the cleaning command generator comprises a D-trigger, a delay element, an AND element, a single vibrator, an OR element, and a code generator, the output of which is the first output of the cleaning command generator, a clock input D -trigger, the first input of the AND element, the information input of the D-trigger and the first input of the OR element are the inputs of the first and fourth cleanup command, respectively, the output of the OR element is connected to the input of the code generator and is the second output of the clear command ki, the output of the D-trigger through the delay element is connected to the second input of the And element, the output of which is connected to the input of the one-shot, the direct output of which is connected to the reset input of the D-trigger, the inverse output of the one-shot is the third output of the cleanup command generator and connected to the second input of the OR element and the third input of element I. 5. The device according to claim 1, characterized in that the synchronization unit contains from the first to fifth elements AND, the first and second elements OR, an inverter, a trigger and one vibrator, the output of which is connected to the first inputs of the fourth and fifth elements And, the output of the fifth element And is the second output of the block, the first input of the second element And is the first input of the block, the first input of the third element And is the second input of the block, the first input of the first element And is connected to the first input of the first OR element with the input of the inverter, with the second input of the fourth And it is the third input of the block, the second input of the third element And is the fourth input of the block, the second input of the first element And is connected to the second input of the second element And is the fifth input of the block, the second input of the first element is the sixth input of the block, the output of the first element OR connected to the reset output of the trigger, the output of which is connected to the input of the one-shot, the output of which is connected to the second input of the fourth element And and with the first input of the fifth element And, the output of the fourth element And is the first output of the block, the second input of the fifth AND element is connected to the inverter output, the output of the fifth AND element is the second output of the block, the trigger installation input is connected to the output of the second OR element, whose inputs from the first to the third are connected respectively to the outputs of the first, second, and third elements I.