SU1501170A1 - Device for controlling regeneration of information in dynamic memory - Google Patents

Abstract

The invention relates to computing and can be used to control the regeneration of information in a dynamic memory. The aim of the invention is to improve the speed of the device. The device comprises a pulse generator 1, a regeneration address counter 2, a multiplexer 3, an OR 4 element, a trigger 5, a control block 6, a memory block 7 and 8, a regeneration request analysis block 9. The analysis of the need for regeneration of information in the device occurs during the processing of the memory access without interrupting the operation of the processor. The generator 1 generates the regeneration request pulses with a period equal to half the regeneration period. The need for regeneration at the current address (counter 2) is determined by the lack of access to this address for half the period of distributed regeneration and the registration of a line with the same address in the previous step of analyzing the regeneration request. The processor is interrupted only in case of need for memory regeneration. 3 il.

Description

315

The invention relates to computing and can be used to control the regeneration of information in a dynamic memory.

The purpose of the invention is to increase the speed of the device.

Fig. 1 is a schematic diagram of a device for controlling the regeneration of information in a memory; Fig. 2 shows an example implementation of the control unit; FIG. 3 shows an example of implementation of the regeneration request analysis block.

The device contains a pulse generator 1, a counter 2 address regeneration, a multiplexer 3, an element SHIII 4, a trigger 5, a control unit 6, a memory block 7 and 8, a regeneration request analysis block 9, a memory access input 10, an input 11 end of memory access, address inputs 12, initial installation input 13, address outputs 14, regeneration output-15, output 16 of generator 1, outputs 17-21 of unit 6, inputs 22-25 of unit 9. Control unit 6 (Fig. 2) contains triggers 26-28, one-shot 29, elements AND 30-34, elements AND NOT 35- 41, element W-NOT 42, elements 43-47 delay and the time setting circuit l 48 one-shot.

Block 9 analysis of the request for regeneration (fig.Z) contains a trigger 49, the element W-NOT 50, the element I 51, the element AND-NOT 52 and the element 53 of the delay.

The device works as follows.

After turning on the power, before starting operation, a signal of the initial installation is supplied to the device 13, which sets the level of the log at the output of trigger 5. 1, at the output of the triggers 26, 27 and 49 - the log level, O, at the output of the trigger 28 - the level of the log.- 1.

The device operates in two modes determined by the control unit 6 depending on which of the signals: 10 memory access or 16 request for regeneration arrived earlier,

If signal 10 arrives before signal 16 (dynamic memory access mode), then trigger 27 switches to the log state. 1, the element AND-NOT 36 - in the state log,

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thereby switching multiplexer 3 to transmit the address of the access, Ele4

The mentor AND-NOT 37 switches to the state of the log, 1, the resulting leading edge of the signal at the output of the element

AND-NOT 37 starts the one-shot 29, which generates a pulse 18 sampling blocks 7 and 8, and also sends a signal to block 7 through the item IS-NOT 39. The signal is sent to block 7. Thus, log 1 is written to block 7 at the address of the address. With a delay (delay element 44) equal to the write cycle in the accumulator, the signal from the output of the NAND 36 element through the AND 31 element resets the trigger

27 in the state log. O. If during recording to block 7, the device received a request for regeneration 16 from generator 1, then it is fixed by switching trigger 26 to the log state, 1, and AND-NOT element 35 is switched to the log state, O only after trigger reset 27 in the state log, O, After switching the element AND-NOT 36 multiplexer

3 switches to gear again

addresses from the counter 2 addresses regeneration. Switching element AND-NOT 35 will cause the appearance on the code of the element AND 34 log, 1, this will be a signal

start one-shot 29 on the formation of the pulse 18 sample drives. After the selection time at the outputs of drives 7 and 8, information was read at the address formed by the counter 2 of regeneration addresses,

Depending on this information, the element OR NOT 50 forms a sign of regeneration 25, which translates the block

control in the appropriate mode of operation (table)

The elements AND-NO 41 and OR-NO 42 form signals when reading blocks 7 and B of the memory, which gates the recording of the regeneration feature 25 to the trigger 28. Initially, the trigger 28 is set to the - state log,

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01 1- About

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Record log, 1 in memory block 8 after the start of regeneration Record log. About .v blocks 7, 8 memory

therefore, if regeneration is necessary (the regeneration feature is a log. 1), then it does not change its

state, and the pulse at the output of the element OR NOT 50 switches the trigger 49 to the state log. one.

After the arrival of signal 11, the end of reversion trigger 5 switches to the state of the log. 1 (signal 24) and a negative pulse 15 is generated at the output of the NANDEM element 52, the duration of which is given by the delay element 53.

This pulse will be a signal for regeneration and through the delay element 47, which is necessary in the absence of access to the memory, it will trigger the one-shot 29 to generate signals from 18 samples of blocks 7, 8 bits, 20 records to memory block 8. Thus, a log is written to the drive 8 at the regeneration address. H

If there is no need to carry out regeneration (a sign of regeneration of the log. O), then at the output of trigger 28 a pulse of negative polarity is formed, the duration of which is determined by delay element 45. Through the delay element 46, which is not necessary to complete the reading of the memory blocks, this pulse through the AND 33 element blocks the processing of the call (if the trigger 27 is now set to the log state 1) 5 through the AND 34 element the single vibrator 29 starts to generate sampling pulses 18 of blocks 7 and 8, write pulse 19 to block 7, write pulse 20 to block 8. In this case, the log level is fed to information input 21 of blocks 7 and 8. About from the trigger output 28. The trigger 26 is reset to the log state. About with the signal from its output through the delay element 43, which sets the time equal to the time of access to blocks 7 and 8.

 Since signal 16 came before signal 10 (the mode of analyzing the need for regeneration without interrupting the operation of the processor), now trigger 26 switches to the log state. M. Then everything happens in the same way as described with the only difference that the entry in memory block 7 of the log. M at the address of the request was made either after resetting the trigger 26 to the state of the log. O through block read time

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7 and 8, determined by the delay element 43, or after resetting the trigger 28 to the state log. 1, set to the state log. About before resetting the trigger 26 to the state of the log. if there is no need for regeneration. If necessary, the regeneration trigger 49

50

5 Q ..

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five

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It is set to log. 1 and the regeneration is performed immediately after the arrival of the signal 24 formed by the trigger 5 on the leading edge of the signal 11 the end of the inversion. The regeneration signal 15, the duration of which is determined by the delay element 53; simultaneously serves as a memory unavailability signal for processing processor signals.

Thus, since the pulse generator 1 generates pulses of a request for regeneration with a period equal to half the regeneration period, the need for regeneration at the address from the counters 2 of the regeneration addresses is determined based on whether the address to the same address was used for the dynamic memory period with the same address in the previous step of analyzing the request for regeneration. Moreover, the processor stops working only if regeneration is necessary, i.e. analysis of the request for regeneration occurs regardless of the processor, if the cycle of its access to the memory for at least three cycles of access to the blocks 7 and 8 of the memory.

Claims (1)

Invention Formula A device for controlling the regeneration of information in a dynamic memory, comprising a pulse generator, which is connected to the counting input of the regeneration address counter, the output of which is connected to the first information input of the multiplexer, the second information input of which is the address input of the device, connected to the address inputs of the first and second memory blocks, the information inputs of which are connected to the first output of the control unit, the second output of which pogo connected to the inputs of the choice of the first and second memory blocks, the third and the fourth outputs of the control unit are connected to the recording inputs of the first and second memory blocks, respectively, the fifth output of the control unit to the control input of the multiplexer, the synchronization input and the control unit to the output of the pulse generator, the input sign of access to the memory and the initial installation input of the control unit respectively, corresponding inputs of the device, characterized in that, in order to increase the speed of the device, it contains a regeneration request analysis block, a trigger and an OR element, the first input of which is input on the end handling device, the second input of the OR gate is connected to the input of at ™ of the control unit memory access sign, the output of the OR element to the reset input of the trigger, whose installation input is connected to the initial installation of the control unit and to the first input of the regeneration request analysis block, the first output of which is the output of the device regeneration requirement and connected to the input regeneration of the control unit, the input of the sign of regeneration of which is connected to the second output of the analysis request block of the regeneration, the second and third inputs of which are connected to the information outputs of the first and volts respectively memory block, a fourth input of the regeneration request analysis block is connected to the trigger output. S .- “J 1B Log f srig.Z