SU1644120A2 - Device for data input - Google Patents

Abstract

The invention relates to computing and can be used to collect information from sensors in automated process control systems. The purpose of the invention is to increase reliability. The device contains Lormier 1, address register 2, trigger 3, multiplexer-4, elements 5, 10, control block 6, buffer memory block 7, working memory block 8, comparator 9, generator 11, correction block 12, reception block Signal Call. Improving the reliability of the device is the ability to obtain information at any time on sensors that are in an emergency condition. 1 il. g (L

Description

The invention relates to computing and can be used in automated process control systems.

The purpose of the invention is to increase the reliability of the device. The drawing shows a block diagram of the proposed device.

The device contains driver 1, address register 2, trigger 3, multiplexer 4, first element 5, control unit 6, buffer memory block 7, random-access memory 8, comparator 9, second element 10, generator 11, correction unit 12 , signal reception unit Call 13.

The device works as follows.

When the power is turned on, the output of the former 1 appears

which sets the register 2 addresses and trigger 3 to its original position. The signal from the first trigger output at the output of the first element And 5 generates a logic zero signal, and the signal from the second trigger output control unit 6 and the buffer memory block are set to the zero state. The first sensor polling cycle begins, in which the RAM 8 is set to the zero position. Under the action of the code coming from the output of the register 2 address to the address inputs of the multiplexer 4 and the operational memory block 8, the output of the first sensor is connected to the output of the first element I 5, and the output of the operational memory unit 8 generates a code th address The code from the output of the RAM unit goes to the first

with

4 GO

1H

the input of the comparator 9, to the second input of which the logical zero signal from the element 5 arrives at this time. If the output of the RAM block 8 has a logical unit signal, then the logical zero signal appears at the output of the comparator 9, which arrives at the second the input of the second element And 10, prohibits the passage of pulses from it from the generator and, arriving at the second input of the correction unit 12, signals the transition of the sensor from one state to another. The generator 11 generates at its outputs a negative polarity clock pulses shifted by 180 ° relative to each other. If there is a logical zero signal at the first input (the buffer memory block is free) and under the action of the first clock pulse, the first output of the correction unit 12 generates a write enable signal that is fed to the input of the buffer memory block. A clock pulse from the second output of the generator (TI2) records the code in the buffer memory block. But the recording does not occur, since at the reset input of the buffer memory block there is a reset signal from trigger 3. With the arrival of the second TI1, the write enable signal from the first output of correction block 12 is removed and a signal is generated at the second output, which records the logical zero code memory unit 8 at the address of the register 2, With the same signals at the inputs of the comparator 9, a signal of a logical unit is formed at its output, allowing the pulses to pass through the element I. 10. The next pulse switches the register 2 addresses d poll the next sensor and removes The signal recording from the second output correction unit. Similarly, a logical zero code is recorded in all cells of the RAM, where a logical unit was previously recorded. After the end of the first polling cycle at the output of the address register 2 overflow, a signal appears that sets the trigger 3 to its initial position, thereby connecting the output of multiplexer 5 to the input of the operational memory block 8 and removing the reset signal from the operational blocks memory and management.

In the second and subsequent polling cycles, the code from the sensor that has gone into the alarm state (the code of the logical unit) does not correspond to the code from the output of the RAM block 8 / logical code zero /. At the output of comparator 9, a logical zero signal appears, which prohibits the passage of TI1 through element 10, and, entering the second input of the correction unit, signals that the sensor goes to an alarm state. With a logic zero signal, the first input of the correction unit / buffer memory unit is free / and under the action of the first TI1, the recording output signal, which is fed to the input of the buffer memory unit, is generated at the first output of the correction unit. The first TI2 records the address code and the change code of this state in the first register of the buffer memory block. The second TI1 removes the write enable signal from the first output of the correction unit and generates a signal at the second output, which records the emergency state code of the sensor at the register address 2 into the RAM memory unit. At the output of the comparator, the enable signal is generated to pass TI1 through the element 0 TI2 shifts the message code from the first register of the buffer memory block to the second, and writes the code 000 to the first. The third TI1 translates the address register 2 into the next position to poll the next sensor and removes the signal from the second output The code of the correction unit 12. The third TI2 shifts the message code from the second register to the next, and the second two write 000 ... The removal of the other sensors from one state to another and the recording of messages about these transitions to the buffer memory is carried out similarly described. Under the action of M2, the message code in the buffer memory block is rewritten into the last register and a readiness signal appears at its last output. After processing this message, an acknowledgment (read acknowledgment) signal arrives, which is recorded in the control unit. The first TI1 generates a debit authorization signal at the output of the control unit. The first TI2 code of the message from the last register is written off - and it is written into it

516

The code from the penultimate register. The message recorded in the first register generates a signal of a logical unit at the output, which signals to the correction unit that all the registers of the buffer memory block are occupied. In this case, the messages in the buffer memory block will not be written until the last register of the buffer memory block is released from the message. The signal shifts the information in the registers by one position. As a result, the first register is released and the overflow signal of the buffer memory block is removed. Further operation of the device is similar to that described. The call signal arrives on the bus. The call is recorded in the reception unit 13. This signal, given a signal from the overflow output of register 2, is fed to the input of the comparator 9. Under the influence of a signal from the output of the comparator, an information availability signal / logical zero code / when the sensor code in this polling cycle does not correspond to the sensor code in the previous polling cycle / sensor transition from one state to another /, but also when the sensor code in this and previous polling cycles corresponds to the alarm state / logical code tion unit and from the sensor output from the RAM memory / unit. According to the information availability signal, the code of the address of the sensor in the alarm state and information about its state are written to the buffer memory block. After polling all the sensors with the second signal from the output of the overflow of the register of address 2, the call signal at the input of the comparag06

the torus is reset and the receiver returns to its original position. Thus, the detection and recording of information about sensors that are in an emergency state is carried out. This allows the operator to obtain information about the sensors in an emergency condition, which increases the reliability of the device. The receiving unit is a call signal built on two D-flip-flops of the 564 series. First, the call signal is recorded by the first trigger. Then, the pulse from the overflow output of the address register is rewritten to the second trigger, and the first trigger is reset to its original position. After all the sensors have been polled with a second pulse from the output of the address register, the second trigger returns to its original position.

Technical and economic advantages of the proposed device in comparison with the prototype consist in increasing the reliability of the device operation due to the possibility of obtaining at any time information about sensors that are in an emergency condition.

Claims (1)

Invention Formula Device for entering information on the author. N 1282107, characterized by the fact that, in order to increase the reliability of the device, a signal receiving block is inserted in it. The call, the synchronous input of which is connected to the address register overflow output, the information input is the device call input, the output of the signal receiving block. .