SU1287236A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing technology and can be used as a buffer storage device for channels and exchange devices, as well as information collection and processing systems. The purpose of the invention is the expansion of the field of application by analyzing the storage of x data. The buffer memory contains memory block 1, in, formational input 2 and output 3, address generation block 4, code analysis block 5, priority block 6, comparison block 7, register 8, elements OR 9 and 10, synchronization block 11, elements And 12 and 13, elements NOT 14 and 15, control inputs 16-19, control outputs 20-22 and control input 23. The data recorded in block 1 by the addresses generated by block 4 contain a code characterizing any sync parameter When reading, the data is analyzed in block 5 by comparing the code of the synchronizing parameter with the code in register 8 recorded with input 19. In case of coincidence or excess of the read parameter value, the data read from block 1 is transmitted to the consumer. Otherwise, they are removed from the buffer device. 1 3.p. A-ly. 6 W1. with S (L with

Description

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The invention relates to computing and can be used as a buffer storage device of channels and exchange devices, as well as information collection and processing systems. ,

The purpose of the invention is to increase the reliability of the device.

Figure 1 shows the structural diagram of the proposed buffer storage device; Fig. 2 is a block diagram of an address generation unit; FIG. 3 is a block diagram analysis of the code; figure 4 is a block diagram of the synchronization unit; FIG. 3 is a block diagram of a memory block; figure 6 - block diagram of the priority block.

The device contains a memory block 1, information inputs 2 and outputs 3, an address generation block 4, a code analysis block 5, a priority 6 blsgk 7 comparison priority block 6, a register 8, elements OR 9 and 10, a synchronization block 1, elements 12 and 13 , elements 14 and 15, control inputs 16-19, control outputs 20-22 and control input 23

The address generation unit 4 comprises a switch 24, a write address counter 25, a read address counter 26, a reversible counter 27, and an OR-NOT element 28 o.

The code analysis unit 5 comprises a switch 29, a register 30, a comparison unit 31, an OR element 32 and an AND element 33.

The synchronization unit 1 contains delay elements 34 and 35 and a pulse shaper 36.

The memory unit 1 contains a drive 37, a pulse shaper 38 and a delay element 39.

The priority block 6 comprises a generator of a Thor 40 clock pulses, triggers 41 - 44, elements OR 45 and 46, and a delay element 47.

The time interval during which data is stored (delayed in the buffer storage device, i.e., the time interval from the moment of their arrival from the transmitter to the Moment of their transfer to the consumer, is set by the processing time of a unit of Information by a consumer. Distribution of processing time of an information unit (a single message by chance my law leads to an increase

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probability of loss of reliability of information contained in the buffer. . storage device. Cases are possible, especially in systems operating in real time when information stored in a buffer storage device and not read by the consumer loses the necessary reliability, i.e. it will not be used by the consumer during processing. At the same time, the presence of this information in the buffer memory device leads to unproductive time losses in the future for the transfer of this data from the buffer memory device. Wah to the consumer and analysis of this data by the consumer.

In this device, the current value of the synchronization parameter is retrieved in the information transmitted through the buffer storage device, for example, the measuring device. This parameter can be the sampling time of the measuring sensors, the code number of the measuring cycle, etc. The found current value of the synchronization parameter is compared with the contents of the register in which the required limit value of the synchronization parameter is stored and can be changed at any time by the consumer.

In case of coincidence or exceeding the read value of synchronization. the read parameter from the buffer memory, the information is transmitted to the consumer. Otherwise, it is removed from the buffer storage device without being transferred to the consumer.

The device works as follows.

Before the start of operation, the signal on the installation input 23 of the counters 25-27 of the address generation unit 4, as well as the triggers 41 and 43 of the priority unit 6, are set to the zero state. The falling edge of the setup signal that passed the element OR 10 records the limit value code of the synchronizing parameter from inputs 19 into register 8. The falling edge of the setup signal that passes the element OR 32 records the limit value code of the synchronization parameter from the inputs

19 through the switch 29 into the register 30 of the code analysis block 5.

The device performs two operations: writing data to memory block 1 and reading data from it.

When a request is made to write data on the input 16 of the device, the latter sets in one state the trigger 41 of the priority block 6. On the positive edge of the signal at the first generator output 40 clock pulses, the trigger 42 of the priority block 6 is set to one, the output of which is fed to the memory control input and the address shaping block 4, where it connects to the address inputs of the accumulator 37 via a switch 24 output signals of the write address counter 25; The input to the control unit of the memory 1, the signal is delayed on the delay element 39 and then fed to the input of the imaging unit 38, which generates a data recording signal from the inputs-2 devices to the accumulator 37. When set in one state, the trigger 42 provides a reset through the OR element 45 trigger 41, and consequently, the trigger 42 in the next clock cycle of the 40 clock pulses. The falling edge of the signal at the input of the address shaping unit 4 is a modification of the write address counter 25 and the reversing counter 27, i.e. a unit is added to their contents. The recording of subsequent information parcels is made in a similar way. When the accumulator 37 is filled, a signal is generated. The buffer is full, which is fed to the output of 20;

When a request is received for reading data at the device input 17, it passes the IPI element 9 and sets the trigger 42 of the priority block 6 into one state. On the positive edge of the signal at the second generator output 40 clock pulses, the trigger 44 of the priority block 6 is set to one, the output of which is fed to the input of the address generation unit 4 and the input of the synchronization unit 11. At this time, the address inputs of the drive 37 through the switch 24 is connected to the outputs of the counter 26

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the read addresses and data from storage 37 are read. Data read from storage 37 is transferred through the switch to the information inputs of the register 30 and to one of the inputs of the comparison block 31 of the code analysis block 5. The other inputs of comparator 31 receive the output signals of register 30. If the code of the synchronization parameter in the data read from accumulator 37 is greater than the code stored in register 30, then the output signal of comparator 31 allows recording through AND 33 and OR 32 V register 30 of the new current value of the synchronization parameter. This recording is made by the output signal of the synchronization unit I1, which is delayed on the delay element 34 and formed by the driver 36. The output signal of the driver 36, which is delayed on the delay element 35, is applied to polling the elements 12 and 13. The output signal from the 12 element, i.e. the signal at the output 22 of the device is a tracking pulse read from information storage 37 and appears when a high signal level is present at the output of comparator 7, i.e. if the code stored in register 30 is equal or exceeded over the code stored in register 8. Otherwise, the output signal of the comparator unit 7 through the NOT element 14 allows the polling pulse to pass through the AND element 13 under the condition of a high signal level at the element output 15, i.e. in the absence of a signal, the buffer is empty at the output 21 of the device. The output signal of the element AND 1 3 through the element OR 9 is fed to the input of the priority node as a request for reading information. The trigger 44 set to one provides a reset via element 1-ШИ 46 of the trigger 42 and, consequently, the trigger 44 in the following way, those of the generator have 40 clock pulses. On the falling edge of the signal at the output of the trigger 44, the read address counter 26 is modified. (one is added) and counter 27 ((one is subtracted. Reading of subsequent information parcels from accumulator 37 is done in the same way. When emptying, accumulate

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The body 37 at the output of the LIVE-NE element 28 appears a high level of signal, which indicates the state of the buffer. The buffer is empty. The sum of the delay time, the signal on the delay element 39 and the pulse duration of the imaging unit 38 should not exceed the tact time of the generator 40 clock pulses. The sum of the signal delay time on the delay elements 34 and 35 and the pulse width of the imaging sensor 36 should not exceed the working tact duration generator 40 clock pulses. The sum of the delay time of the signal on the elements 34, 35 and 47 of the delay and the signal duration of the imaging unit 36 must exceed the duration of the tact of the generator 40 clock pulses. The change in the contents of register 8 in the process of reading data is made at the input 18 of the device.

Controlling the flow of information passing through a buffer storage device allows to increase the efficiency of information processing systems using the proposed device by reducing the overhead of transmitting / receiving and analyzing information for reliability.

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The buffer memory containing the memory block, the information inputs and outputs of which are the corresponding inputs and outputs of the device, the block formed address, the first output of which is connected to the address input of the memory block, the priority block the first output of which is connected to the control input the memory unit and to the first i input of the address generation unit, the second input of which is the first control input of the device and connected to the first input of the priority block, the second input of which is the second control the input of the device, the register, the first and the second elements, which, in order to increase the reliability of the device, it contains a code analysis unit, a comparison unit, a synchronization unit, the first and second OR elements, the first input of the code analysis unit is connected to the output of the memory block, the second input of the analysis block

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The codes are the third control, the device input and connected to the first input of the register, the output of which is connected to the first input of the block.

comparison, the second input of which is connected to the output of the code analysis block, the third input of which is connected to the first output of the synchronization block, the input of which is connected to the third 0 input of the address generation block and to the second output of the priority block whose third input is connected to the output of the first OR element, The first input of which is the fourth control input of the device, the second input of the first element OR is connected to the output of the second element AND, the first input of the first element AND is connected to the second output of the synchronization unit and to the first The first input of the first element is connected to the output of the comparison unit and to the input of the first element NOT; the input of the second element is NOT the second controlling output of the device and connected to the second the output of the address generating block, the third output of which is the third control output of the device, the first input of the priority block is connected to the fourth input of the code analysis block and to

5, the first input of the second OR element, the second input of which is the fifth control input of the device, the output of the second OR element is connected to the second input of the register.

0 2, The device according to claim 1, wherein the analysis code block contains a switch, a register, a comparison block, an OR element and an AND element, the first input of which

45 is the third input of the code analysis unit, the output of the AND element is connected to the first input of the OR element, the second input of which is connected to the first input of the switch and is 50 with the fourth input of the code analysis unit, the output of the 1-SHI element is connected to the first input of the register, the second input of which is connected to the switch output, the second input of which is the second input of the cd analysis block, the first input of the switch is the first input of the code analysis block and is connected to the first

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the input of the comparator unit, the output of which is to the second input of the comparator unit and is connected to the second input by the element output of the cat AND analysis unit, the output of the register is connected to the terminals.

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Claims (1)

Claim 1. A buffer storage device containing a memory unit, the information inputs and outputs of which are the corresponding inputs and outputs of the device, an address generation unit, the first output of which is connected to the address input of the memory unit, a priority unit, the first output of which is connected to the control input of the memory unit and to the first ι input of the address generation block, the second input of which is the first control input of the device and connected to the first input of the priority block, the second input of which is the second control in the progress of the device, the register, the first and second elements AND, characterized in that, in order to increase the reliability of the device, it contains a code analysis unit, a comparison unit, a synchronization unit, the first and second elements OR, the first input of the code analysis unit is connected to the output memory block, the second input of the analysis block 7236 6.codes is the third control, the input of the device and is connected to the first input of the register, the output of which is connected to the first input of the comparison unit 5, the second input of which is connected to the output of the code analysis unit, the third input of which is connected to the first output of the synchronization unit, the input of which is connected to the third 10 input block of the formation of the address and to. the second output of the priority block, the third input of which is connected to the output of the first OR element, the first input to ~ 15 of which is the fourth control input of the device, the second input of the first OR element is connected to the output of the second AND element, the first input of the first AND element is connected to 20 to the second output of the synchronization unit and to the first input of the second AND element, the output of the first AND element is the first control output of the device, the second input of the first AND element 25 is connected to the output of the comparison unit and to the input of the first element NOT, the input of the second element is NOT the second control output of the device and connected to the second output of the address forming unit 30, the third output of which is the third control output of the device, the first input of the priority block is connected to the fourth input of the block code analysis and to 35 to the first input of the second OR element, the second input of which is the fifth control input of the device, the output of the second OR element is connected to the second input of the register. 40 2. The device according to claim 1, about t πη- 4 in that the code analysis unit contains a switch, a register, a comparison unit, an OR element, and an And element, the first input of which 45 is the third input of the code analysis unit, the output of the AND element is connected to the first input of the OR element, the second input of which is connected to, the first input of the switch and is -. 50 with the fourth input of the code analysis unit, the output of the UTI element is connected to the first input of the register, the second input of which is connected to the output of the switch, the second input of which is the second input of the code analysis unit, the first input of the switch is the first input of the code analysis unit and connected to the first the second input of the comparison unit and is the output of the analysis unit co ^: DOV. the input of the comparison unit, the output of which is connected to the second input of the AND element, the output of the register is connected to fi 8. 2 FIG. 3 of FIG. H FIG. 5