SU1261010A1 - Buffer storage - Google Patents

Abstract

The invention can be used to coordinate the transmission rate when entering data from sources of multi-channel measurement information into a system for collecting and processing information. The essence of the invention is to increase the information capacity of the device by providing the ability to reduce the current data redundancy of some measurement channels. The address part (channel number) of each information parcel is compared with the analogous part of the previous parcel and, if they are equal, the additional memory block is addressed to the address equal to the address part of the information parcel. When reading from the additional memory block of the zero data bit, a parameter is written to the main memory block without modification of the address of the address. 3 il. HS 05

Description

The invention relates to computing technology and can be used in the construction of buffer storage devices (RAM) in systems for collecting and processing measurement information.

The purpose of the invention is to increase the information capacity of the device.

 FIG. 1 shows a block diagram of the proposed device; in fig. 2 shows a block diagram of the memory block; in fig. 3 - block diagram block diagram.

The buffer memory contains a memory block with information inputs 2 of the first group, 3 second groups and information outputs 4, the first counter of the 5 address, the second counter of the 6 address, reversible counter 7, the element OR - NOT: 8, the first 9, the second 0 outputs control, first 11, second 12 elements AND, trigger 13, first 14, second 15 registers, synchronization unit 16, NOT element 17, OR element 18, additional memory block 19, comparison unit 20, second 21, third 22 control inputs, third control output 23. first control input 24.

The memory unit 1 comprises an accumulator 25, AND-OR elements 26, a NOT element 27, a delay element 28 and a pulse shaper 29.

The synchronization unit 16 comprises first 30, second 31, third 32 delay elements, first 33 and second 34 pulse shapers.

As an additional memory block 19, a permanent storage device can be used, in which cells by addresses that uniquely correspond to the address part of information packets, zero bits are written for those channels whose data allow for reductions in current redundancy, n unit bits for those channels, data which do not allow reductions in current redundancy.

The device works in the following way.

Before the start of operation, the signal at input 24 counters 5-7 are set to the zero state.

In the recording mode, information to the device input comes in the form of words containing an address tag (channel number), which is present at the device inputs 3, and a parameter that is present at the device inputs 2, accompanied by a recording clock signal at the device input 21. On the leading edge of the signal at the input 21 of the device, the channel number is written to register 14, and the previous contents of register 14 are written to register 15. A bit of information is read from memory block 19 recorded but the address is equal to

five

0

five

five

0

 the contents of register 15, which is fed to the information input of the trigger 13. The clock signal delayed by the delay element 30 of the synchronization unit 16, is set in the corresponding state of the triplex S3. At the same time, the comparison unit 20 compares the contents of the registers 14 and 15. (The content of the first counter 5 of the address and the reversible counter 7 is increased by one by the falling edge of the signal at the third output 6jiOKa 16 of the sync clock, i.e. the write sync signal, the last successive element. msnt 30 delay and shaper 33 in the following cases: when the signal is high at the output of the OR element — NOT 8, i.e. at the “Buffer fi” state with different contents of the registers 14 and 15, i.e. output G) lock 20 comparison; with equal content registers 14 and 15 and a high level of the trigger signal 13.

The allocation of AvSDs with, 1 tea is made by elements 11 and 2 and e; 1; OR 18. (The signal at the output of the former 33, pass the delay element 31, enters the input | of the memory 1 of the memory 1 and connects through the element FiH 27 to the address inputs the accumulator 25 through the AND.OR element 26 bits of the first counter of the 5 address of the address, with the C4), the current address for the fox is formulated. At this address, the information present on the inputs 2 and 3 of the device is recorded in the accumulator 25 by a signal on the output of the NOT element 27, the delay element 28 delayed by the iia, and formed by the driver 29. next-to-second (| yormatio iiociJ. IoK) - izdes dits similarly. Record n BZU lipo- leads to a low signal level at the second output of the control, 1 device, i.e. 1FI 1 ulvol. The value of the most significant bit of the reversible counter 7 (the width of the counter 7 per unit makes the counter of the counters 5 and ()). The high vpoBCHfj signal on the output 10 of the device indicates the state of the Eufer is full.

With 1 shadow {- information C: the reading reading at input 22 of the device is input to input 1 mirovats ;; 34 of the K block), K (the horizontal one; 1t of the signal generates a pulse, which modifies the contents of the second address counter 6 (adding a chip) and reversing counter 7 (subtracting the hypothesis). - l 25, to the address inputs of which at this time is 11doc; | 1th through e, smsnth AND-OR 26 output bit signals; 1y of the second counter of address 6. S1 ial on the output line 23 of the device, Ie delayed by the delay element 32, the shaper signal 34. is the impulse to accompany the read un with |: 1Ormatsii. follow

Information parcels from the LPD are made in the same way. Data reading from the device is possible at a low signal level at the first output 9 of the device control, a high signal level at the output of the OR-NOT 8 element indicates the "Buffer is empty."

Claims (1)

Invention Formula A buffer memory containing a memory block, the information inputs of the first and second groups of which are information inputs of the device, the information outputs of which are the information outputs of the memory block, the address inputs of the first and second groups of which are connected to the outputs of the first and second address counters , a reversible counter, the outputs of which are connected to the inputs of the OR-NOT element, the output of which and one of the outputs of the reversible counter are respectively the first and second control outputs The first element, whose output is connected to the first inputs of the first address counter and reversible counter, the second element, the trigger, the output of which is connected to the first input of the second element, and the second inputs of the address counters are connected to the third input of the reversible counter. device input, characterized in that, in order to increase the information 0 five the device’s capacity, it contains the first and second registers, a comparison unit, a synchronization unit, a NOT element, an OR element, an additional memory block whose inputs are connected to the outputs of the second register and the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the outputs of the first the register and the information inputs of the second register; the control inputs of the registers are connected to the first input of the synchronization unit and are the second control input of the device, the third control input of which is the second input the synchronization unit, the first output of which is the third control output of the device, the second, third, fourth, fifth outputs of the synchronization unit are connected respectively to the first trigger input, the first input of the first And element, the first input of the second address counter and the second input of the reversible counter, the input of the memory unit, the information inputs of the second group of which are connected to the information inputs of the first register, the output of the comparison unit is connected to the second input of the second element AND, the input element NO, output The elements of the OR-NOT element, the second element AND, the element are NOT connected to the inputs of the OR element, the output of which is connected to the second input of the first element AND, the output of the additional memory block is connected to the second trigger input. VU2.3