SU1566336A1 - Device for information output - Google Patents

Abstract

The invention relates to computing and can be used to output command or indicator information. The aim of the invention is to expand the scope by increasing the size of the output information. The device contains a decoder 1, bus 2 addresses, bus 3 data, synchronization input 4, element 5, control input 6, register 7, reset input 8, memory block 9, delay element 10, counter 11, information 12 and control 13 exits. The device provides a reduction in the memory of the control computer, as well as the time for information output, and can be used in software systems for controlling machine tools and robotic complexes. 2 Il.

Description

1

The invention relates to computing technology and can be used to output command or inikator information.

The purpose of the invention is to expand the scope of application by increasing the probability of the output information.

FIG. 1 shows the function. The circuit diagram of the device; 2 - JQ belt pattern of operation of the device.

The device contains a decoder 1, inputs (buses) 2 address, inputs (tires) 3 data, synchronization input 4, AND 5, control input 6, register 15 7, reset input 8, memory block 9, delay element 10, counter 11, information 12 and control 13 outputs. The device works as follows .20

When the device is turned on by the Reset signal, arriving at input 8 at the reset input of counter 11, its contents are set to O and the next sync signal arriving at 25 input 4 to the clock input of counter 11, a pulse appears at its return transfer output, incoming to the installation of the installation in О register 7 and dumping information output 12 of the arrangement.

In block 9 of the memory, information words are formed with a length of NK + .L bits, with K bits being the actual controlling or indicator, and the L bits is the value of the information output time. The values of K and L are chosen based on the requirements for specific applications of the device and are determined by the size 0 of the output information and the time intervals of the output. The output of the corresponding information word to the output of the device and the simultaneous setting of the time of the information is carried out according to the number of the word e5 supplied from the active computer device at the input 3 of the device data. For this, the processor sets to 2, the input 2 of the address of the device, the output of data 3 / course is the number of output memory from memory block D. At the output of the decoder 1, a signal 1 appears, which is fed to the first input of the element And 5. On a signal output supplied According to input 6 to the second input of the element 5, the output appears signal 1, which arrives at the control input of the memory block 9. At the output of the memory block

The values of the output information and the output time appear, respectively, at the information inputs of the register 7 and counter 11. From the output of the element 5, the signal G through the element 10 of the delay required for the signal delay for the time of setting the information at the output of the memory block 9 comes to control inputs of the register and the counter, made a record in them. Information output 12 sets the value of the output information. Under the influence of the signals supplied at input 4 to the decrementing input of counter 11, the contents of the counter decrease and after a specified time interval, a pulse arrives at its reverse transfer output, arriving at the reset input of register 7 and resetting it at A. Impulse appearance at the control output 13 devices signal to the system about the end of the output information.

Claims (1)

Isoreteni formula A device for outputting information, comprising a decoder, whose inputs are the address inputs of the device, a counter, the clock input of which is the synchronization input of the device, the AND element, the second input of which I is the control input of the device, the register whose outputs are information outputs of the device, characterized in that, in order to expand the scope of application by increasing the size of the output information, a memory block and a delay element are inserted in it, the output of which is connected to the recording inputs of the a gistra and a counter whose installation input is O, which is the device reset input, and the output is the device control output and connected to the register reset input, the information inputs of which are connected to the corresponding outputs of the memory unit, the remaining outputs of which are connected to the information inputs of the counter , the output of the decoder is connected to the first input of the element I, the output of which is connected to the input of the delay element and the control input of the memory block whose address paths are connected to the information inputs of the device. s F i Z one F / J fe Zw "