SU1376075A1 - Device for input of information from two-position transducers - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control and monitoring systems for entering information about the state of two-position sensors into a control computer. The purpose of the invention is to increase the speed of the device. The device contains a pulse generator, a multiplexer, a memory unit, a reference element, three counters, seven triggers, two AND-NOT elements, five AND elements, an NOT element, a AND-NOT element block, a one-shot and an OR-NOT element. The device performs a cyclic survey of sensors. Information is entered when detecting a change in sensor state. In this case, the cyclic interrogation is terminated, the readiness signal is inserted into the control computer, the operation of the computer chatter protection circuit is started and the information is read in parallel with the operation of the chatter protection circuit. The device has an initial installation mode. 1 il. (L

Description

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The invention relates to computing and automation and can be used in automated control and monitoring systems for entering information about the state of two-position sensors into a control computer.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the device.

The device for entering information from two-position sensors contains a pulse generator 1, the first element AND-NOT 2, the first counter 3, the first element AND 4, the input 5 of the initial installation of the device, the first trigger 6, the block of elements AND-NOT 7, the second

When the initial installation mode is set, the device switches to the input 5 when a pulse (logic O) is applied. The first trigger 6 is set to one and the first counter 3 is set to the zero state. Clock pulses from the output of the pulse generator 1 through the first element AND-NOT 2, opened at the other input from the inverse output of the second, trigger 10, arrive at the counter 3, operating in the summation mode, and also through the first, element 4 to the synchronization input of the block 11 and the gate input of the fourth trigger 24, the information input of which receives a signal from the output of the block 11. At the information and control inputs of the block 11 from the output

set to logical

element 8, third element 9, second 20 and trigger 6 through elements 8 and 9, trigger 10, memory block 11, multiplexer 12, device address outputs 13, on-off sensors 14, comparison element 15, fourth AND element 16, element 17, fifth element 25 and 18, one-shot 19, third trigger 20, second counter 21, third counter 22, element OR-NOT 23, fourth trigger 24, fifth trigger 25, sixth trigger 26, seventh Trig-30 ger 27, second element IS-NOT 28, information output 29, rewriting resolution input 30, output 31 of the device readiness signal.

O - write mode O into the cell corresponding to the code set at the address inputs of block 11 from the outputs of counter 3. When writing to the last cell, logical 1 is set at all inputs of the block of AND-NOT elements 7, and the output is a logical zero pulse, which sets / flip-flop 6 to the zero state and switches the device to the sensor polling mode. At the same time on the manager

The input of the block 11 is set to logical 1 from the output of the AND 8 element (read mode), and on the information input is the signal of the state of the sensors 14 connected to the input of the multiplexer 12 corresponding to the code on its address inputs. The status information of the sensor 14 is fed to the first input of the element AND 16, through the element NOT 17 to the first input of the element AND 18, to the input of the comparison element 15, where it is compared with the contents of the corresponding cell coming from the output of block 11. If they do not match the signal at the output of the trigger 24, and therefore at the output 29 of the device, corresponds to the state of the sensor 14, and at the output of the comparison element 15, a discrepancy signal (logical 1) arises, which translates the trigger 10 into a single state. At the same time, the logical O with the inverse output of the trigger 10 blocks the passage of clock pulses through the element IS-NOT 2 k at its output, and consequently, the level

The device works as follows.

In the initial state, the logical O from the direct output of the third trigger 20 through the second inputs of the fourth 16 and the fifth 18 elements And goes to the reset inputs of the second 21 and third 22 counters and prohibits counting. Fifth 25 and sixth 26 triggers are set to the zero state and logical 28 is formed at the output of the And 28 element. The seventh trigger 27 is set to the zero state and logical O is formed at its output. The state of the trigger cells that make up the block 11 memory (dynamic dynamic storage device) after switching on the power is uncertain, therefore the device has an initial installation mode, in which logical O are recorded in the cells of block 11. After the initial installation, the device goes into op mode dew sensors.

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0 yes trigger 6 through the elements And 8 and 9 5 0

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O - write mode O into the cell corresponding to the code set at the address inputs of block 11 from the outputs of counter 3. When writing to the last cell, logical 1 is set at all inputs of the block of AND-NOT elements 7, and the output of logical zero, which sets trigger 6 is in the zero state and switches the device to the sensor polling mode. At the same time on the manager

the input of block 11 is set to logical 1 from the output of the element 8 (read mode), and on the information input a signal of the state of the sensors 14 connected to the input of the multiplexer 12 corresponding to the code on its address inputs. The status information of the sensor 14 goes to the first input of the element AND 16, through the element NOT 17 to the first input of the element AND 18, to the input of the comparison element 15, where it is compared with the contents of the corresponding cell coming from the output of the block 11. If they do not match, the signal At the output of the trigger 24, - and, therefore, at the output 29 of the device corresponds to the state of the sensor 14, and at the output of the comparison element 15, a mismatch signal (logical 1) arises, which translates the trigger 10 into a single state. At the same time, the logical O with the inverse output of the trigger 10 blocks the passage of clock pulses through the element IS-NOT 2 k at its output, and consequently, the level

logical 1, a at the control input of block 11 is the logical level O (recording mode). Logic 1 from the direct output of the trigger 10 transfers the seventh trigger 27 to a single state. Upon receipt of a code readiness signal from the device output 31, the control computer reads information from output 29 and device outputs 13, sends a sensor overwrite sensor 14 to the cell of block 11, which translates the sixth trigger 26 into a single state Logic O the inverted trigger output 26 triggers the trigger 27 to the zero state and thereby removes the ready signal from the output 31 of the device. Simultaneously with the output of the readiness signal of logical 1, the direct output of the trigger 10 is fed to the input of the one-shot 19, which produces a short pulse (logical O). This impulse translates the third trigger 20 into a single state of Logic 1 from its direct output to the second inputs of the fourth 16 and fifth 18 AND elements and allows the signal of the state of the sensor 14 to pass to the reset inputs of the second 21 and third 22 counters. If the sensor. 14 is triggered with bounce, then the counting on the reset inputs of the second 21 and third 22 counters is intermittent — each new bounce pulse nullifies the counters and the counting starts again.

Only after the end of the bounce at the reset input of one of the counters (second 21 or third 22) is a stable logical 1 established. If at the end of the bounce, sensor 14 is closed, then logical 1 (counting resolution) appears at the reset input of counter 21, and if sensor 14 open, then logic 1 appears at the reset input of counter 22. A counter that has a reset input

logical 1 is present, counts the required number of pulses and

Thus, the process pd, the processing of information, the control circuit protection from the other sensor contacts go pa and independently from each other allows processing and simulating fast processes.

its output overflows. generates real time. c logical 1 which arrives

to the input of an SHSh-NOT 23 element. A negative differential from the output of the OR-NOT 23 element transfers the trigger 20 to the zero state. Logic O from the direct output of the trigger 20 through the fourth 16 and fifth 18 elements And goes to the reset inputs of the second 21

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and the third 22 counters, zeroed them and forbids the account. At the overflow outputs of the second 21 and third 22 counters, logical O is set, and at the output of the OR-NOT 23 element, logical 1. A positive differential from the inverse output of the flip-flop 20 translates into five flip-flop 25 into the single state. From the above it can be seen that the process of receiving and processing information of the control computer and the work of the bounce protection circuit of the contacts of the sensors 14 are parallel and independent of each other. If the process of receiving and processing information ends before the end of the bounce, the contact first appears logic at the second input of the AND-NE element 28, and then at the first input of this element. Otherwise, logical 1 first appears at the first input of the NAND 28 element, and then at the second input of this element. When logical 1 appears at the first and second inputs of the NAND element 28, logical O appears at its output

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which transfers the fifth 25 and sixth 26 triggers to the initial (zero) state and passes through the second input of the element 4 to the synchronization input of the block 11 and to the reset input of the trigger 10, which is transferred to the zero state by a positive differential. In this case, the passage of clock pulses through the AND-HE 2 element is unblocked and a logical 1 is set at the control input of block 11 (read mode). Thus, the device proceeds to a further interrogation of the sensors 14. In the absence of the bounce of the sensors 14, the device operates similarly to that described.

Thus, the process of receiving and processing information of the control computer and the operation of the bounce protection circuit of the sensor contacts run in parallel and independently from each other. This allows information processing and simulation of fast processes in the

Claims (1)

Invention Formula A device for inputting information from on-off sensors, comprising a multiplexer, a memory unit, a reference element, the first element HE HEj, three counters, five AND elements, the trigger code, the block of AND-NOT- elements, the NOT element, the one-shot, the OR-NOT element and the pulse generator, the output of which is connected to the counting inputs of the second and third counters and the first input of the first AND – NE element, whose output is connected to the first input the first element And the counting input of the first counter, the outputs of which are connected to the inputs of the block of elements AND-NOT, with the address inputs of the multiplexer and the memory block and are the address outputs of the device, the output of the first element And is connected to the reset input of the second, trigger and sync - d A memory unit whose output is connected to the first input of the reference element, the output of which is connected to the gating input of the second trigger, the inverse code of which is connected to the second input of the first NAND element and the first input of the second element AND whose output is connected to the recording enable input of the block the memory, the information inputs of the multiplexer are the information inputs of the device, the output of the multiplexer is connected to the first input of the third And element, the output of which is connected to the information input of the memory block, the second input m of the comparison element, the first input of the fourth element AND and the input element NOT, the output of which is connected to the first input of the fifth element AND whose output is connected to the reset input of the third counter, the output of which is connected to the first input of the OR-NOT element, the reset input of the first counter combined with the installation input of the first trigger and is the input of the initial installation of the device, the output of the block of elements AND-NOT is connected to the reset input of the first trigger, inverse 5 0 5 o d five the output of which is connected to the second inputs of the second and third elements And, the direct output of the second trigger is connected to the input of a single vibrator, the output of which is connected to the input of the installation of the third trigger, the direct output of which is connected to the second inputs of the fourth and fifth elements And, the output of the fourth element And connected to the reset input of the second counter, by-, the stroke of which is connected to the second input of the IPI-NOT element, the installation and information inputs of the second trigger are connected to the potential unit bus of the logical unit. o, in order to increase speed, the device contains fifth, sixth and seventh triggers and a second NAND element, the output of which is connected to the second input of the first element, AND and the reset inputs of the fifth and sixth triggers, the forward outputs of which are connected respectively to the first and the second inputs of the second AND-NOT element, the element output of the OR-NOT element is connected to the reset input of the third trigger, the inverse output of which is connected to the installation input of the fifth trigger, the installation input of the sixth trigger is the enable input of the device overwriting, and The full output of the sixth flip-flop is connected to the reset input of the seventh flip-flop, the output of which is the output of the device readiness signal, the setup input of the seventh flip-flop is combined with the one-shot input, the information and fourth triggered inputs are the inverse output of the fourth trigger; erra is the information output of the device. .L I / 7 H Plpt 2 .l but At