SU1425651A1 - Extremum filtration device - Google Patents

Abstract

The invention relates to computing and can be used in specialized computing devices when processing two-dimensional data arrays, for example, in image processing. The purpose of the invention is to increase the speed. The device contains memory blocks 1-3, counters 4-6, adders 7, 8, registers 9-12, shift register 13, comparison block 14, switch 15, pulse generator 16, frequency divider 17, triggers 18-20, AND elements 21-24, OR elements 25,26, NOT elements 27, 28, one-shot 29, 30, delay elements 31, 32. When the device is in operation, a sequential view of the original array occurs, and for each element of the array - a sequential search for an extreme value in the pale aperture . The purpose of the invention is achieved by a conveyor .. processing the definition of extremes with memorization in buffer registers. The pax addresses of the array element in the aperture field and the value of this array element. 1 il. § (L

Description

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The invention relates to computing and is intended for use in specialized computing devices in the processing of two-dimensional data arrays, for example, in image processing.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the proposed device.

The device contains memory blocks 1--3, counters 5-6, adders 7 and B, registers 9-12, shift register 13, comparison block 14, switch 15, rebar 16 pulses, frequency divider 17, triggers 18-20, elements And 21-24, elements OR 25 and 26, elements NOT 27 and 28, 9DNovibrators 29 and 30, elements .31 and 32 delays, start inputs 33, initial setting 34, selection of an extremum type 35, synchronization outputs 36, completion of work 37 , information code 38.

The operation of extremal filtering, over a two-dimensional array A of pkht dimension, is as follows. For each element of array A, where I, 2-n, j 1,2-n, an ext- I remum is defined among the elements of the pxq I matrix (p, q are odd), called the aperture, with its center ajj. ; The device allows for extreme filtering of two-dimensional

; arrays for which the numbers π and m are the integer powers of two, i.e. , t "

Counter 4 has a capacity, i.e. the number of points in the aperture. Counters 5 and 6- have respectively: 1 „and 1 bits. In memory block 3, the source array A is stored, in memory blocks 1 and 2, the offset of the coordinates of the elements of the aperture matrix relative to its center. The sign bit of adders 7 and 8 is represented by two bits.

The device works as follows.

When the maximum filtering is performed, the input 35 is given a logical zero and, by the initial installation signal, input 34, which passes through the OR 25 and AND 23 elements, registers 9 to the zero state. When performing the minimum filtering, the input of logic 35 enters input 35 and register 9 is set

50

five

0

five

Q 5

Q

is in a state where units are written in all its bits.

The pulse generator 16 generates synchronization pulses, the arrival frequency of which is divided by two using a frequency divider 17.

The trigger signal on input 33 on the leading edge of the pulse from the frequency divider 17 causes the trigger 18 to be set to one and allows the pulses from the frequency divider 17 to pass through the AND 21 element (the third input of the 21 Element receives the logical unit level from the output element NOT 28).

The contents of counter 4 are fed to the address inputs of memory blocks 1 and 2, from which the offset of the coordinates of the corresponding elements of the aperture matrix are selected. These atvm offsets are added by adders 7 and 8 with the coordinates of the current value ac, located in counters 5 and 6. The calculated values are the addresses of the elements of the array aij in memory block 3.

If, when adding in any adder, the sum turned out to be negative or overflowed, then this element of the aperture matrix is located outside of the array A.

According to the pulses of the first sequence (from the output of element 21), the value of the address of the element of the array is entered in registers 10 and 11. On the pulses of the second sequence shifted by clock time, which arrive

from the output of the second bit of the shift register 3, the values of the elements of the array aij, read from the memory block 3, are recorded in the register 12. The signal from the output of the element OR 26 is stored in triggers 19 and 20. If the element is outside the array, then from the output element OR 26 receives a single signal, which is delayed by two clocks in triggers 19 and 20 and is fed to the control input of switch 13, with this value at its outputs changing by the value set at input 35, i.e. zero when searching for the maximum and maximum number when searching for the minimum. At the output of the comparison unit 14, the level of the logical unit is formed if the number at the output of the switch 15 is higher (less when searching for the minimum) than in register 9.

With the presence of this signal, no pulses of the sequence are allowed to pass from the output of the fourth bit of the shift register 13 through the AND 24 element to the synchronous input of the register 9, in which the extreme value is written. On the k-th pulse at the overflow output of counter 4, a signal is generated, according to which the one-oscillator 29 generates a pulse that enters through the element 28 at the input of the element 21, eliminating one pulse from the sequence. On the overflow pulse of the counter 4, the one-shot 30 forms a short pulse, which, after a delay by the delay element 32, arrives at the device synchronization output 36. This signal from the outputs 38 reads the first result. The pulse generated by the one-shot 30 after the delay and the delay element 31 for a time sufficient for reading the result sets the register 9 to the state determined by the signal at the input 35 of the extremum type selection. The pulse from the output of the one-shot 30 arrives at the counting input of counter 5, providing a transition to the next element of array A. After viewing all the elements of the array, the overflow signal from the output of counter 6 sets the trigger 18 to the zero state and goes to output 37 of the device.

Claims (1)

Invention Formula Extreme filtering device containing three memory blocks, three counters, a comparison block, a switch, the first register, two adders, a pulse generator, the first trigger, the first one-shot, the first delay element, four AND elements, two OR elements and the first HE element, and the device start input is connected to the information input of the first trigger, the direct output and the synchronization input of which are connected respectively to the first and second inputs of the first I element, the output of which is connected to the counting input of the first counter, Exit bits of which are connected with the address inputs of the first and second blocks of memory data outputs which o five 0 five connected to the first groups of inputs, respectively, of the first and second sum-. The outputs of the sign bits of which are connected to the inputs of the first OR element, the overflow output of the first counter are connected to the input of the first one-oscillator, the output of which is connected through the first delay element to the first input of the second OR element, the output of which is connected to the first inputs of the second and third elements. And, the outputs of which are connected respectively to the inputs of the installation of the first register in one and zero state, the outputs of the bits of which are information outputs of the device and connected to the first group of information inputs of the comparison unit, the output of which is connected to the first input of the fourth element And whose output is connected with the synchronization input of the first register, the information inputs of which are connected to the second group of inputs of the comparison unit and the output of the switch, the information inputs of the first group of which are They are connected to the control input of the comparison block Q, the second input of the second element I, the device type extremum selection input, and through the first element NOT to the second input of the third element I, the overflow output of the second counter is connected to the counting input of the third counter, the overflow output of which is the output of the operation of the device and is connected to the input of the installation of the first trigger in the zero state, the outputs of the bits of the second and third counters are connected to the second groups of inputs of the first and second su respectively Mmators, the initial setup input of the device is connected to the second input of the second element OR, which is due to the fact that, in order to improve speed, a frequency divider, second and third triggers, second, third and fourth registers, a shift register, and a second one-shot are entered into it. , the second delay element and the second element are NOT, and the output of the first element I is connected to the inputs of the synchro of the second and third registers and the second trigger and with the installation input of the first bit of the shift register, the output of the second bit of which 5 0 five ABOUT five : ff is connected to the synchronization inputs fjp.eTbero of the trigger and the fourth re- (Shchstra, the output of the pulse generator is connected to the synchronization input, | shift register and turn the frequency divider | to the synchronization input of the first trigger, the output of the fourth bit of the shift register is connected to the second input the fourth element L, the outputs of the bits of the second and third registers are connected respectively with groups of the lower and higher bits of the address input of the third memory block, whose information inputs are connected to the information inputs of the fourth rtogo register outputs ASP rows are connected to vtory- kommutato5a m data inputs, a control input of which is connected yui91y 20 and third registers. five It is connected to the forward output of the third trigger, whose information input is connected to the forward output of the second trigger, whose information input is connected to the output of the second OR element, the output of the first one-oscillator is connected to the counting input of the second counter and the input of the second delay element, whose output is device sync output, the overflow output of the first counter is connected to the input of the second single vibrator, the output of which through the second element is NOT connected to the third input of the first element I, the outputs of the mantissa first second and second adders, connected to the information inputs of the second