SU1536371A1 - Device for extremum filtration - Google Patents

Abstract

The invention relates to computing and can be used in specialized computing devices for processing two-dimensional data arrays, for example, in image processing. The purpose of the invention is to expand the functionality by providing the possibility of changing the dimensions of the aperture. The device contains a memory block 1, adders 2, 3, switch 4, comparison blocks 5, 6, 7, counters 8-11, registers 12, 13, 14, trigger 15, pulse generator 16, groups of elements 17, 18, elements AND 19 - 23, elements OR 24 - 28, element NOT 29, delay elements 30, 31, 32, pulse shaper 33, inputs for setting the length of row 34 and column 35 of the aperture, start input 36, setup initial input 37, mode selection input 38 , synchronization output 39, information output 40, end of work output 41. The operation of extreme filtering (EF) consists in determining for each element the initial a single array of extreme value in a certain neighborhood, called the aperture of the given element of the array. Before starting work, the initial array is entered into the memory 1, and the aperture dimensions are entered into registers 13 and 14. When the device is operating, the source array is sequentially scanned and for each element of this array a sequential search for an extreme value in the aperture field. The result of the ESP is generated at the output 40 of the device. 1 il.

Description

The invention relates to automation and computing and can be used in specialized computing devices for processing two-dimensional arrays of data, for example, for image processing.

The purpose of the invention is to expand the functionality of the device by providing the possibility of changing the dimensions of the aperture,

The drawing shows a diagram of the device.

The device contains a memory block adders 2 and 38 switch 4 "blocks of comparison 5 - 7 and counters 8 - 11, registers 12 - 14, trigger 15, generator of 16 pulses, groups of 7 s 18 And elements, And elements 19 - 23 elements OR 24 - 28, element NOT 29, elements 30 - 32 delays; shaper 33 pulses9 inputs of setting the length of line 34 and aperture column 35, start input 36, initial setup input 37, mode selection input 38, synchronization output 39, information output 40, output 41 of operation.

The operation of extremal filtering of children by a two-dimensional array A of dimension m xn is as follows: For each element of the array s, where i is l, 2, ..., m, j 1,2, ..., n, is determined by the extremum among the elements of the matrix p q (re q q odd) s called aperture, centered at aj „

The device is triggered. ct produce an extreme filter x .yu two-dimensional arrays9 for which the numbers ha and n are powers of two, t, e, m 2 ™, n 2, counters 9 to 10 have 1, 1 n bits, respectively, in memory block 1 the initial array A is stored. Registers 13 and 14 record the reduced dimensions p and q of the matrix-aperture (maximum displacements from the center of the apertoi) t namely p1 (p - l) / 2j q: q - 1) /, Numbers from registers 13 and i4 are transmitted to counters 8 and 11 with inversion, Counters 8 and 13 have an extra bit compared to registers 13 and 14 to represent the sign of a number. Adders 2 and 3 are made with the representation of the sign of a number in two bits.

The device works as follows.

Before operating the device, counters 9 and 10 and trigger 15 are

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ds in the zero state. When performing the maximum (minimum) filtering, the zero (single) level is applied to the input of the choice of the type of extremum, and the initial setting signal at input 37 causes all bits of the register 12 to be set to the zero state. In addition, the signal of the initial installation through the elements OR 26 and 28 sets the sign bits of the counter-s 8 and 1 1 into one state and opens groups 17 and 18 of the AND elements, permitting the writing in the counters 8 and 11 of the reverse codes of numbers recorded in the registers 13 and 14. Then, the same setup signal through delay element 32 adds one to the contents of counter 11 to correct the contents of counter 11 to ensure that exactly q rows of the aperture matrix are viewed.

After the start signal at input 36, which sets the trigger 15 in a single step, the pulses from the pulse generator 16 go through the AND 22 element to the counting input of the counter 8, the values in counters 8 and 11 go to the adders 2 and 3, respectively. The same adders also receive the values from counters 9 and 10. The values calculated by adders 2 and 3 represent the lower and upper digits of the addresses of the aperture element, centered on a, -, respectively: (i and j are recorded in counters 9 and 10) . At this address, the value that goes to the first group of inputs of switch 4 is selected from memory block 1. If the sum is negative or overflow when adding in any adder, this means that this element of the aperture is located outside the array A, On this is indicated by the signal from the output of the element OR 25e which goes to the control input of the switch 4. At the same time, the value of the current element of the aperture from the first group of inputs of the switch 4 to its output-od is not received, but is replaced by the value nym inlet 38; zero when searching for a maximum or maximum number when searching for a minimum. The comparator unit 5 outputs, via the AND 21 element, a write signal to the register of the 12th number, located at the output of the switch 4, if

this number is more (less - when searching for a minimum) of the number in register 12,

In the case when, when the next pulse arrives from the generator 16, the contents of the counter 8 coincide with the contents of the register 13, the signal from the output of the comparison unit 6 is fed to the shaper 33, which generates a pulse recording repeatedly (via delay element 31, OR element 28 and group 17 of elements And) in the counter 8 reverse code number (-p). The same pulse from the output of the delay element 31 adds one to counter 11, which provides a transition to viewing the next row of the matrix-aperture.

The output signal of the comparator unit 7 appears with the transition to viewing the last row of the aperture. After the end of viewing this line, the signal from the output of the comparator unit 6, converted into a pulse by the shaper 33, through the delay element 31 and the open element 23 forms a sync pulse at the output 39 of the device, through which the result is output from the outputs 40, as well as through the delay element 30 the register 12 is in the state determined by the signal at the input 38 of the choice of the type of extremum. The same signal from the output of the AND 23 element records the additional code 11 (-q1) into the counter 11, which prepares the device for viewing the aperture of the next element of the original matrix A. In addition, the same pulse from the output of the AND 23 element adds one to the counter 9, the transition, therefore, to the next element of the matrix A.

After viewing all the elements of the matrix A, the overflow signal from the output of the counter 10 sets the trigger 15 to the zero state and arrives at the output 41 of the terminating operation.

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Extreme filtering device comprising a memory block, two. adder, switch, first comparison block, first register, first, second and third counters, pulse generator, trigger, NOT element, four AND elements, first and second OR elements, pulse shaper, and

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the first delay element, the input of the initial installation of the device is connected to the first input of the first OR element, the output of which is connected to the first inputs of the first and second elements AND, whose outputs are connected to the inputs of setting the bits of the first register to the single and zero state, respectively; connected to the output of the third element And, the first input of which is connected to the output of the first comparison unit, the output of the pulse generator is connected to the synchronous input of the trigger and the first input of the fourth element And, the device start input is connected to the D-input of the trigger, the output of which is connected to the second input of the fourth element I, the output of which is connected to the second input of the third element I and the counting input of the first counter, the input of the device mode setting connected to all information inputs of the first switch group, the second input of the first element I and through the element NOT with the second input of the second element I, the overflow output of the second counter is connected to the counting input of the third counter, the overflow output of which is the end output operation of the device and connected to the R input of the trigger, the outputs of the bits of the second and third counters are connected to the first groups of inputs of the first and second adders, respectively, the outputs of the bits of which are connected to the groups of the low and high bits of the address of the memory block, respectively, with the second group of information inputs of the switch, the outputs of which are connected to the inputs of the first group of the first comparison unit and information inputs of the first register, the outputs of which bits are information the device’s outputs and are connected to the inputs of the second group of the first comparison unit, the outputs of the sign bits of the first and second adders are connected to the inputs of the second OR element, the output of which is connected to the control input of the switch, the output of the device synchronization is combined with the input of the first delay element with the second input of the first element a OR, characterized in that, in order to expand the functional

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the possibilities by changing the dimensions of the aceture, the second and third registers, the fourth counter, the second and third blocks of the comparison n, the AND element, the third, fourth and fifth OR elements, the second and third delay elements, and the first and second g rubs of elements And, with the groups of inputs specifying the length of the row and column of the device aperture connected to groups of information inputs of the second and third registers, respectively, the inverse outputs of the i-ro and j-ro bits of which, respectively, C ,,., 1р „J 1 , 2 j, „. ,, 1, 1р, 1, are the maximum lengths of the row and column of the aperture, respectively; are connected respectively to the ith and jth inputs of the first group, respectively, of the third third comparison block, and with leer inputs, respectively, of the 1st and th elements And, respectively, the first and second groups, the outputs of which are connected to the information inputs of the i-th and j-th bits, respectively, of the first and fourth | counters9; the outputs of the bits of which are connected to the second groups of inputs

respectively the first and second adders and respectively the second and third comparison units, the outputs of which are connected to the inputs of the pulse former and the fifth element AND, the output of which is connected to the input of the first delay element, the counting input of the second counter and the first input of the third OR element, whose output is connected with the second inputs of all elements AND the second group, the information input of the senior bit of the fourth counter

and, through the second delay element — with the first input of the fourth OR element, the output of which is connected to the counting input of the fourth counter — the output of the pulse former is connected to

the input of the third delay element, the output of which is connected to the second input of the fifth element AND, the second input of the fourth element OR and the first input of the fifth element OR whose output is connected to the information input of the high bit of the first counter and the second inputs of all elements AND of the first group, the input the initial installation of the device is connected to the second inputs

the third and fifth elements OR.

Claims (1)

The claims 50 An extreme filtering device containing a memory unit, Two · adders, a switch, a first comparison unit, a first register, a first, 55 second and third counters, a pulse generator, a trigger, a NOT element, four AND elements, a first and second OR element, a pulse shaper and the initial installation of the device is connected to the first input of the first element OR, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are connected to the inputs of the installation of the bits of the first register, respectively, in unit zero e state, the synchronization input of which is connected to the output of the third element And, the first input of which is connected to the output of the first comparison unit, the output of the pulse generator is connected to the trigger sync input and the first input of the fourth element And, the device start input is connected to the trigger D-input, the output of which is connected with the second input of the fourth element And, the output of which is connected to the second input of the third element And and the counting input of the first counter, the input of the job mode of the device is connected to all information inputs of the first group of the switch, the second input of the first element And and through the element NOT with the second input of the second element And, the overflow output of the second counter is connected to the counting input of the third counter, the overflow output of which is the output of the end of the device and connected to the R-input of the trigger, the outputs of the bits of the second and the third counters are connected to the first groups of inputs, respectively, of the first and second adders, the outputs of the bits of which are connected with the groups of the lower and higher bits of the address of the memory block, respectively, the group of outputs which is connected to the second group of information inputs of the switch, the outputs of which are connected to the inputs of the first group of the first comparison unit and the information inputs of the first register, the outputs of the bits of which are the information outputs of the device and connected to the inputs of the second group of the first comparison unit, the outputs of the significant bits of the first and second adders are connected with the inputs of the second OR element, the output of which is connected to the control input of the switch, the synchronization output of the device is combined with the input of the first ele The delay element, the output of which is connected to the second input of the first OR element, characterized in that, in order to expand the functionality by providing the ability to change the aperture dimensions, the second and third registers, the fourth counter, the second and third comparison blocks, five |> 1st element AND, third, fourth and fifth elements OR, second and third delay elements, first and second g in The groups of elements are And, and the groups of inputs for specifying the row and column lengths of the device aperture are connected to the groups of information inputs of the second and third registers, respectively, whose inverse outputs are i-ro and j-ro discharges of which, where 1 => 1.21 p, j = 1 , 2, ”.., 1 <^, Ip,; the maximum lengths of the row and column of the pert, respectively, are connected respectively with the i-th and j-th inputs of the first group, respectively, of the second) third comparison unit and with the first inputs, respectively, i-ro and -th elements And, accordingly, the first and second groups, the outputs of which are united with information inputs Accordingly, i-ro and j-ro bits, respectively, of the first and fourth counters, the outputs of the bits of which are connected to the second groups of inputs of the first and second adders, respectively, of the second and third comparison blocks, the outputs of which are connected to the inputs of the pulse shaper and the fifth, respectively AND element, the output of which is connected to the input of the first delay element, the counting input of the second counter and the first input of the third OR element, the output of which is connected to the second inputs all x AND elements of the second group, the information input of the high order of the fourth counter and, through the second delay element with the first input of the fourth OR element, the output of which is connected to the counting input of the fourth counter, · the output of the pulse shaper is connected to the input of the third delay element, the output of which is connected to the second the input of the fifth AND element, the second input of the fourth OR element and the first input of the fifth OR element, the output of which is connected to the information input of the senior level of the first counter and the second inputs all And the first group of elements, devices, initial setting input is connected to the second inputs of the third and fifth elements in OR.