SU1211727A1 - Priority device - Google Patents

Abstract

The invention relates to automation and computer technology and is intended for use in devices that perform the function of interruption. The purpose of the invention is to reduce the amount of equipment. The priority device contains two registers, four AND elements, the NOT element, and four OR elements. 1 il.

Description

The invention relates to digital technology and can be used in the common memory management units of computer systems or systems for resetting and registering information. five

The purpose of the invention is to reduce the amount of equipment of the device.

The drawing shows the priority device.

The device contains triggers 1-4 10 of the first register, triggers 5-8 of the second register, elements AND 9-12, element NOT 13, elements OR 14-17, request inputs 18-21 of the device, outputs 22-25 of the device, clock input is 26. Devices, input 27 reset the device.

The device works as follows.

Before operation, the device 20 is set to its initial state by applying a unit-level impulse device to the reset input 27, which through the OR 13-16 elements is fed to the inputs of the flip-flops 1-4 and sets them to the zero state. The zero level from the direct outputs of the flip-flops 1-4 is fed to the inputs of the flip-flops 5-8, and on the trailing edge of the sync pulse, these triggers set the zero state. Therefore, at the outputs of 22-25 - zero levels.

When prompted, i.e. unit-level pulses, to inputs 18-21, flip-flops 1-4 are set to one, and from their direct outputs to the inputs of flip-flops 5-8, unit levels are received. On the falling edge of the first synchro pulse arriving at the input 26, which through the inverter 13 also enters the clock inputs of the flip-flops 5-8, the flip-flops 5-8 are set to one. At the direct outputs, dah triggers, and consequently, at the second inputs of the elements And 9-12 - unit numbers, and on the inverse - zero. The zero level from the inverse output of the trigger 5 of the highest priority channel enters the third inputs of the input elements AND 10-12 of the lower priority channels and closes them. The following clock pulse, at input 26 passes through the element And 9 to the output 22, since the second input

This element receives a single level from the forward output of trigger 5. At the same time, the pulse from output 22 through the element OR 14 enters the reset input of trigger 1 and sets this trigger to the zero state by the leading edge. From the direct output of trigger 1, the zero level enters the trigger input 5 , and on the falling edge of the pulse, which sets the trigger edge 1 to the zero state, the trigger 5 is also set to the zero state, and the unit level from its inverse output goes to the third inputs of the And 10, 11, 12 elements. These pulses successively pass through the elements AND 10 to the output 23, the element 11 and 11, to the output 2 to the output 25, after which the device returns to the initial state.

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Claims (1)

Invention Formula A priority device containing two registers, a group of AND elements and a group of OR elements, with the single input of each bit of the first register connected to the corresponding inquiry input of the device, each output of the first register connected to the single input of the same bit of the second register, direct output of each bit The second register is connected to the first input of the element of the same name. And the groups, the second inputs of the elements And the group are connected to the clock input of the device, the element and the group are the group of outputs of the device, which is; e so that, in order to reduce the amount of equipment, the device contains a NO element, and the device’s clock input is NOT connected to the clock inputs of the second register bits, the output of each RShI group element is connected to the reset input of the same name of the first register, the inputs of the OR elements of the group are connected to the reset inputs of the device, the second input of each element of the OR group is connected to the same output of the device, the inverse output of each bit of the second register is connected to the corresponding input of all subsequent elements And groups. 2B 2G fS18 RGN jl ten eleven 21J 17 12 Compiled by M. Kudr Shev Editor N. Shvydka Tekhred T. Tulik Proofreader S. Cherni 641/53 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries N3035, Moscow, Zh-35, Raushsk nab ,, d.4 / 5 Branch ShSh Patent, Uzhgorod, Project.A, A