SU1510099A1 - Series-to-parallel conde converter - Google Patents

Abstract

The invention relates to computing and can be used in systems for collecting and processing information using the conversion of bipolar serial code into unipolar parallel code. The purpose of the invention is to reduce the redundancy of the converter. The converter contains a controller 1, a generator of 2 pulses, channels 3 transformations, each of which includes shapers of 4.5 pulses, shift register 6, code converter 7, elements 8-12 AND, triggers 13-16, decoder 17, counter 18, buffer registers 19, 20, element 21 OR, inverters 22-24, block 25 of inverters, input register 26, count register 27 and output register 28. 1 Il.

Description

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The invention relates to the field of computer technology and can be used in systems for collecting and processing information using the conversion of bipolar sequentially code to unipolar parallel code.

The purpose of the invention is to reduce the redundancy of the converter.

The drawing shows the functional code converter circuit.

The converter contains a controller 1, a generator of 2 pulses, conversion channels 3, each of which contains shapers of 4 and 5 pulses, a shift register 6, a code converter 7, elements 8-12, triggers 13-16, a decoder 17, a counter 18, a buffer registers 19 and 20, an OR 21 orb, inverters 22–24, a block of 25 inverters, an input register 26, a counting register 27 and an output register 28.

The converter works in the following way.

When the power is turned on, the generator 2 is started and the pulses begin to flow to the first inputs of the elements AND 8 and 11.

At the initial moment, in the absence of a bipolar code, at the input of the converter, which transforms the bipolar code into unipolar code, zero potentials are set at both its outputs (synchronization and data). From the synchronization output of the pre-image 7, the zero potential is fed to the first input of the element OR 21, to the input of the inverter 22, from the output of which the potential corresponding to logical 1 is set at the input S of the trigger setup 13. In the absence of frequency from the synchronization output of the converter 7 to at the pulse shaper input 4, a zero potential is established, and at the pulse shaper output 4, a potential equal to logical 1 is fed to the second input of the element And 8, being at the same time permitting for the frequency the input element And 8 from the generator 2. Thus, the pulses come from the output of the element And 8 to the counting input of the trigger 13, while the potential output of the logic O set at the input D of the trigger data 13 is overwritten at the direct output of the trigger 13 at the entrance of the selection mode S

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MA register 6 shift. The frequency from the output of the element AND 8 through the element OR 21 enters the counting input of the register 6. However, the recording of information in the register 6 does not occur, since you have-; mode boar is set to zero potential all the time. When a bipolar code arrives at the sixth input of the channel, specifically at the input of converter 7, packets of 32 pulses with 4 C pauses begin to arrive from its synchronization output, with 4 C, where L is the period of the frequency of incoming pulses. A solid pulse corresponds to 1 bit of information — logical O or logical 1. The first synchronization pulse that arrives at the input of flip-flop 13 from the top of the inverter 22, the forward output of flip-flop 13 sets the level of logical 1, which is fed to the mode select input register 6 shift. The same pulse triggers the shaper of 4 pulses, at the output of which the potential of logical O is set, prohibiting the passage of frequency from the first input of the AND 8 element to its output. At the input of the element OR 21, connected to the output of the element And 8, the logical level O is set. From the other input of the element OR 21, the first synchronization pulse from the output of the converter 7 passes to the output of the input of the shift register 6. Thus, on the leading edge of the first synchronization pulse 1, and on the mode selection input of register b, logical 1 is set and as this edge arrives at the counting input of register 6, the latter is reset to recording, i.e. The first output register bit is set to. Oh, the remaining thirty one bits is in the logical 1 state. On the falling edge of the first synchronization pulse, the first bit of information from the information output of the converter 7 to the input D of the data of the trigger 14 is rewritten to its, trigger 14, output. Thus, by the first synchronization pulse, the first bit of information is written to the trigger 14 and is reset — the register 6 is reset.

The positive leading edge of the second synchronization pulse arriving at the input of the driver 4,

the latter is restarted and at its output continues to maintain a level of logical O, which prohibits the passage of frequency from the input of the element 8 to its output. With the same positive (leading) front, the first bit of information recorded in trigger 14 and set at the data input of register 6 by the preceding synchronization pulse is recorded in the first register bit 6. In the second output bit of register 6, a logical O is set. The negative edge of the second pulse of the second bit of information is recorded in the trigger 14 and set at the input D of the data of the register 6. In the same way, the third synchronization pulse starts the shaper 4. A positive front of the third pulse to the register 6 is recorded a second bit of information, and in the negative edge trigger 14 - the third bit

Thus, every third and third

35

information. A thirty-second pulse 25 is a two-bit information word, the thirty-first bit of the de reg register 6 sets the thirty-first bit of information, and the thirty-second, last bit is written to the trigger 14. This is followed by a pause between the bipolar code bursts of duration 41), where is the synchronization frequency period.

At the input of the imaging unit 4, a zero potential is established, and from its output to the input of element B, a potential of logical 1 is received, allowing the passage of the frequency of its input to the output.

The positive edge of the first frequency pulse received from the output of the element AND 8 to the input of the element OR 21. and from the last to the counting input of register 6, the thirty second bit of information recorded in trigger 14 is rewritten into register 6 and set to the thirty second output of register 6, the thirty-third register bit is set to O. The negative front of the first pulse received from the output of the element AND 8 to the counting input C of the flip-flop 13, the output of the last is set to zero potential recorded at the input D of the flip-flop 13. Zero n potential of the output latch 13 goes to S register select mode input 6. Process pre-. education is over. Informational, read-two-bit word arriving at the sixth information input of the channel is set at the output of register 6 and set at the input of register 28. With this code, the word is accompanied by a synchronization pulse that comes from the thirty-third output of register 6. The leading edge of the specified pulse is formed After setting the thirty second bit of information, the falling edge is formed after the reset of register 6 upon the arrival of the first synchronization pulse following the set information word. The first eight bits - 40 times of the information word are decrypted using a binary-decryptor assembled on register 26, element 12, which is an expander of 8, and block 25 of inverters. Register 26, in accordance with the address set on it, generates a logical 1 level on the input group of the AND 12 element. In this case, the potential that arrives at the input of the AND 9 element is formed at the output of the 12 element, and the output of the synchronization pulse from its other input is allowed 9 and further to the fourth register entry 28. Thus, only the word whose address is set on register 26 is written to register 28. From the output of register 28, data is set at the input D of the buffer

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drew on the channel information input in the bipolar code, set at the output of register 6 in the unipolar code.

An indispensable condition for the operation of the circuit is that the frequency of the generator 2 must be such that the duration of the pulses generated by it must be much less than 47, where -f is the synchronization frequency period. In addition, the duration of the pulses generated by the shaper 4 must be greater than or equal to C so that the output of the shaper 4 with a synchronization frequency all the time has a potential that prohibits the passage of the frequency of the generator 2 from the input element And 8 per eto outputs, i.e. The pulse generator 4 must pause between the information words of the bipolar code.

Thus, each tr and a two-bit information word,

two-word information word,

arriving at the sixth channel information input is set at the output of register 6 and set at the input of register 28. In this code, the word is accompanied by a synchronization pulse, which comes from the thirty-third output of register 6. The leading edge of the specified pulse is formed after setting the thirty second bit of information, the back the front is formed after resetting the register 6 upon the arrival of the first synchronization pulse following the set informational word. The first eight bits of the information word are deciphered using a binary decimal decoder assembled on register 26, element 12, which is an expander of 8, and a block of inverters 25. Register 26, in accordance with the address set on it, generates a logical 1 level on the input group of the AND 12 element. In this case, a potential that enters the input of the AND 9 element is formed at the output of the 12 element, and the output of the synchronization pulse from the other input of the element 12 9 and further to the fourth register entry 28. Thus, only the word whose address is set on register 26 is written to register 28. From the output of register 28, data is set at the input D of the buffer

register 20. As the 4th channel input command arrives, the output of the buffer register 20 is connected to the input of controller 1 and the data from buffer register 20 is copied to controller 1. By the Reset command received to the first channel input from the controller, register 27 and counter 18 are set in O. The inverse output of the trigger 15 with the specified command records the logic level 1, and the direct output of the trigger 16 records the logic level O set at the input D of the trigger data 16. The Reset command precedes the command Pu k, t5 at which the flip-flop inverse output is set to the zero state. From the inverted output of the trigger 15 to the input of the element And 10 enters the potential, which allows the passage of a synchronization pulse coming from the output of the element And 9 to the corresponding input of the element And 10.

Thus, the input S of the flip-flop setup 16 receives a pulse from the output of the element 10. At the direct output of the flip-flop 16 a potential of logical 1 is set, which, acting on the second input of the element 11, resolves the frequency slip from its first input to the output. The frequency at the first input of the element 11 comes from the output of the generator 2. From the output of the element 11, the pulses arrive at the input of the register 27 and begin to accumulate on NOTMo. Thus, after receiving the Start command and installing the first register 6 after the Start command, the words whose address is set to register 26, time 27 starts counting, and the first synchronization pulse, which triggers the count, is entered into counter 18 from the output of the inverter 23. The second synchronization pulse, coming from register 6 after converting the second word to t with the same address, sets at the output of counter 18 a deuce code that is decrypted by the binary-decryptor 17. The level difference from the output of the decoder 17, corresponding to code 2, through the inverter 24 is fed to the input of the imaging unit 5. This difference in potential levels from the output of the imaging unit 5 an impulse is formed which, entering the input R of trigger 16, set

its direct output to the zero state, and entering the input R of the trigger 15, sets its inverse

exit to a single state. The potential from the output of the trigger 15 is fed to the input element And 10 and prohibits further passage of the synchronization pulses to the output element And 10.

The potential from the output of the trigger 16 goes to the second input of the element 11 and prohibits further passage of the frequency to the input of the register 27. At the output of the register 27, a code is generated that corresponds to the time interval between two words with one address set on the register 26. The read command arriving at the third channel input from controller 1 output,

the output of the buffer register 19 is connected to the input of the controller, and the code of the time interval set at the input of data 19 comes from the output of the buffer register 19 to the controller 1.

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Claims (1)

Invention Formula Serial-to-parallel code converter, containing a controller, a pulse generator, and in each of the conversion channels — a code converter, the first output of which is connected to the input of the first pulse generator, first to third AND elements, first to fourth triggers, a counter, the outputs of which bits are connected to the corresponding inputs of the decoder, the OR element, the first and second buffer registers, the register shift and counting register, the output of the second trigger is connected to the second input of the And element, the outputs of the buffer registers of all channels are connected and combined with. controller input, first and second whose outputs and pulses of the pulse generator are connected respectively to the R input of the counting register, the S input of the first trigger, and combined by the first inputs of the first and second elements AND of each of the conversion channels, the inputs of the converter of each conversion channel are different information inputs of the converter by the fact that, in order to reduce the redundancy of the converter, a zero potential bus, inverters, an inverter unit, a second form, pulse generator, output register, input register, fourth and fifth elements AND, the inverse input of the first trigger connected to the first input; the third element And, the output of which is connected to the S-input of the second trigger and through the first inverter - with the first input of the counter, the output of the decoder pa combined and connected to the first output of the code converter, the output of the first pulse shaper connected to the second input of the first element AND whose output is connected to the C input of the fourth trigger and the second input of the OR element whose output is connected to the C input of the shift register, the second through the second inverter and the second generators of which are connected to the 0-input; pa combined and connected to the first output of the code converter, the output of the first pulse shaper is connected to the second input of the first element AND, the output of which is connected to the C input of the fourth trigger and the second input of the OR element, the output of which is connected to the C input of the shift register, the second outputs of which connected to 0 input; mi the pulse generator is connected to the R-BXOs of the first and second triggers, the D inputs of which are connected to the zero potential bus, the output of the second element I is connected to the information input of the counting register, the output of which is connected to the information input of the first buffer register, the second output of the code converter connected to the D input of the third trigger., 20D input of the fourth trigger connected the output of which is connected to the D input of the re-bus with a zero potential, the second gistra shift, the first output of which is the input of the counter and the inputs of the first and connected to the first input of the quadruple second trigger of each channel element And, the output of which the converter is connected to the first 25 controller output, third and fourth with the second input of the third element AND and the C input of the output register, the output of which is connected to the information input of the second buffer register, C input of the third trigger, the first input of the OR element and the input of the third inverter whose codes are connected to the R inputs of the first and second buffer registers of the conversion channels, respectively. the second register, the first inputs of the input register and the inverter unit with the second inputs of the input register, the outputs of which are connected to the corresponding inputs of the fifth And element, the output of which is connected to the second input of the fourth And element, the output of the fourth flip-flop , Whose E-input and whose codes are connected to the R inputs of the first and second buffer registers of the conversion channels, respectively.