RU1815670C - Device for intermittent occurrence of data - Google Patents

Abstract

The invention relates to specialized computing devices and can be used in decoding devices operating with binary cascading block codes using inter-block data demarcation. The purpose of the invention is to expand the functionality of the device. The data de-interleaver comprises RAM, an address calculating unit, and a control unit. The address calculating unit comprises a pulse generator, a calculation subunit, a register subunit and a register. The calculation subunit comprises an address module, an offset module, and a control module. The address module contains a converter, an adder, a controlled key and a register. The biasing module contains the first and second controlled keys, the first and second AND elements, the OR element, and the delay element. The control module comprises a converter, a controlled key, a binary counter, an OR-NOT element, the first and second delay elements, as well as the first and second OR elements. 5 C.p. f-ls, 15 ill. 2 tab.

Description

The invention relates to specialized computing devices and can be used in decoding devices operating with binary cascading block codes using inter-block data deinterleaving, for example, in data receiving devices transmitting via a communication channel with interference (transmission of digital audio information in television and broadcasting, in telemechanics, etc.).

The aim of the invention is to expand the functionality of the interleaver by performing non-linear data deinterleaving with a non-constant delay difference of each previous and subsequent code in the data blocks.

The following notation is adopted in the drawings:

S is the number of data in the code data block,

i is the number of the code given in the data block, i 1,2,3, .... S;

Bi is the number of code data blocks, by which the 1st data in the code data block is delayed during data deinterleaving, while Bs 0, BI, BI Vm;

bi - the difference in the number of blocks of code data, which are delayed by the 1st and (K1) -th dan00

ate

ON 4

ABOUT

mine in the code data block, with bi 5: 2. bs "0. bi BI-Ext-1 1.

In FIG. 1 is a structural diagram of a data interleaver; in FIG. 2 is a block diagram of a control unit: FIG. 3 - address sequence forming unit; in FIG. 4 is a block diagram of an address calculator; in FIG. 5-structure block register scheme; in FIG. 6 is a block diagram of an address calculating unit; in FIG. 7 t block diagram of the address increment counting unit; in FIG. 8 is a block diagram of a correction block; in FIG. 9 is a block diagram of a pulse number analyzer; in FIG. 10 is a block diagram of a first binary counter; in FIG. 11 is a structural diagram of a second binary counter; in FIG. 12 is a timing diagram of the operation of the analyzer for receiving the number of pulses; in FIG. 13 is a timing diagram of a control unit; in FIG. 14 is a timing diagram of an address calculator; in FIG. 15 is a timing diagram of the operation of a data interleaver.

The data de-interleaver device consists of a control unit 1, an address sequence generating unit 2, the data inputs / outputs of the memory unit 3 being connected to an external bi-directional data path 4, the first input of the control unit 1 is input 5, the device is issued, the second input of the control unit 1 confirmation of device reception is input 6, while the first (clock) output of the control unit 1 is connected to the first (clock) input of the address sequence forming unit 2, the outputs of which are connected to the dual-address addresses of the memory block 3, whose non-write / read and non-sample inputs are connected to the outputs of the second (read-write) and third (storage) control block 1, respectively, whose outputs from the fourth to the seventh are outputs 7 Ready to issue, 8 ready to accept, 9 ready to enter, and 10 entered devices of the data transfer device respectively.

The memory unit 3 must provide simultaneous storage of V data, where V is the minimum required capacity of the memory unit 3, determined from the dependence:

s - I

V- Ј I I-.

The control unit 1 (FIG. 2) consists of a pulse number analyzer,

inverter 12. element AND NOT 13, elements

And 14, 15, 16, 17, 18, element 19 OR NOT,

elements OR 20 and 21 and triggers 22 and 23.

The address sequence generating unit 2 (Fig. 3) consists of a pulse generator 24, a calculator 25, a register block 26 and a register 27.

The address calculator 25 (FIG. 4) consists of an address calculation unit 28, block 29

supplying the address increment, address increment correction unit 30.

The subunit 26 of the registers (Fig. 5) consists of three groups 311,312, .... 31z-2, 32,322, ..., 32z-2, 331,332, ..., ZZz-2 - 2 registers in each group.

The address calculation unit 28 (Fig. 6) consists of a converter 34, the adder 35. The address increment counting unit 29 (Fig. 7) consists of the first and second binary counters 38i and 39, the first and second controlled keys 40 and 41, the first and the second elements AND 42, 43, the AND element 44 and the delay element 45.

Block 30 correction (Fig. 8) consists of

5, a parallel code converter, control key 47, binary counter 48, OR-NOT element 49, first and second delay elements 50 and 51, and first and second OR elements 52 and 53.

0 The pulse number arrival analyzer 11 (Fig. 9) consists of a counter 54, first and second elements And 55 and 56, a delay element 57, first and second inverters 58 and 59, and a trigger 60.

5 The first binary counter 38 (Fig. 10) of block 28 (Fig. 7) consists of n D-flip-flops

61l, 6l2, ... 61n.

The second binary counter 39 (Fig. 7) of the bias module 29 (Fig. 7) and the binary counter 0 of the chip 48 (Fig. 8) of the control module 30 (Fig. 8) consist of each of elements 62i, 622, ..., 62P, elements And 63i, 632, ..., 63n and D-flip-flops 641,642 ...., 64P.

Timing diagrams of the operation of the analyzer 11 of the arrival of the number of pulses (Fig. 12) consist of eight a, b, c, d, e, f, h timing diagrams that show changes in time of signal levels at the outputs of the elements of the analyzer 11 in depending on changes in signal levels over time at its input, and the letter symbols of the time diagrams correspond to the following names of inputs and outputs: a) the input of the analyzers 11; b) 5 direct outputs of the counter 54; c) the output of the first inverter 58; g) - the output of the first element And 55; d) - the output of the delay element 57; e) - the output of the second element 56 And; g) - the output of the second inverter 58; h) - the output of the analyzer 11 (the output of the trigger 60).

Timing diagrams of the operation of control unit 1 (Fig. 13} consist of thirteen a, b, c, d, d, e, f, h, and, and, k, l, m timing diagrams of the operation of control unit 1. Timing diagrams of operation control unit 1 (see Fig. 14) show time-varying signal levels at the outputs of control unit 1 and its elements depending on changes in signal levels at inputs of control unit 1.

In FIG. 13 letter symbols of time diagrams correspond to the following names of inputs and outputs: a) input 5 confirmation of the issuance of control unit 1; b) - input b confirmation of acceptance of control unit 1; at) -. analyzer output 11; d) - clock output of control unit 1; d) the output of the inverter 12; e) - the output of the first trigger 22; g) - output element OR NOT 19; h) - read / write output of control unit 1; i) - output storage of control unit 1; i) - output 7 is ready to issue a control unit 1; k) - output 8 is ready to receive control unit 1; k) - output 9 is ready to enter control unit 1; m) - output 10, entry of control unit 1.

Timing diagrams of the operation of the address calculator 25 (Fig. 14) consist of twelve a, b, c, d, d, e, f, h, and, k, l, m timing diagrams that show changes in signal levels over time at the outputs the calculator 25 and at the outputs of its functional elements (see Figs. 3, 4, 6, 7, 8) depending on changes in the signal level at the clock input of the calculator 25, and the letter symbols of the time diagrams correspond to the following names of inputs and outputs: a) - clock input of the calculator 25; b) - output switching block 29 (output element AND 43 block 29); C) - output change block 29 (clock input of the second counter 39 of block 29); d) - output plus block 30 (output of element 49 OR NOT block 30); d) - the output of the delay element 45 of the block 29; e) - the output of the first element And 42 block 29; g) - counting input of the counter 48 of the block 30; h) - the clock input of the counter 48 of the block 30; i) - the output of the first element OR 52 block 30; j) is the output of the first delay element 50 of the block 30; l) - group of information outputs of block 30 (direct outputs of counter 48 of block 30); m) - the second group of information outputs of block 29 (direct outputs of the second counter 39 of block 29).

Timing diagrams of the device for nonlinear data deinterleaving (Fig. 15) consist of eleven a, b, c, d, e, f, g, h, and, and, to the timing diagrams of work

non-linear data deinterleaving devices. Timing diagrams of the operation of the device for nonlinear data interleaving (see Fig. 15) show changes in time of signal levels at the inputs and outputs of the device and its blocks, as well as on the data bus. In FIG. 15 letters of the time diagrams correspond to the following names of inputs and outputs: a) data bus 4; b) - input 5 confirmation of the issuance of the device; c) - input 6 confirmation of receipt of the device; d) - clock output of control unit 1; d) - the output of block 2; e) - read / write output of control unit 1; g) - output storage of control unit 1; h) - output 7 is ready to issue devices; i) - output 8 is ready to receive the device; i) - output 9 is ready to enter the device: k) - output 10 is the entry of the device.

The nonlinear data deinterleaving device (Fig. 1) works according to the following principle: the data at the input of the nonlinear data interleaving device is supplied sequentially in time one after another on the data bus 4; The 1st data of the current data block, when, is recorded by the nonlinear data interleaver in the memory unit 3 and then is read onto the data bus 4 from the memory unit 3.

The analyzer 11 (Fig. 2.9) works as follows.

In the initial state of the analyzer 11, its counter 54 is reset to zero (low level signals are generated at all direct outputs of the counter 54), the trigger 60 is set to one, and the low level signal is relied on the output of the analyzer 11. At the same time, a high-level signal is generated at its output, and low-level signals are generated at the outputs of the first and second elements And 55 and 56, and high-level signals are generated at the outputs of the first and second inverters 58 and 59. On the leading edge of the high-level pulse signal supplied to the input of the analyzer 11, the state of the counter 54 is increased by one (the signals at the direct outputs of the counter 54 are generated in accordance with the binary representation of the number one more unit for the number corresponding to the signals at the direct outputs of the counter 54 , in its previous state), and immediately after this signal, thanks to the first inverter 58, a signal is generated at the output of trigger 60 at a level equal to the signal at its information input.

Therefore, the first change in the state of the trigger 60 will occur only after entering the input of the analyzer 11

(s-1) -ro no Ordering of high level pulse signal.

When S-ro arrives at the input of the analyzer 11 in order of counting a high-pressure pulse signal, a high level signal is generated at the output of the first element And 55, according to which, after a delay time, the counter 54 is reset to zero and the output of the first element 55 is formed low signal In this case, due to the first inverter 58, the trigger 60 is set to unity by the high-level signal at the information input and the analyzer 11 returns to its initial state. The delay time t, 3d, when the signal level at the delay element 57 is selected is selected from the condition of reliable operation of the analyzer 11 and should be as close to zero as possible.

The control unit 1 (Fig. 2, 13) operates as follows.

In the initial state of the control unit 1, the analyzer 11 is in its initial state, and the triggers 22 and 23 are reset to zero. At the inputs 5, a confirmation of delivery and 6 of a confirmation of receipt of the control unit 1 in its initial state are supplied with low level signals. Moreover, at the inverted output of the trigger 23, at the output of the OR-NOT 19 element and at the output of the analyzer 11, high-level signals are generated, and at the output of the inverter 12, a low-level signal. Therefore, it is ready to output at outputs 7, 9 is ready to enter, 10 recording and reading / writing of control unit 1 are formed of low level signals, and at its outputs 8 it is ready to receive, storage and high level signals are generated at clock output. When a high-level pulse signal arrives at input 5, a control unit 1 is issued at the output of its OR-NOT element, a low-level pulse signal is generated, and at the output of the NAND-13 element, and therefore at the clock output of the control unit 1, with a high-level signal at its first input of the AND-NOT 13 element, a low-level pulse signal is generated. On the trailing edge of the low-level pulse signal (when the signal level goes from low to high), the state of the second trigger 23 changes at the output of the OR-NOT 19 element if a low-level signal is applied to its input of forced installation to a single state, since the inverse the output is connected to the information input of the trigger 23 (and based on the trigger 23 a binary counter is organized modulo two. Therefore, in

the operating time of the high-level pulse signal at input 5 confirms the issuance of the control unit 1, a pulse signal is generated at its clock output

high level, and the storage output is a low level pulse signal. At the same time, a low level signal is formed at the output 8. At the end of the pulse signal high

0 level at output 5 confirms the issuance of the control unit 1, at its outputs 7 it is ready to issue, storage and high level signals are generated at the clock output, and at output 8 it is ready to receive 5 the low level signal does not change.

Upon receipt of a high-level pulse signal at input b, the acknowledgment of the control unit 1 at the output of the OR-NOT 19 element generates a low-level pulse signal, and trigger 22 is reset to zero if it was in the single state.

Therefore, during the operation of the high-level pulse signal at input 5, acknowledgment of receipt of the control unit 1 at its read / write output will maintain a high-level signal, but on. ready to give output 7, ready to receive 8 - low level signals will be generated. At the end of the action of the high-level pulse signal at input 6, the acknowledgment of receipt of the control unit 1 by the signal at the output of the OR-NOT 19 element, its trigger 23 will change its state (to zero) if no signal is sent to its forced-unit input high level Therefore, if the trigger 23 is reset to zero, then at the outputs 8 is ready to accept and

0 storage, high level signals will be generated, and at the output 7 it is ready to give out a low level signal.

The signals at outputs 9 are ready to enter, 10 are entered and the clock output of block 1

5, the controls do not change their low level if high-level pulse signals are input to the acknowledgment input 6 of the control unit.

In addition, taking into account the logic of work

0 analysis analyzer 11 (see Fig. 12, 9) for the time between the end of each (S-1) -ro and S-ro arrival in order of counting a high-level pulse signal to input 5 confirmation of the issuance of control unit 1, the input of the inverter 12 and at the first inputs of the AND-NOT 13 and AND 16 elements, a low level signal is generated. Therefore, in this case, the storage and 8 is ready to receive the control unit 1 at the output. High level signals are generated.

At the end of each (S-l) -ro operation, in order of counting the high-level pulse signal supplied to input 5, confirmation of the issuance of the control unit t at the first, second and third inputs of the element 17 And high-level signals are generated. Therefore, at the end of each (S-1) -ro operation, in order of counting the high-level pulse signal received at input 5, confirmation of the output of the control unit 1 is ready, at its output 9, a high-level signal is generated, on the leading edge of which the trigger 22 will be set to a single state. h

Upon receipt of input 5, confirmation of the issuance of the control unit 1 for each S-ro in order of counting a high-level pulse signal, at outputs 10, the input of control unit 1 is generated a high level signal, and at the clock output of control unit 1, the signal level does not change (low level).

Thus, at the end of the operation of each S-ro, in order to count the high-level pulse signal received at input 5, confirmation of the issuance of the control unit 1, the control unit 1 switches to its initial state. Changes in signal levels at the inputs and outputs of the control unit 1 and its main elements are shown in the timing diagrams of the operation of the control unit 1 {see FIG. thirteen).

The address calculating unit 28 (see FIG. 6) operates as follows. In the initial state of the address block 28, the signals at the outputs of the register 37 correspond to a binary representation of a number equal to one, and low-level signals are supplied to the switching and changing inputs.

On the leading edge of the high-level pulse signal, the change of block 28 arrives at the outputs of the register 37, and, meaning the outputs of the address block 28, signals are generated that are either equal to the signals at the outputs of the adder 35 of the same name, if a low level signal is input or the signals at the outputs of the same name of the converter 34, if a high level signal is supplied to the switching input of block 28. The signals at the outputs of the converter 34 depend on the signals at its inputs, and hence at the inputs of the first group of information inputs of block 28.

This relationship is described as follows.

If the signals corresponding to the binary representation of the number J are received at the inputs of the first group of information inputs of block 28, where j GN,, 2,3, ..., S-1, then the signals corresponding to the binary representation of the number are generated at the outputs of the converter 34

AJ AJ-I + o -1) bm + 1,

where AJ-I is the value of the number AJ at, and it is accepted:

A0 -1, bo 0.

The starting address of the region of the memory unit 3 for interleaving data corresponding to the number Ai.

 + (1 - 1) -0 + 1 -1 + 0 + 1 0.

At this address, the first data of the first block of code data is recorded, which is transmitted via data bus 4 (see Fig. 1) by interleaving:

Thus, the truth table of the converter 34. showing the dependence of the signals at its outputs from the signals at its inputs, will be:

Transmitter Truth Table 34

Numbers, binary representations

at the inputs of the Converter 34

1

2

3

s-1

Table 1

which correspond to the signals

at the outputs of the converter 34, depending on the signals at its inputs

At-o

 + 1

Az Aa + -2 b2 + 1

A Aj-1 + 0 - 1) bj-1 + 1

Ag-1. As-2 + (s - 2) bs-2 J 1

The signals at the outputs of the adder 35 correspond to a binary representation of the sum of numbers corresponding to the signals at the inputs of the first and second groups of information inputs of block 28.

The first binary counter 38 (FIG. 10) of block 29 (FIG. 7) operates as follows.

In the initial state, the first D-flip-flop 61 of the binary counter 38 is set to one, and all the other D-flip-flops 61J, where, 3, ..., ni, are reset to zero, and the counting input and the input of the installation to the binary unit counter 38 provides low level signals. At the same time, signals corresponding to the number one are generated on the group of direct outputs of the first binary counter 38 of block 29, and 2n1-2 on the inverse outputs.

On the leading edge of the pulse signal supplied to the counting input of the counter 38, the first D-flip-flop 611 is reset to zero, and the second D-flip-flop 612 is set to one. Thus, the state of counter 38 increased by one, and signals corresponding to the binary representation of the number two were generated at the direct outputs of counter 38.

When the next pulse signal arrives at the counting input of the counter 38, its state increases by one.

When a high level signal is supplied to the installation input to the unit of the binary counter 38, the binary counter 38 is set to its initial state.

The second binary counter 39 (Fig. 11) of the block 29 (Fig. 7) and the binary counter 48 (Fig. 11) of the block 30 (Fig. 8) works as follows.

In the initial state of the second binary counter 39 of the offset unit 29, its first D-flip-flop 64 is set to one state, and all other D-flip-flops 64J, where, 3,4, ..., n2, are reset to zero.

Moreover, at the direct outputs of the second binary counter 39 of block 29, signals corresponding to the binary representation of the number one are generated. In the initial state of the binary counter 48 of block 30, its D-flip-flops 64 j, for which j-e bits, starting with the least significant number one, are a binary representation of the number

 + 1 - bi are equal to one, are set to a single state, - and the rest are reset to zero.

In this case, at the direct outputs of the binary counter 48 of block 30, a signal0

5

0

5

0

5

0

5

0

5

The numbers corresponding to the binary representation of the number + 1 - bi.

For example, let pz 3 and bi 3.

Then, 23 + 1 - 3,610 1102 and, therefore, in the initial state of the binary counter 48 of the control unit 30, its first trigger 64 will be reset to zero, and the second and third D-flip-flops 64a and 64z will be set to a single state.

In addition, in the initial state of the second binary counter 39 of block 29 and the counter 48 of block 30, low level signals are supplied to their counter inputs and clock inputs.

Moreover, at the outputs of all elements 621,622 ..... 62P I and I 56, 63i.632, ..., 63h with the first inverse input, and, therefore, at the installation and discharge inputs of all D-flip-flops 64i. 642, ..., 64P low-level signals are formed.

On the leading edge of the pulse signal arriving at the counting input of counters 39 and 40, the state of counters 39 and 48 increased by one, similar to the operation of the first binary counter 38 of block 29 (see Fig. 10 and the description of the operation of the first binary counter 38 of block 29).

When changing the signal levels at the inputs of the forced installation of counters 39 and 40 with a low level signal at their clock input at the installation and reset inputs of all D-flip-flops 64i, 642, ..., 64n, the signals do not change their levels, because with a low signal level at the clock inputs of the counters 39 and 48 at the outputs of all its elements And 62i. 622, .... 62P, and 631.632, ... 63p with the first inverse input low level signals are generated.

If a high level signal is generated at the Jth input of forced installation of the binary counter 38 and 48, then when a high level signal is supplied to the clock input of the counter 39 or 48, respectively, a high level signal is generated at the output of its element And, and 63 j AND with the first inverse input is a low level signal, because a high level signal is supplied to the inverse input of the element 63 j AND with the first inverse input, which will form a low level signal at its output. At the same time, a high level signal is generated at the installation input of the D-flip-flop 64i, 642 ...., 64p, and a low level is generated at the reset input and the D-flip-flop 64 j is forced to one state if it is reset to zero. or will not change its state if it has been set to a single state.

If, at the kth input of forced installation of the binary counter 39 or 48, where, 2,3, .., n2 or pZ, respectively, a low level signal is generated, then when a high level signal is applied to the clock input of the counter 39 or 48, respectively, the output of its And element 62 And a low level signal will be formed, and at the output of its And 62 element with the first inverse input, a high level signal, because the low level signal fed to the inverse input of And element 62 with the first inverse input when a high level signal is fed to his second pr my entrance, on Exit member 62 and to the first inverted input of the high level signal is formed. At the same time, a low-level signal is generated at the installation input of the D-flip-flop 64, and a high-level signal is generated at the reset input and the D-flip-flop 64 is forced to zero if it was set to one, or does not change its state if it was reset to zero.

Therefore, when a high-level signal is applied to the clock inputs of the binary counters 39 and 48 at their direct outputs, signals equal to the signals at their forced inputs of the same name are generated, respectively.

Block 29 (see Fig. 7) operates as follows.

In the initial state of block 29, its first and second counters 38 and 39 are set to the state corresponding to the binary representation of the number one, and low-level signals are sent to the clock input and input plus - At the same time, the outputs of the first and second elements And 42 and 43, low level signals are generated since S 1. Therefore, a low level signal is generated at the output of the delay element 45 and, therefore, at the second input of the OR element 44. It follows that at the outputs switching and changing the block 39 at its initial state, low level signals are generated, and at the first and second groups of information outputs of the block 29, signals corresponding to the binary representation of a number equal to one are generated. On the leading edge of the high-level pulse signal supplied to the clock input of block 29, the state of the first binary counter 38 is increased by one. If in this case the signals at the outputs of the first binary counter 38 begin to correspond to the number S, then at all the diodes and at the output

of the first element AND 42, high level signals are generated.

Upon reaching the signal generated at the output of the first element And 42

5 high level, the outputs corresponding to the binary representation of the number one are generated at the outputs of the first binary counter 38, and the low signal is again generated at the output of the first AND element 42

0 level Thus, the stable states of the first binary counter 38 will vary from one to S-1 inclusive. In addition, the leading edge of the high-level pulse signal.

5 of the block 29 arriving at the clock input, when the signal is low at the second input of the OR element 44, the outputs of the second binary counter 39 will generate signals equal to the signals on the group of information inputs of the block 29 when the signal is low at its output switching. On the leading edge of the high-level pulse signal supplied to the plus input of block 29, the state of the second binary counter 39 increases by one. Moreover, if signals corresponding to the binary representation of the force are generated at the direct outputs of the second binary counter 39, then at all inputs and at the output of the second element And 43, a high-level signal is generated, which is fed to the control inputs of the first and second controlled keys 40 and 41, to the input of delay element 42 and to the output, switching unit 29 means, starting from When, at the output of the second element And 43, a high level signal is generated, at the inputs of the forced installation of the second

0 binary counter 39 sends signals equal to the signals at the direct outputs of the first binary counter 38, at the outputs of the second group of information outputs of block 29, signals equal to

5 signals at the direct outputs of the second binary counter 39, and after a time determined by the parameters of the delay element 45, at the second input of the OR element 44 and at its output, when the signal is low

0 level at its first input, a high level signal will be generated, the output of the block 29 changing, and along the rising edge of which, at the direct outputs of the second binary counter 39, signals equal to the signals at the same outputs of the first binary counter 38 will be generated, which will not correspond a number greater than S-1. Therefore, at the output of the second element And 43, a low level signal is again generated, which will go to the control inputs of the first and second controlled keys 40 and 41, to the input of the delay element 45 and to the output, switching the block 29, and after a time determined by the parameters of the element 45 of the delay, it will arrive at the clock input of the second binary counter 39 and at the output, the change in block 29.

Thus, upon the plus input of the S-ro block 29 in order of counting a high-level pulse signal, switching pulses and a change in block 29 produce high-level pulse signals at the outputs, the signal at the output changing will be delayed relative to the signal at the switching output of block 29.

Such a delay is necessary so that the signals from the corresponding inputs of the first controlled key 40 can be transmitted to the inputs of the forced installation of the second binary counter 39 before the leading edge of the high level signal arrives at its clock input. Block 30 (see Fig. 8) works as follows.

In the initial state of block 30 at the outputs of the counter 48, and therefore at the group of information outputs of the block 30 and at the inputs of the OR-NOT 49 element, signals are generated that correspond to the binary representation of the number 2PZ + 1 - bi, where pz is the resolution of the counter 48, a bi is the difference in the number of code data blocks, by which the first and second data in the code data block are delayed during deinterleaving,

where 2 bi 2p3. In addition, in the original

Transmitter Truth Table 46

Numbers That Match Signals

at the inputs of the Converter 46

at the ex

1

2

s-1

s

0

5

0

5

0

5

state of the unit 30, low level signals are supplied to its clock input and to the switching and changing inputs. At the same time, at the output of the OR-NOT element 49. and therefore at the plus output of block 30 and at the control input of the controlled key 47, a low level signal is generated, so

as 2PZ + 1 - bi 0, for 2 bi 2PZ. If a high-level signal is input to the switching input of block 30 or a high-level signal is boosted at the plus output of block 30, then signals equal to the signals are generated at the inputs of the binary counter 48 forcing the binary counter 48 by the high-level signal generated in this case at the output of the first OR 52 element the output of the converter 46, which depends, unambiguously, on the signals at its inputs, and therefore, on the signals on the first group of information inputs of the block 30. This dependence of the signals at the outputs of the converter 46 on the signal in its inputs is described as follows: if the signals corresponding to the binary representation of the number j,, 2,3, ..., 5 are supplied to the input of the converter 46, then the signals corresponding to the binary representation of the 2PZ number - bj are generated at the outputs of the converter 46, where pz is the bit count of the binary counter 48, and bj is the difference in the number of blocks of code data that je and Q + 1) -e given in the code data block are delayed by.

Thus, the truth table of the Converter 46 has the following form:

table 2

comfort signals

at the outputs of the converter 46

, 2PZ - b2 2PZ - b3

2 m bs 1

With the simultaneous presence of low level signals at the switching input and output plus the control unit 30, a low level signal is generated at the control input of the controlled key 47 and signals equal to the signals at the second group of information inputs of the block 30 are generated at the inputs of the forced installation of the binary counter 48.

When a high-level pulse signal is supplied to the clock input of block 30 at the outputs of the counter 48, signals equal to the signals at its forced inputs are first generated, and then, after a while, the parameters of the second delay element 51 are determined, a high-level pulse signal is generated at the counting input of the binary counter 48, on the leading edge of which the state of binary counter 48 is increased by one. Moreover, if the previous state of the binary counter 48 corresponded to the binary

the representation of the number 2PZ -1, then the binary counter 48 is set to the zero state and the signals at its direct inputs will correspond to the binary representation of the forces of the number zero. As soon as the binary counter 48 is set to zero, the output of the OR-NOT element 49 will generate a high-level signal, which is fed to the output plus block 30, to the input of the first delay element 50 and to the second input of the first OR element 52, the output of which with a low level signal at its first input, a high level signal is also generated.

After a time determined by the parameters of the first delay element 50, a high level signal is generated at the second input of the second OR element 53, at the output of which, at a low level signal, a high level signal is also generated at its first input, which is fed to the clock input of the binary counter 48.

On the leading edge of the high level signal supplied to the clock input of the binary counter 48, signals equal to the signals at its forced inputs are generated at the forward outputs of the counter 48.

A high level signal at the clock input of the binary counter 48 may also be formed when a change in the high level signal control module is applied to the input. The parameters of the first delay element bO are selected from the condition of stability of the operation of unit 30 and should ensure the formation of a high level signal at the clock input of the binary counter 48 after generating signals on

the outputs of the controlled key 47 when the signal level changes from low to high at its control input when a high level signal is generated at the output 5 plus of block 30. The delay in changing the signal level by the first element 50 should be as small as possible.

The parameters of the second delay element 51 are selected from the condition of stable operation of block 30 and should ensure the formation of a pulse signal at the counting input of the binary counter 48 after the formation of a high level pulse signal at its clock input and after

15 generating signals at its forward outputs along the leading edge of the signal supplied to the clock input of the binary counter 48, provided that high-level pulse signals are supplied to

0 clock input and input change block 30 at the same time (synchronously). In other words, while applying high-level pulse signals to the clock input and input, a change of control module 30 l is necessary, at the direct outputs of binary counter 48, signals equal to the signals at its forced inputs must first be formed, and then the state of binary counter 48 should increase

0 per unit. The delay in signal level variation by the second element 51 should be as minimal as possible.

After the state of the binary counter 48 changes after the formation of a high level signal at the output plus block 30 (the signals at the direct outputs of the binary counter 48, and hence at the group of information outputs of block 30, become equal signals at the outputs

0 converter 46, corresponding to a number greater than zero) at the output of the OR-NOT element 49, and therefore, at the output plus the block 30, at the second input of the first element OR 52 and at the input of the first element 50

5 of the delay, and then, at the clock input of the binary counter 48, Low signals are generated.

Thus, the zero state of the binary counter 48 is unstable,

0 and the establishment of the zero state of the binary counter 48 is accompanied by the formation of a high-level pulse signal at the output plus block 30. Moreover, from the group of information outputs

5 of block 30, signals corresponding to the binary representation of the number are generated

2PZ - bj, if the signals on the first group of information inputs of block 30 correspond to the binary representation of the number J, where L.2,3 ...., 5-1.

Block 26 registers (see Fig. 5) operates as follows.

In the initial state of block 26, the signals at the outputs of its registers 31 J, where, 2,3, ..., S-2 is the sequence number of register 31 in block 26 of the registers, correspond to binary representations of numbers AJ defined by the dependencies:

Aj-s-2 +1

AJ s-2 Aj + i + (S-j - 1) bs-j-i + 1,

signals at the outputs of the registers 31 J, where, 2,3, ..., s-2 - serial number of the register

32 in block 26 of the registers correspond to binary representations of the number C, defined by the dependence:

Cj S-j,

and the signals at the outputs of the registers 33, where, 2,3, ..., s-2 is the serial number of the register

33 in block 26 registers, correspond to binary representations, the number of DJ, defined by the dependence:

DJ 2PZ - bs-j, where n3 is the number of bits of the registers 33, equal to the number of bits of the counter 48 of the block 30 of the block 25 of the calculation. On the leading edge of the pulse signal supplied to the clock input of the block 26 registers, there is a shift of the signals with the input of the first, second and third groups of information inputs of the block 26 registers to the outputs of the first registers 30i, 311 and 321, respectively, the signals from the outputs of the previous registers 30j, 31 j and 32j, where, 2, ..., s-3 are the register numbers in the register groups of the register block 26, respectively, are shifted to the outputs of the following registers 30j + i, 3.1 j + i and 32j + i, respectively. In this case, the signals at the outputs of the first, second and third groups of outputs become equal to the signals that were at the outputs of the registers 305-z, 318-z and 325-z before the arrival of a high-level pulse signal to the clock input of the block 26 of the registers. Block 26 registers can be implemented on the basis of, for example, RAM.

The calculator 25 (see Fig. 4, 14) works as follows.

In the initial state of the calculation unit 25, its blocks 28, 29 and 30 are in their initial states, respectively (see Figs. 4, 6, 7, 8, 14). In this case, on the first, second and third groups of information inputs of the computing unit 25 are formed

,;

10

fifteen

twenty

25

thirty

35

40

45

fifty

55

signals corresponding to binary representations of a number, respectively, one and

 - bi + 1, at the outputs switching, changing the offset unit 29 and at the output plus the control unit 30, low level signals are generated, and signals corresponding to the binary representation of the number one are generated at the first groups of information inputs of the address unit 28 and unit 30. On the leading edge of a high-level pulse signal supplied to the clock input of the computing unit 25, and hence to the clock inputs of the blocks 29 and 30. signals with the input of the second and third groups of information inputs of the calculation unit 25 are transmitted to the outputs of the same name from the second and third groups of information outputs, respectively (see Fig. 4, 7, 8). At the same time, at the output, a change in block 29, and hence at the inputs, a change in blocks 28 and 30, a high-level pulse signal is generated. On the leading edge of the high-level pulse signal input to the change in block 28, the outputs corresponding to the binary representation of the sums corresponding to the signals at the inputs of the first and second groups of information inputs of block 28 are generated at the outputs of the first group of information outputs of block 28 (see Fig. 4 , 6). On the leading edge of the pulse signal arriving at the input, a change in block 30 (see Figs. 4, 8), the signals at the outputs of the counter 48 by the signal at its clock input will become equal to the signals at the inputs of the forced installation of the counter 48, and after a time determined by the parameters of the second delay element 51 of the control unit 30, the state of the counter 48 of the unit 30 will increase by one. Therefore, the signals at the outputs of the third group of information outputs of the calculator 25 after applying a high level pulse signal to its clock input will correspond to the binary representation of the number equal to the number corresponding to the signals at the inputs of the third group of information inputs of the calculator 25, increased by one. Moreover, if the number corresponding to the signals at the outputs of the third group of information outputs of the calculator 25 becomes equal to the number S, then the output plus block 30, and therefore, the output plus block 29, a high-level pulse signal is generated at the leading edge of which counter 39 of block 29 (see Fig. 4, 7) is increased by one, and the signals at the outputs of the second group of information outputs of calculator 25

will correspond to the binary representation of the number equal to the number corresponding to the signals at the inputs of the second group of information inputs of the calculator 25, increased by one. If the number corresponding to the signals at the outputs of the second group of information outputs of the calculator 25 becomes equal to S, then at the output, switching, and then at the output of the change in block 29, high-level pulse signals will be generated.

At the same time, on the leading edge of a high-level pulse signal generated at the output, a change in block 29, and hence at the inputs, changes in blocks 28 and 30 with a high-level signal formed at the output, switching of the mixing block 29, and hence at the inputs, switching of blocks 28 and 30, at the outputs of the first and third groups of information outputs of the calculator 25, signals are generated that are equal to the signals at the outputs of the converters 34 of blocks 28 (see Figs. 4, 6) and 43 of block 30 (see Figs. 4, 8), respectively, which the queue is uniquely dependent on the signal at the inputs of the first group of information inputs of blocks 28 and 30, respectively, and hence at the inputs of the first and third groups, respectively, block 29 outputs information.

In addition, along the leading edge of the pulse signal arriving at the clock input of block 29 (see Figs. 4, 7), the outputs corresponding to the binary representation of the number corresponding to the signals at the outputs of the first group of information are generated at the outputs of the first group of information outputs of block 29 the outputs of block 29 until the next pulse signal is fed to its clock input, increased by one.

The signals at the outputs of the first group of information outputs of block 29 will correspond to binary representations of numbers from 1 to S inclusive, but the state of the signals corresponding to the number S is unstable and they are replaced by signals corresponding to the number one.

For reliable and correct operation of the calculator 25, the parameters of the delay element 45 of the block 29 (see Fig. 4, 7, 14) and the parameters of the first delay element 50 of the block 30 (see Fig. 4, 8, 14) must ensure the formation of a leading edge a high-level pulse signal at the second input of the OR element 44 of block 29 (see Fig. 4. 7, 14), and hence at the clock input of its second counter 39, along the leading edge of the signal at the output, the switching of block 29 after the formation of the high pulse signal

level at the second input of the second element OR 53 of block 30 (see Figs. 4, 8. 14) by the signal at its output plus.

Therefore, the delay level of the signal level change at the delay element 45 of the block 29 (see Fig. 7.14) should be slightly larger than the delay level of the signal level change at the first delay element 50 of the block 30 (see Fig. 8, 14).

Block 2 (see Fig. 3) works as follows.

In the initial state of the address calculation unit 2, its calculator 25 and the unit 26 (see Fig. 3, 4, 5, 6, 7, 8, 14) are in their initial states, and the register 27 is reset to the zero state . In this case, low level signals are sent to the clock input and input 6 to confirm receipt of the address calculating unit 2.

On the leading edge of the high-level signal arriving at the clock input of block 2, at the outputs of register 27, and hence at the outputs of block 2, signals are generated that are equal to the signals at the outputs of the first group of information outputs of block 26 of the registers (the address of the address to memory block 3 changes ty)

The high-level pulse signal received at input 6 confirms the reception of the address calculation unit 2, and hence the input of the driver 24, causes the output of the driver 24 pulses, and hence at the clock inputs of the calculator 25 and 26 registers, a short high-level pulse signal. The parameters of the pulse shaper 24 should be selected so as to ensure the formation of an output pulse generator 24 of a minimum duration sufficient for the stable operation of all functional and logical elements of block 2 (changing the state of the register and counters, as well as switching logic elements).

On the leading edge of a high-level pulse signal arriving at the clock inputs of the calculator 25 of the calculation and the register block 26, the process of generating signals corresponding to the logic of the calculator 25 at the outputs of its first, second and third groups of information outputs occurs in the calculator 25, and in the block 26 of the registers a rightward shift of the signal registers stored in the block 26 of the registers in accordance with the logic of the operation of the register block 26 (see the description of the principle of operation of the register block 26 and Fig. 5).

Thus, in block 2, the processes of generating signals at the outputs of block 2 corresponding to the address are separated in time

access to block 3 and generating signals corresponding to the following addresses of access to block 3, which increases the speed of block 2.

A nonlinear data interleaver operates as follows. .

In the initial state of the device for nonlinear data interleaving, input 5 and output confirmation 6 receive low level signals, the control unit 1 and 2, and address calculation 2 are in their initial states, in memory unit 3 for all addresses from nods to V -1 inclusive, either arbitrary data or data is stored, the values of which are determined by the data de-interleaver receivers, for example, zeros, and the signal level values on the data bus 4 are not determined and can be arbitrary.

At the same time, at the outputs 7 it is ready to issue, 9 it is ready to enter and 10 the entry of the device for non-linear data deinterleaving, low level signals are generated, and at the output 8 it is ready to receive devices - a high level signal is generated. In addition, in the initial state of the nonlinear data deinterleaver, at the outputs of the address computing unit 2 and at the read / write output of the control unit 1, low level signals are generated, and at the output of the storage of the control unit 1, a high level signal is generated. The presence of the indicated combination of signal levels at the outputs of the nonlinear data interleaver indicates to the external data interleaver devices on TJ that the nonlinear data deinterleaver is not ready to output the next data on the data bus, and to devices - data sources - indicates that the nonlinear data interleaver is ready to receive the next data on the data bus 4 for deinterleaving. At the same time, according to the high level signal at the output, the storage of the control unit 1 of the memory unit 3 is in the data storage mode.

The start of operation of the nonlinear data interleaver initiates an external data source device by generating signals on the data bus 4 corresponding to the value of the first data to be deinterleaved, and then by applying a high-level pulse signal to input 5, confirmation of the output of the nonlinear data interleaver is given. nyh.

High Level Pulse Duration at Input 5 Confirmation

the issuance of a nonlinear data interleaver must be at least the minimum time necessary to write data to the memory unit 3 and is determined by the parameters of the memory unit 3.

At the same time, a high-level pulse signal is generated at the current output of the control unit 1, and a low-level pulse signal is generated at the output of the control unit 1 storage, according to which a memory is written to the memory unit 3 with a low-level signal at the read / write output of block 1 management.

In addition, output 8 is ready to receive non-linear data deinterleaver devices. A low level signal is generated. The simultaneous presence of low level signals at outputs 7 is ready to give out and 8 is ready to receive nonlinear data deinterleaver devices indicates to external devices that the nonlinear data deinterleaver is busy with its internal operating cycle and is not ready to exchange data with external devices.

At the end of the pulse signal at input 5, confirmation of the output of the nonlinear data interleaver is generated. High-level signals are generated at the output 7. I am ready to issue the devices and the signal levels corresponding to the address of the next access to memory unit 3.

In this case, the data source device must free the data bus 4.

The presence of the generated combination of signal levels at the outputs of the nonlinear data deinterleaver indicates to external devices that the nonlinear data deinterleaver is ready to give them another data interleaving, and to external devices — data sources — indicates that the nonlinear data interleaver is not ready to receive from them is another given.

Moreover, at the beginning of receiving data interleaving, external devices - receivers of interleaved data should be ready to receive not the first, but the second data of the first block of interleaved data. The value of the first data must be formed by the data receiver devices themselves according to the same rule as entering data into storage in memory unit 3 (RAM) in its initial state, because the first data received by the device is a nonlinear data interleaver for

deinterleaving will not be the first output interleaved device data. This logic of the nonlinear data interleaver allows the external interleaved data receiver devices to be inactive if there is no interleaved data extruded for them.

In order to receive the next interleaved data, the external interleaved data receiver must be ready to receive the data via data bus 4 and provide input 6 with a confirmation of the reception of the nonlinear data interleaver of a high level pulse signal with a duration not less than the minimum required signal duration at the inputs of block 3 memory to read data from the data bus 4 from it.

When a high-level pulse signal is received at input 6, a non-linear interleaving device is received at the output, the control unit 1 generates a low-level pulse signal, according to which, when a high-level signal is read / write, the control unit 1 reads the next data from memory unit 3 at the address corresponding to the signals at the outputs of block 2, and at the output 7 I’m ready to issue non-linear data interleaving devices — a low level signal is generated. At the end of the action of the high-level pulse signal at input 6, confirmation of receipt of the device for nonlinear data deinterleaving at the output 8 is ready to receive the device; a high-level signal is generated, and at the read / write output of the control unit 1, a low-level signal is generated.

In this case, the nonlinear data interleaver becomes ready to receive the next data for deinterleaving from external data source devices.

According to this logic of operation, the nonlinear data interleaver receives data for interleaving and outputs the interleaved data on the data bus 4 until it finishes receiving the next (S-1) -ro data in the current data block.

Upon completion of the reception by the device of nonlinear interleaving of data (S-1) -ro of the given by (S-1) -y pulse signal received at input 5, confirmation of the output of the device of nonlinear interleaving of data, the formation of high-level signals at outputs 8 is ready to receive and 9 I’m ready to enter nonlinear data interleaving devices that indicate to external devices - data sources that the nonlinear data deinterleaving device is ready to receive the next one, Se given in the current code data block, and to devices - transceivers ezhennyh data - that they should be ready to forced reception of data via the bus 4, followed by the high level pulse signal at the output of the nonlinear device 10 entering interleaving dennyh (strobe.).

The last Se data of the current block of code data is transmitted via data bus 4 from external devices - data sources via Sy in order of counting to a high-level pulse signal, which is fed to input 5 to confirm the output of a nonlinear data interleaving device to the input of external devices-interleaved data on the generated in the control unit 1 of the high-level pulse signal at the output 10, the input of the nonlinear data interleaver, coinciding in time with the high-level pulse signal supplied to 5 move confirmation issuance data interleaving nonlinear device.

At the end of S-ro, in order to count a high-level pulse signal, which confirms the input of a nonlinear data interleaver to input 5, it is only at output 7 that a high level signal is generated and the device becomes ready to issue another deinterleaved data to external devices- interleaved data receivers, this data being the first data of the next next current de-interleaved output code data block.

Subsequently, the operation logic of the nonlinear data interleaver will be repeated, i

A high level pulse signal at output 10, entering a nonlinear data interleaver may indicate to external devices that the last data of the current code block is being transmitted via data bus 4. In this description of the principle of operation of the device for nonlinear data interleaving, the count of pulse signals supplied to input 5 confirms the issuance of the device from one to S inclusive, then the count is again repeated from one (see Fig. 10).

After receipt of input 6, confirmation of the issuance of the nonlinear data interleaver of a certain number of pulses, the nonlinear data interleaver returns to its original state and the operation of the device is repeated.

This means that the operation of the device for nonlinear data interleaving is periodic, can continue for as long as desired, and any permitted stable state can be selected as the initial state of the device.

The above-described logic of the device for nonlinear data interleaving provides the expansion of functionality by implementing the function of interleaving data by providing arbitrary, not necessarily the same, delay differences of each previous and subsequent data in the data blocks of the code. This provides an object of the invention.

Claims (6)

1. A data interleaver containing a memory unit, characterized in that, in order to expand the functionality of the device, a control unit and an address sequence forming unit are introduced into it, the first input of the control unit is the first input of the device, the second input is combined with the first input of the address sequence forming unit and is the second input of the device, the first output of the control unit is connected to the second input of the address sequence forming unit, the second output of the control unit It is connected to the first input of the memory unit, the second input of which is connected to the third output of the control unit, the third input of the memory unit is connected to the output of the address sequence generator, the fourth, fifth, sixth and seventh outputs of the control unit are respectively the first, second, third and the fourth outputs of the device, the inputs (outputs) of the memory unit are connected to the data bus. 2. The device according to claim 1, with the proviso that the address sequence forming unit comprises a pulse shaper, an address calculator, a register unit and a register, first, second and third information outputs of the address calculator connected respectively to the first, second and third information inputs of the register block, the first information outputs of which are connected to the information inputs of the register and the first information inputs of the address calculator, the second and third information inputs of which are connected respectively to the second and third information outputs of the register block, the fourth input of which is combined with the fourth input of the address calculator and connected to the output of the pulse generator, the input of which is the first input of the address sequence generator, the clock input of the register is the second input of the address sequence generator, register outputs are outputs of the address sequencer. 3. The device according to claim 2, characterized in that the address calculator comprises an address calculation unit, an address increment calculation unit and an address increment correction unit, the first information inputs of the address calculation unit are connected to the first information outputs of the address increment calculation unit, the outputs of the calculation unit addresses, second information outputs of the address increment calculation unit and outputs of the address increment correction block are respectively the first, second and third information outputs of the address calculator, the first the information inputs of the address increment correction block are connected to the third information outputs of the address increment count block, the second information inputs of the address increment block, the first information inputs of the address increment block and the second information inputs of the address increment block are the first, second and third information inputs of the address calculator , the fourth output of the address increment counting unit is connected to the combined third inputs of the address calculation unit and the unit address increment correction, the fourth input of which is the fourth input of the address calculator and connected to the second input of the address increment counting unit, the fifth output of which is connected to the fourth input of the address calculation unit and the fifth input of the address increment correction block, the second output of which is connected to the third the input of the address increment counter. 4. The device according to p. 3, characterized in that the address calculation unit comprises a code converter, an adder, a controlled key and a register, the first information inputs of the address calculation unit are connected to the first information inputs of the adder and the inputs of the code converter, the outputs of which connected to the first information inputs of the controlled key, the second information inputs of which are connected to the outputs of the adder, the second information inputs of which are the second information inputs of the address calculation unit, the third input of which is connected to the control input of the controlled key, the outputs of which are connected to the information inputs of the register, the outputs of which are the information outputs of the address calculation unit, the clock input of the register is the fourth input of the address calculation unit. 5. The device according to claim 3, characterized in that the address increment counting unit comprises first and second binary counters, first and second controlled keys, first and second AND elements, an OR element and a delay element, direct outputs the first binary counter are connected to the combined first information inputs of the first and second controlled keys, to the first inputs of the first AND element and are the first information outputs of the address increment counting unit, the first information outputs of the second binary counter are connected to the first the inputs of the second AND element, with the second inputs of the second controlled key and are the second information outputs of the address increment counting unit, the outputs of the second controlled key are the third information outputs of the address increment counting block, the second inputs of the first controlled key are the first information inputs the address increment counting unit, the outputs of the first controlled key are connected to the first inputs of the second binary counter, the second outputs of which are connected to the second inputs of the second e element And, whose output is connected to the input of the delay element, the inputs of the first and second controlled keys and is the fourth output of the address increment counter, the first input of the OR element is combined with the counting input of the first binary counter and is the second input of the increment block addresses, the output of the first AND element is connected to the installation input in 1 of the first binary counter, the output of the delay element is connected to the second input of the OR element, the output of which is connected to the enable input of the forced installation of the second binary counter and is the fifth output of the address increment counting block, counting input the second binary counter is the third input of the address increment counter. 6. The device according to p. 3, characterized in that the address increment correction unit comprises a code converter, a controlled key, a binary counter, an OR-NOT element, the first and second delay elements, the first and second OR elements, the first information inputs of the correction unit address increments are connected to the first information inputs of the code converter, the outputs of which are connected to the first information inputs of the controlled key, the second information inputs of which are the second information inputs of the increment correction block addresses, the first input of the first OR element is the third input of the address increment correction block, the output of the first OR element is connected to the third input of the controlled key, the outputs of which are connected to the information inputs of the forced installation of a binary counter, the outputs of which are connected to the inputs of the OR element are NOT the first outputs of the address increment correction block, the output of the OR element is NOT connected to the second input of the first OR element, the input of the first delay element and is the second output of the correction block address expansion, the input of the second delay element is the fourth input of the address increment correction block, the output of the second delay element is connected to the counting input of the binary counter, the enable enable input of which is connected to the output of the second OR element, the first input of which is the fifth input of the block address increment correction, the second input of the second OR element is connected to the output of the first delay element. 01 Bl Lz Si 91 hi 02  -h b Ј L i e-i OZ99181 ЈZ g r b / ter i / . L gpf L 25 26 J Fig.Z FIG. 28 at R F 2GP J6 J7 rtJ 6 G cho 39 frj, - Щ. 7 L Fie. 8 29th Ja ", 1 thirty about t- "D u with fg / 2.77 well iftue.lZ i gs-i s 1 FIG. thirteen Fie. 74130 N u P  i w s P l u; Fig.15