SU1617443A1 - Device for transceiving data in serial code - Google Patents

Abstract

The invention relates to computing and can be used in interface devices of digital computers with external subscribers. The aim of the invention is to improve the speed of the device. A device for transmitting information by a serial code contains a transmission register 1, a decoder 2 zero, two triggers 3 and 10, an element OR 4, a counter 5, four elements AND 6-9, a delay element 11, a reception register 12, two groups 13 and 14 elements AND During operation of the device, only meaningful information is transmitted, thereby increasing the speed of information transfer. 1 il.

Description

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The invention relates to computing and can be used in interface devices of digital computers with external subscribers.

The purpose of the invention is to increase the speed of the device.

In the drawing, a device for transmitting information by a serial code has been prefixed.

. The device for transmitting information by a serial code contains a transmission register 1, a decoder 2 zero, the first trigger 3, element KS1 A, counter 5 clock pulses, first 6, second 7, third AND 8 and fourth 9 And elements, second trigger 10, delay element 11 , the register 12 of the reception, the first 13 and the second 14 groups of elements And the inputs and outputs 15-23.

The device works as follows.

The initial setup signal with inputs 23 through the OR element 4 sets the first trigger 3, the transmission register 1, the second trigger 10, the reception register 12 and the clock counter 5 to the zero state. At the first input of the fourth element M 9 the inverting potential is established from the inverse output of the first trigger. Signal Record from the device input 22, having passed the AND 9 element, records information from the device input 15 into the transmission register 1. The Start signal from the device input 21 sets the trigger 3 to one, i.e. At the first inputs of the elements, And 6 and 9 are set accordingly resolving the same and forbidding potentials. The clock pulses T1 from the input 18 of the device, having passed the element 6, arrive at the clock inputs of the transmission register 1, the reception register 12 and the counter 5 clock pulses. Each clock pulse T1 shifts the contents of transfer register 1 by one bit and the output of the transfer of transfer register 1 is information, which is fed to the serial input of reception register 12 and written to it using clock pulses T1. The shift of information in the transfer register 1 occurs as long as at least one par of register 1 is equal to one. At the same time, the 5-clock counter counts the number of transmitted0

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significant bits of information. The number of counted clock pulses is fixed to counter 5 in binary; i code.

When all bits of register 1 take a zero value, which corresponds to the transmission to the channel of all non-zero bits of information, a single signal appears at the output of the decoder 2, which allows the passage of a T2 clock pulse from the clock 19. A T2 clock pulse through AND element 7 sets a trigger 10 in a single state and allows the passage of a clock pulse TZ with the inputs 20 of the device through the element AND 8 to the first inputs of the elements And groups 13 and 14 and to the input of the element 11 delay. With the clock pulse of the TZ, all bits of information from the register 12, as well as the number of counted pulses, through the groups of elements 13 and 14, respectively, arrive at the information and control outputs of the device and then, for example, in a digital computer. The clock pulse TK through the element 11 of the delay sets the device to zero. Knowing the state of the control 17 and information 16 outputs of the device, it is possible to process the received information.

It is assumed that the clock im-. pulses T1, T2 and TZ, which are shifted relative to each other at acceptable intervals, of time, enter the device with the appearance of the Start signal.

Claims (1)

Invention Formula A device for transmitting information by a serial code containing a transmission register, the information inputs of which are the information inputs of the device, and the information outputs are connected to the inputs of the zero decoder, the first trigger, the OR element and the clock counter, in order to increase speed , the first, second, third and fourth elements of AND are entered into it, the second trigger, the delay element, the receive register, the first and second groups of AND elements, whose outputs are respectively and The informational output format of the device word, the first inputs of the first, second and third elements I vl 516 The first, second, and third clock inputs of the device, the setup input of the first trigger, respectively, is the input of the device, the direct output is connected to the second input of the first element, And the inverse output is connected to the first input of the fourth element, whose second input is The device records the input, the output is connected to the recording register of the transfer register, the first input of the OR element is the input of the initial setup of the device, the second input is connected to the output of the delay element, and the output is connected to the reset input of the first th trigger, the reset input of the second trigger, the reset inputs of the transmission register, the counter of clock pulses and the reception register, clock 74436 the input of which is combined with the clock inputs of the transmission register, the counter of clock pulses and connected to the output of the first element I, the output of the zero decoder is connected to the second input of the second element I, the output of which is connected to the installation input of the second trigger, the direct output of which is connected to the second input of the third element And, the output of which is connected to the input of the delay element and the first inputs of the elements of the second and first groups, the second inputs of which 5 are connected respectively to the outputs of a clock counter. And the reception register, the information input of which is connected to the transfer output of the transmission register, 0 ten