SU1126958A1 - Device for servicing interrogations - Google Patents

Abstract

A DEVICE FOR SERVICE OF INQUIRIES, containing a group of priority registers, a register of registers, a counter, a comparison circuit, a trigger, a pulse generator, an OR element and a group of AND elements, each group. The code inputs of the device are connected to the group of inputs of the corresponding priority register of the group, the group of inputs for the device is connected to the group of inputs of the register of the register, each output of the register of the station is connected to the first input of the element of the same name AND group, characterized in that, in order to speed up device, it contains a buffer register, a register of the number of free channels, two elements OR NOT, a group of blocks of elements AND, a block of decoders and a group of elements of the ban, and a group of information inputs of the device wa is connected with the group of input channels available register group whose inverse output is connected to the first group of inputs of comparing circuit, the output of which is connected to a general reset input buffer register and the register number of free KaHajTOB,. the direct outputs of which are connected to the inputs of the first element OR NOT, the output of which is connected to the inverse inputs of the group inhibiting elements, whose outputs are the device outputs and connected to the reset inputs of the corresponding register bits and the buffer register, the outputs of the buffer register are connected to the inputs the second element OR NOT and with the first inputs of the same name blocks of elements AND groups, the second inputs of which are connected to the direct output of the rigger section and the first inputs of the group inhibiting elements, the second inputs of Topbtx The third input of each prohibition element of the group is connected to the same output of the decoder block, whose inputs are connected to the output groups of the blocks of I. elements, the groups of inputs of which are connected to the output groups of the same name priority registers of the group with a zero trigger code, the zero input of which is connected to the installation input to the counter unit and the code of the second element OR NOT, the counting input of the counter and the single trigger input are connected to According to the output of the OR element and the start output of the device, the group of outputs of the counter is connected to the second group of inputs of the comparison circuit, the output of the second element OR is NOT the signal output of the device.

Description

 The invention relates to computing, in particular, to priority devices, and can be used in multiprocessor computing systems.

A priority device is known, which contains a register of a claim, a priority register, a control trigger, AND and OR elements, a checker, a circuit, a comparison, and a pulse generator. Usgroystzo provides a selection of the signal for service by comparing the priority codes of the received signals to the register of the quota with the contents of the counter counting the pulses of the pulse generator. At the time of the codes coinciding, the device gives a signal to service L.

A disadvantage of the known device is the low speed in selecting a group of priority requests, due to the use of a pulse generator and a counter for comparing priority codes.

Closest to the present invention is a device for servicing requests, containing a register for wok; elements AND and OR, group of priority registers, control trigger, pulse generator, reversible counter, frequency divider, group of comparison circuits. The output of the pulse generator is connected to the direct input of the AND element, the first inverse input of which is connected to the inverted output of the control trigger, the second inverse input to the output of the first OR element and to the reset input of the control trigger, the direct input of which is connected to the code of the second OR element . the inputs of which are connected to the first inputs of the AND elements of the first group, the outputs of which are connected to the installation inputs to zero of the respective priority registers, the outputs of the register of the current are information inputs and devices. In addition, the outputs of the group comparison circuits are connected to the second inputs of the AND elements of the first group, the outputs of which are connected to the inputs of the first OR element, and to the corresponding reset inputs of the register register, the outputs of which are connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the divider exit frequency, and the outputs to the counting inputs of their respective priority registers, the setup inputs of which are the input code buses of the device, and the output of the priority registers connected to the first inputs of the circuits There are no groups whose V9 inputs are input device code buses, and the outputs of priority registers are connected to the primary inputs of the group comparison circuits, the second inputs of KOTopf / iX are connected to the output of a reversible counter, the counting input of which is connected to the output of the AND element, the setting the reverse input is connected to the output of the second

 the OR element, and the subtracting input to the output of the first OR element, the output of the pulse generator is connected to the input of the frequency divider, the outputs of the AND elements of the first group are the output buses of the device.

The disadvantage of the device is low speed.

The purpose of the invention is higher device speeds.

5 The goal is achieved

the fact that the device for servicing requests, which contains a group of priority registers, the register of requests, the counter, the comparison circuit, the trigger,

0 a pulse generator, a CI element and a group of elements AND, each group of code inputs of the device is connected to a group of inputs of the corresponding group priority register,

“; a group of inputs for the wok of the device is connected to a group of inputs of the register of the wok; each output of the register of the wok is connected to the first input of the element of the same name and group, entered; a ferry register, a register of the number of free channels, two elements ГGSH-IE, a group of blocks of elements I, a block of decoders, and a group of elementals of the city of pret, and a group of information

5 inputs of the device are connected to the group of inputs of the register of the number of free channels, the group of inverted Eigiadov of which is connected with the first group of Ehodov of the comparison circuit; Vyhg.d which is connected to the insults. reset the buffer register and peri icTpa of the number of free channels, the straight lines of which are connected to the strokes of the first OR-NOT element, the output of which is connected to the inverse px (1

the inhibit elements of the group, whose paths are outputs of the device and are connected to the reset inputs of the corresponding register bits of the request and the buffer register, the outputs of the buffer register are connected to the inputs of the second element OR NOT and the first inputs of the blocks of the same name AND group, the second inputs of which are connected to the direct output of the trigger and the first inputs of the prohibition elements of the group, the second inputs of which are connected to the output of the pulse generator, the third input of each prohibition element of the group is connected to the same output of the block decryptors, the inputs of which are connected to groups of outputs of blocks of elements AND groups, groups of inputs of which are connected to groups of outputs of the same name priority registers of the group, the second inputs of elements And groups are connected to the zero output of the trigger, the zero input of which is connected to the installation input to the unit of the counter and to the output of the second of the OR-HEj element, the counting input of the counter and the single trigger input are connected respectively to the output of the OR element and to the device start-up output; the group of meter outputs is connected to the second group of inputs to comparison circuits, the output of the second element OR is NOT the signal output of the device. The drawing shows a block diagram of the device. The device contains a register 1 request, a group of inputs 2 a request, a group of elements I 3, a buffer register 4, a group of priority registers 5, a group of blocks 6 And elements, a group of outputs 7, a block 8 of the deviphthors signal output 9, register 11 of the number of free channels, group of information inputs 12, comparison circuit 13, counter 14, element OR 15, impulse generator 16, element OR-NOT 17, element 18, trigger 19, code input groups 20, start input 21. When the number of quotes in register 4 exceeds the number of free channels in register 11, there is always a single signal at each of the outputs of the OR 15 element at each step of allocating the priority request, allowing the counter 14 to continue to operate continuously. After selecting the priority signal for the last channel, the comparison signal from the output Circuit 13 Comparison 1 8 will reset the registers 11 and 4 to the zero state. At the same time, at the output of the OR-NOT 17 element, there is a single signal that will prevent the output of signals through the elements 10. Zero signals from the outputs of the register 4 when utstvuyut all the inputs of OR-NO element 18, a single output signal which establishes a control trigger 19 in a state of zero, and the down counter 14 - e y in nichnoe and bus 9 will go into a computer as signal.agotovnosti to work in the next cycle. When the number of the request in register 4 is less than the number of free channels in register 11, after selecting the last application, all the inputs of the element OR NOT 18 will have zero signals. A single signal from the output of the element OR-IE 18 acts in the same way as above. The device works as follows. Before the start of the operation cycle, the registers 1-, 4, 11 and the trigger 19 of the control are set to zero states, and the unit one is the readout counter 14 (not shown). After that, groups of inputs 20 to the inputs of priority registers 5 receive priority codes that determine the priority of the respective subscribers. The group of inputs 12 in register 11 receives the code of the number of free channels. At the output of the OR-NOT 17 element, a zero signal is generated, allowing the elements 10 to operate. Since the trigger 19 is in the zero state, the And 3 elements are opened with a single signal from the zero output of the trigger 19, and the blocks of the 6 And elements and the 10 are closed a zero signal from the direct trigger output 19. Saiipocsi from subscribers for a group of inputs 2 are received in register 1 and copied to the corresponding bits of buffer register 4. The device starts up with a START signal coming to the control input 19 of the trigger. After the flip-flop 19 is set to one, the transfer of incoming quotes to register 4 is blocked, which captures the received quotes in this service cycle. After that, the inputs of block 8 through 5 blocks 6 are transmitted only to those priority codes from priority registers 5, for which they are recorded in register 4, and the remaining inputs of block 8 will have zero codes. Block 8 decrypts the most priority code and at its corresponding output 9, a single signal is recorded, which is equal to the passage of a pulse from the generator of 16 pulses through the corresponding elements 10 to the corresponding output 7 and further to the computer, where this subscriber is received for service. In addition, this signal will set the corresponding bits of registers 1 and 4 to the zero state, thus excluding the selected request from the queue, and through the OR 15 element will go to the counter input of the counter 14, reducing its content by one. In block 8, the most priority code from the remaining ones is deciphered, since the transfer of the previously selected code is blocked by the register register 4 set to zero in the previous step. In this case, a single signal will occur at the other output of block 8 and the next pulse from generator 16 is transmitted through the corresponding prohibition element 10 to the corresponding output 7. In the future, the operation of the device will be similar until then. 58 until the contents of counter 14 become equal to the code on the inverse output: register 11 in the comparison circuit 13. The output signal of the circuit 13 sets the registers 11 and 4 to zero. At the same time, at the output of the OR-NOT 17 element, a single signal is generated that closes the prohibition element 10 of the first group on the inverse input. At the output of the element OR NOT 18, a single signal will appear, which will set the trigger 19 to the zero state, and the subtractive counter 14 to the single state and output 9 as a ready signal will go to the computer. For a single signal from the zero output of the trigerra 19, the reception of the request from register 1 to the buffer register 4 is allowed for the next cycle of the device operation. The next cycle of the device operation will begin after the reception in the register 11 of the code of the number of free channels. If necessary, other codes can be transferred to priority registers 5 to change the priority to subscribers. After that, input 21 receives the START signal, which determines the new cycle of the device operation. The selection of the priority code in block 8 is combined in time of the work of the detracting counter 14 by the next pulse of the generator 16.

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Claims (1)

DEVICE FOR SERVICE OF REQUESTS, containing a group of priority registers, a register of applications, a counter, a comparison circuit, a trigger, a pulse generator, an OR element, and a group of AND elements, with each corpse, pa of the device code inputs connected to the input group of the corresponding group priority register, input group applications of the device is connected to a group of inputs of the register of applications, each output of the register of applications is connected to the first input of the same element AND group, characterized in that, in order to improve the performance of the device, it holds a buffer register, a register of the number of free channels, two OR-HE elements, a group of blocks of AND elements, a block of decoders and a group of inhibit elements, the group of information inputs of the device connected to the group of inputs of the register of the number of free channels, the group of inverse outputs x <connected to the first a group of inputs of the comparison circuit, the output of which is connected to the inputs of the general reset of the buffer register and the register of the number of free channels. · direct outputs of which are connected to the inputs of the first OR-NOT element, the output of which is connected with inverse inputs of the ban elements of the group, the outputs of which are the outputs of the device and connected to the reset inputs of the corresponding bits of the application register and the buffer register, the outputs of the buffer register are connected to the inputs of the second element OR NOT and to the first inputs of the same blocks of elements AND groups, the second inputs of which are connected with direct exit Q -Trigger and with the first inputs of the <g group inhibit elements, the second inputs of which are connected to the output of the pulse generator, the third input of each element of the ban group is connected to the same output of the decoder unit, the inputs of which are connected to the output groups of the blocks of elements of the I. group the input groups of which are connected to the groups of the outputs of the same priority registers of the group, the second inputs of the elements and groups are connected to the zero output of the trigger, the zero input of which is connected to the installation input to the counter unit and to the second output of the OR-NOT element, the counting input of the counter and the single input of the trigger are connected respectively to the output of the OR element and с. the output of the start of the device, the group of outputs of the counter is connected to the second group of inputs of the comparison circuit, the output of the second element OR is NOT a signal output of the device.