SU602936A1 - Code-to-pulse number converter - Google Patents

Description

cops AND 2 transfers, elemeiton AND 3, 4, i.io cops OR NOT 5, the first and second i-groups of the elements 6 and 6, which form in each discharge of the counter the main and auxiliary triggers. In addition, the device contains a switch trigger 7, a ban trigger 8 and an output element 9. The bus 10 unit information and bus 11 zero information connected to the inputs of elements 6 of the buffer zero trigger of the counter, the bus 12 first clock pulses connected to the inputs of elements 4 , 6 main triggers of all bits of the counter, to the inputs of the switching trigger 7 and output element I 9, and the bus 13 of the second clock pulses are connected to the inputs of elements And 4, 6 auxiliary triggers of all bits of the counter and to the inputs of the trigger Ditch 7, 8, single output 14 of switching trigger 7 is connected to the inputs of all elements AND 4 of the counter, except elements of the main zero-discharge trigger, and to the inputs of the inhibit trigger 8, the output element And 9, and zero output 15 of the switching trigger 7 is connected to the inputs of all elements I6, and the output 16 of the element And 2 is connected to the input of the trigger 8 prohibition, liHa "Reset is connected to the inputs of the elements And 3 and the trigger 7, 8, and P1ina" The output is connected to the output of the output element And 9.

Before sending the input code through the bus, the Reset signal arrives and sets counter 1, switch trigger 7, inhibit trigger 8 to its initial state. In this case, the zero bit of the counter 1 is set to the state "1, the remaining bits to the state" O, the switching trigger 7 is set to the state "O and its zero output 15 arriving at the third inputs of the elements 6 and 6, switches the counter 1 into the receive mode of the sequentially received code, simultaneously the single output 14 of the switching trigger 7, entering the third inputs of the AND elements 4, prohibits the pulse counting mode and closes the input of the inhibit trigger 8 and the output element AND 9, with the other input presenting the output element AND 9 yuschy level with the trigger 8 prohibition. The clock pulses arriving at the buses 12, 13 receive also the shift information arriving at the tires 10, 11, which is recorded in the counter 1.

At the same time, the shift < 1 > (liquidating bit), entered in the zero digit of the counter, is made Thus, when all the bits of the incoming information are snapped into counter 1, eliminating the bit on the falling edge of the first clock cycle, the state of the trigger switch 7 changes to the opposite type, which will cause the counter 1 to switch from the information reception mode to the pulse counting mode and open the inputs of the 8 prohibition trigger and output element AND 9. In this case, the first stroke, simultaneously arriving at the input of counter 1 and to the input of output element AND 9, will pass through the “a slot” Exit before the counter 1 overflows.

As soon as the number of driving pulses reaches a digit that is numerically equal to the return value of the code, the code entered in counter 1, the counter will overflow, and a transfer signal will appear at its output, which, when it enters the inhibition trigger 8, changes its state by the second clock the opposite and thus closes the output element And 9 and stop issuing output pulses. Before submitting a new code parcel, the signal "Reset is received and the conversion process will proceed as described above.

The proposed device provides the ability to supply information by a serial code, while in the prototype it is supplied by a parallel code. In connection with this, the proposed device in comparison with the known one has significantly less input

tires, the number of which does not depend on the width of the input code.

Claims (2)

1. USSR author's certificate number 415658, cl. G06 F 5/04, 1971. 2. Ismailov M. Yu. Automatic systems and devices with stepper motors. Ed. “Energie, M., 1968, p. 118-119.