SU982036A2 - Device for selection of object images - Google Patents

Description

one

The invention relates to automation and can be used in systems for the automatic analysis of flat images in biology, metallography and microelectronics, in particular, for controlling photomasks of IC crystals, printed circuit boards, etc. in appearance.

According to the main author. St. N 911569 knows a device for selecting images of objects containing a first delay element connected with a scanning unit, with one input of the first element AND, another input of which is connected to the scanning unit, and with one input of the second element and, a counter connected with the first element And and with an OR element, one input of which is connected to the first delay element, a closed area detector, whose inputs are combined with AND elements and the first delay element, and the output

connected to the OR element, and the second (Delay element connected to the second AND element and to the first delay element. Detector of closed areas consists of selections) a connected to the control unit and OR-NOT elements of the counter connected to the third element ORINE, the inputs of which are connected to the first and second elements OR-NOT and connected in series to the first switch, the inputs of which are connected to the control unit, the first shift register, the output of which

15 is connected to the first switch and to the first comparison element, the output of which is connected to the first switch, of the second shift register connected to the control unit, to

20 to the first and second elements of the corresponding, AND elements, the other inputs of which are connected to the control unit, the third shift register connected to the control unit to the second and third elements of the comparison and to the first switch, the second switch connected to the counter, to the control unit, to the third element of comparison and to the corresponding element I, and the fourth shift register connected to the first and second switches and to the third element of comparison 1. This device allows with high accuracy to harass the automatic counting of the number of objects, however, often there is a need to isolate from the entire set of objects studied only some predefined, with high reliability. The purpose of the invention is to increase the reliability of the device when selecting predetermined images of objects. The goal is achieved by inserting a serially connected memory block into the device, the inputs of which are connected to the counter, to the corresponding element of the group, to the second selection block, to the second and third registers. shear, and the second unit of selection, the other inputs of which are connected to the corresponding elements And and the delay elements. Fig. 1 shows the structural structure of the device for selecting the image of the object. in FIG. 2 - detector of closed regions J in FIG. 3 and examples of implementation of the memory unit and the second selection unit, respectively. The proposed device (FIG. 1) contains a scanning unit 1, two delay elements 2 and 3, two elements And 5, a detector of closed areas 6 , the element OR 7 and the counter 8 and the output of the scanning unit 1 is connected to the input of the first delay element 2 and. the first input of the first element And j, the output of which is connected to the subtractive input of the counter 8, the output of the first delay element 2 is connected to the input of the second delay element 3, the first input of the detector of closed regions 6, the first input of the OR element 7 the second input of the first element And and the first the output of the second element And 5 second input KOTdporo connected to the output of the second delay element 3 second, third And the fourth inputs of the detector 3 closed areas 6 are connected to the outputs of the elements And i and 5 and the second delay element 3, respectively, and the output from the second th input of the OR gate 7 whose output is connected to the summing input of the counter 8, wherein produced account objects. The detector of closed areas 6 (FIG. 2) contains the first selection block 9, the elements OR NOT 10, 11, and 12, the binary counter 13, the switching blocks, the shift ISIS registers, the control block 19, the comparison elements 20, 21 and 22, the AND elements 23, 2 and 25 groups, memory block 26 and the second selection block 27 “Memory block 2b (FIG. 3) contains one three-input element OR 28, a pulse shaper 29, a decoder 30, one four-input element OR 31, one two-input element AND 32, two two-input elements OR 33 encoder 3, multiplexers selectors 35, storage node 36 and two-input element ent And 37. The second selection block 27 (fig. k) contains two-input elements AND, two-input elements OR-46-30, pulse generator 51, counting trigger 52, counters 53 and 5, and memory nodes 55 and 56. Inputs 57, 58 and 59 of the first block 9, and the input 60 of the second block 27 are the inputs of the detector of the closed regions 6 and connected to the outputs of the two elements And 5 and to the output of the delay element 2, respectively, besides the input 58 of the first block 9 is connected to the second input of the second block 27 , the first, second and third outputs of the first block 9 are connected to the corresponding inputs unit 19, the first input of the element OR NOT 12, the input, elements OR of NO 10 and 11, and the first three control inputs of block 26j the outputs of elements OR NOT 10 and 11 are connected to the second and third inputs of the element OR NOT 12, the output of which is connected to the clock input of the counter 1}, the frame damping pulses (OIGs) are fed to the input of the zero setting, the outputs of the first register 15 are connected one bit to the inputs of the second register 16, to the first information input of one block 1, the first inputs of the comparison element 20 The outputs of the second register 16 are the same as the bottom. with the second inputs of the first element of comparison 20, with the first inputs of the second element of comparison 21, with the first inputs (: 10 input inputs of another block 1 and block 26, with the input of the third register 17 | the outputs of which are bitwise connected to the first inputs of the third comparison element 22, with the second, information inputs of blocks 14 and block 26, the outputs of one of the blocks 14 are bitwise connected to the inputs of the fourth register 18, the outputs of which are connected to the second inputs of the third comparison element 22 and with the inputs of blocks 1, the fourth information input of one block is connected to the output of counter 13 and the third input of block 2b. The output of the first element of comparison 20 is connected to the first control input of one switching block k, the outputs of the second element This comparison 21 is connected to the first inputs of the AND 23, 2 and 25 elements, the output of the first And 2 element is connected to the second control input of one block 14 and the fourth input of block 19, the fifth input of which is fed to lower-case damping pulses , the output of the second element And 2 is the output of the detector of closed areas 6, the output of the third element And 25 is connected to the first control input of another block 14 and the fourth control input block 26, the output of the third element of the comparison 22 is connected to the second control input of another block 14. First and second exit s block 19 are connected to third and fourth control inputs Yui um one block H to fifth control input of which is fed kntsy GIS, and the first clock input pulses are supplied to the clock frequency. The third output of block 19 is connected to the second clock input of one block It, the fourth output to the second input of the second register 16, the fifth output to the second inputs of elements And 23, 2A and 25, the sixth output to the third input of the 17th register 17, the seventh, eighth, the ninth outputs - with the third, fourth and fifth control 6 inputs of another block I, the first clock input of which is supplied with clock frequency pulses, and the second clock input connects with the tenth output of block 19 So the input of the first register 15 is connected to the output of one block 1 and clock input the second register 18 — with the output of another unit Sh. The fourth information 61 and fifth control 62 inputs of the block 26 are external inputs, and the outputs of block 26 are connected to the third and fourth inputs of the second block 27, to the remaining inputs of which are supplied the SGI, OIG and clock pulses. The device works as follows. Memory block 26 (Fig. 3) has multiplexers selectors, the outputs of which are connected to the address inputs of the memory node 36, by means of which the address inputs of the node 36 are switched by pulses at the control inputs of the node 36 with a certain information input. The pulse at control input 62 records the logical unit into the cells of the memory node 36 whose addresses are equal to the binary codes of the numbers received from information input 61. The binary input codes of the working numbers of those intersections that will be needed later divide Thus, when pulses are received at the control input B1, the working numbers of the objects that need to be allocated are written to the storage unit Zb. When entering the control inputs of the block 26 connected to the outputs of the first block 9 of the feature codes P1, P2, PZ, P4 and P5, information is read from the memory node 36, and when a sign P1 appears, the address inputs are connected to the output of the binary counter 13 signs P1, occurrences of signs P2, PZ, P and P5, the address inputs are connected to the output of the third register 17. When the working numbers at the corresponding information inputs of the block 26 and recorded in the memory node 36 coincide, the impulse of logical e appears Init, which pass through the AND gate 37 is supplied to the second input of the block 27. The element 37 is strobed and the pulses are generated by pulse generator 29 (it produces pulses of positive polarity at the rising edge of the input pulse).

During the processing of information, the working numbers assigned to the intersections may change. Whether the working number recorded in the memory node 36 changes it, then the logical units from the output of the AND 25 element are written to logical units in the memory cell of the new working node. number.

The second block 27 has two nodes 55 and 56 (Fig. 4). each of which operates either in the write mode or in the read mode, and their address inputs. binary counters 53 and 5 control the operation. Storage nodes 55 and 56 are controlled by a counting trigger 52, which changes its state with the arrival of the GIS. Assuming that the counting trigger 52 is in a zero state, then one of the storage nodes 56 is operating in a recordable record. At the clock input of the counter 5, which controls the address inputs, through the OR 7 element, the AND Q2 element and the IP element 49, intersection pulses are received from the corresponding row (input 58 of the allocation unit of the closed regions 6). If an intersection pulse arrives at the counter, which is necessary to allocate, then the memory node 5b receives a signal from the pulse generator 23 blocks

26, a logical unit is sent to the input of the storage node 5b through the element AND, which is fed to the input of the storage node 56 from the element 37 of block 26. If an intersection pulse arrives at the hour meter, which is not necessary to allocate, then

Node 56 at the corresponding address is written a logical zero.

Upon admission to the second block

27 GIS pulse count counters

53 and 5 go back to the initial state, and the counting trigger 52 changes the coupling state to the opposite. In this case, in the write mode, the other storage unit 55 works similarly as described. The storage unit 56 operates in the read mode. On

the clock input of the counter 5, which controls its address inputs, through the OR kd element, the AND 4l element and the OR 9 element receives intersection pulses (input 60 of the block for selecting the closed areas 6. When the intersection pulse arrives, it is necessary to separate it, is a pulse of a logical unit, which, passing through the element OR 50, arrives at the input of the element AND L5, and opens it, thereby passing the corresponding intersection pulse to the output of the second block 27. Thus, the output of the element And comes only of the impulses of intersections to be allocated.

When an element 38 of the OIG arrives at the inputs, the second block 27 is brought to the initial position. A pulse shaper 51t which generates pulses of positive polarity at the falling edge of the SGI serves to match the information recorded in the corresponding compression node 55 56 with the intersection pulses.

The introduction of new nodes makes it possible to significantly increase the reliability of the device by selecting predefined images.

Claims (1)

1. USSR author's certificate W 911569, cl. g, 06 K 9 / “6, 12.08.80. H X I h / ZPE Tl. at h / r / V at h / P / I x T