SU1660008A1 - Working memory addressing device - Google Patents

Description

The invention relates to computing and can be used for

addressing a memory containing groups of information arrays. The purpose of the invention is the extension of functionality due to the registration and redirection of free memory areas. The device contains a decoder 1, a group of elements And 2, 6, 7 and 15, a group of elements OR 3, 8, 9 and 17, a group of elements 4 and 16 delay, a group of triggers 5, a group of registers 10, a group of counters 11. a group of elements OR- NOT 12, group of adders 13, switch 14, element OR 18, adder 19, multiplexer 20. The goal is achieved by introducing new elements and connections. 1 il.

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The invention relates to computing and can be used to address a memory containing a group of information arrays.

The purpose of the invention is the extension of functionality due to the registration and redirection of free memory areas.

The drawing shows a functional diagram of the device.

The device contains decoder 1, group of elements AND 2, group of elements OR 3, group of elements 4 delays, group of triggers 5, group of elements AND 6, group of elements AND 7, group of elements OR 8, group of elements OR 9, group of registers 10. group of counters 11, a group of elements OR-NOT 12, a group of adders 13, a switch 14 (a group of elements AND 15, a group of elements 16 delay, a group of elements OR 17, an element OR 18, an adder 19, a multiplexer 20, inputs 21-28 of the array volume, initial setting , write mode, addresses of free array, read mode, initial hell ENA list arrays recording mode start address, the start address dedicated device array free pointer outputs 29-31 of the array, the array of free addresses, indicating the absence of the desired array devices,

The device works as follows.

Before starting, the signal from input 22 through the elements OR 3 clears all triggers 5. Then signals to inputs 21, 26 and 27 are given.

The device works on the example of accessing an array (block) with a volume of K words as follows. For each such set of signals in the K-th register 10, designed to store the initial address of the list of blocks of volume K, the address is recorded from input 26. After all the initial addresses are written, the device is ready to write or read the addresses of free blocks of any volume.

When recording, the volume of the free array, the sign of the record and the address of the array are fed to the inputs 21, 23 and 24. The signal from the corresponding K-th output to the decoders through the K-th element AND 2, the K-th element OR 17 translates (confirms) trigger one to 5, adds one to the contents of the K-th counter 11 and through the K-th element OR 9 and the switch 14 outputs the output 29 address (equal to the sum of the contents of the K-th register 10 and the new contents of the K-th counter 1 ^ formed in the K th adder 13. At this address, the address of the free array from the input 24 is recorded through the multiplexer 20.

When reading, a signal is sent at input 25 and a code at input 21. The signal from the corresponding decoder's K-th output of decoder 1 goes through the K-th element OR 8 passes to the K-th element AND 7. which is prepared for opening with signals from the single output of the K-th trigger 5 and from the input 25. The signal from the output of the element And 7 enters through the K-th element OR 9 to the control input of the switch 14. The sum of the codes of the K-th register 10 and the K-th counter 11 from the output of the K-th adder 13 through the switch is issued on exit 29 of the device. This sum is equal to the address of the cell in which the address of the last block in the list of the required volume is located. In addition, the signal from the output of the K-th element And 7 enters the subtractive input of the counter 11 (subtract one) and it begins to indicate the address of the cell in which the address of the penultimate block of the required volume is located. If the selected array is the only one in the list, then along the ORINE 12 circuit - the delay element 4 - the OR element 3 zeroes the Kth trigger 5.

If during the next request it is found that the list of arrays of volume K is empty, then the signal from the K-th output of the decoder 1 through the circuit elements AND 6, elements OR 8 passes to the output of the element AND 7 corresponding to one of the large ones whose list is not empty (the corresponding trigger 5 in a single state). According to the rule described above (reading), at the output 29 of the device, the address of the cell containing the address of the free array is formed, and the counter is prepared to indicate the next unallocated array. Simultaneously, the address of the allocated array from the input 28 of the device is fed to one of the inputs of the adder 19, to the other input of which the code of the required demand from the input 21 of the device enters. Since in this case a volume is allocated greater than that required by request, then at the output of the adder 19, the initial address of the free area is formed, which by gradation corresponds to the volume preceding the selected one. The signal from the output of element 7 And, corresponding to the allocated volume, is fed to one of the inputs of the preceding element 15, to the other input of which a signal is received from the output of element 8, indicating that the list of previous volumes is empty at the time of the request. The signal from the output element 15 is supplied to the element 16 delay. The delay is chosen in such a way that the next procedure does not prevent the consumer who sent the request to accept

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address of the selected array. The signal from the output of the delay element 16 is fed through the element 17 to the single input of the trigger 5, corresponding to the volume preceding the selected gradation. Simultaneously, the signal from the output of the element 17 is fed to the input of the corresponding element 9 and the input of the addition of the unit of counter 11. From the output of the element 9, the signal goes to the corresponding control input of the switch 14, and the output 29 transmits the result of addition on the adder register register 10 corresponding to the array, over the volume preceding the allocated one and the contents of the corresponding counter 11. At the same time, the signal from the output of the delay element 16 through the element 18 goes to the control input of the multiplexer and to the output 30 mouth oystva information is issued from the output of the adder 19. Further, the cell address which is formed at the output of device 29 is recorded an address of the free zone which is formed in an adder 19 and transmitted to the output device 30. Consequently, if at the request the required volume is allocated from the composition of a larger array, then the remaining part of the array is not considered to be occupied, but is treated as a free array, preceding the selected one by gradation.

Claims (1)

The claims device addressing memory, contains a decoder, three groups of elements AND, three groups of elements OR, a group of delay elements, a group of registers, a group of counters, a group of elements OR NOT, a group of adders, a group of triggers and a switch, and the output of the K-th adder the group is connected to the K-th information input of the switch (K = 1, M, where M is the number of memory arrays), the output of which is connected to the output of the pointer pointer of the device’s free array, the K-th output of the decoder is connected to the first input of the K-th element a And the first group and the input sample of the K-th register of the group, the output of the K-th group counter is connected to the first information input of the K-th group adder and the inputs of the K-th element OR-NOT group, the output of which is through the K-th group delay element to the first input of the K-th element OR of the first group, the output of which is connected to the input of the set to zero of the K-th group trigger, the inverse output of which is connected to the first input of the K-th element AND of the second group, the second input of which is connected to the first the input of the K-th element of the third group, the direct output of the K-th trigger of the group is connected to the second input of the K-th element of the third group, the third input of which is connected to the input of the read mode of the device, the P-th output of the decoder is connected to the first input (P- 1) -th element OR of the second group (P = 2.M), the output of which is connected to the second input of the P-th element AND the second group, the second input of the first element AND the second group is connected to the first output of the decoder, the output of the M-th element AND the second the group is connected to the output indication of the absence of the required array device va, the input of the starting address of the device array list is connected to the information input of the K-th register of the group, the output of which is connected to the second information input of the K-th group accumulator, the input of the recording mode of the device's initial address is connected to the input of setting the zero of the K-th group counter and synchronous input K-th register of the group, the output of the K-th element AND the third group is connected to the first input of the K-th element OR of the third group and the subtraction input of the unit of the K-th group counter, the input of the addition of which is connected to the input of the unit installation K-th group trigger and the second input of the K-th element OR of the third group, the output of which is connected to the K-th control input of the switch, the input of the initial installation of the device is connected to the second inputs of the elements OR of the first group, the input of the recording mode of the device connected to the second inputs of the elements AND the first group, characterized in that, in order to extend the functionality due to the registration and redirection of free memory areas, a group of AND elements, a group of delay elements, a group of OR elements are introduced into it. the OR element, the adder and the multiplexer, the input volume of the device array is connected to the input of the decoder and the first input of the adder, the second input and output of which are connected respectively to the input of the initial address of the device’s dedicated array and the first information input of the multiplexer whose output is connected to the output address of the device free array , the output of the P-th element And the third group is connected to the first input (P-1) of the -th element AND of the fourth group, the output of which through (P-1) -th delay element of the fourth group is connected to (P- 1) to the input of the OR element and the first input (P-1) of the element OR of the fourth group, the second input and output of which are connected respectively to the output (P-1) of the AND element of the first group and the installation input to the unit (P-1 ) th 7 1660008 8 trigger group, the output (P-1) of the -th element OR by the group boom is connected to the second input (P-1) of the -th element of the fourth group, the output of (P-1) -th element of the second group is connected to the second input (P- 1) -th element 5 of the second group, the output of the M-th element of the first group is connected to the installation input of the unit of the M-th group trigger, the input address of the device free array is connected to the second multiplexer information input, the first and second control inputs of which connected respectively to the output of the OR element and the recording mode of the device /