SU1481739A1 - Device for processing numeric numbers - Google Patents

Abstract

The invention relates to computing and can be used in the construction of systems for collecting and processing information represented by arrays of numbers, for example, in digital image processing devices. The purpose of the invention is to expand the functionality by performing the operation of combining, intersecting, and complementing over L - sets. The device contains a register 8, a reversible counter 9, a memory unit 12, a logic processing unit 13, delay elements 10 and 11, an AND 14 element, a group of AND 15 elements. The logical processing unit contains information registers, AND elements, an OR element, a switch, elements AND-NO. The operation of the device is based on the recording in the memory unit of single signs of the presence of a specific number in each of the input arrays at the address specified from the output of the counter used as a register. Numbers are recovered by allocating the corresponding strobe signals by fixing the origin and excluding from the series the clock pulses of those in the order of the pulses, the numbers of which were not present in the array during recording. The value of the array numbers is recovered from linearly increasing or decreasing codes allocated at the outputs of the counter. The logic processing block introduces additional restrictions on the output of numbers. 1 hp ff, 3 ill.

Description

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The invention relates to the field of computer technology and can be used in the construction of systems for collecting and processing information represented by numeric arrays, for example, in digital image processing devices.

The aim of the invention is to expand the functionality of the device by performing operations of combining, intersecting, and complementing L-sets.

FIG. 1 is a diagram of a device for processing arrays of numbers; in fig. 2 is a block diagram of logical processing; in fig. 3 - a graphic representation of the operation on two sets.

A device for processing arrays of numbers (Fig. 1) contains inputs 1 - 1 -1-3 for recording device modes, inputs 2-1-2 - (L + 1) for setting modes for a device, providing the ability to change functions, input 3 for recording block operation mode memory, allowing it to be set to the recording mode of any of the L arrays and its transfer to the information output mode, the input 4 records the array numbers, the input 5 controls the output mode in order of increment or

Elements 14 and 15-1 through 15-L are designed to receive gate signals, which are used to sample processing results from an increasing or decreasing sequence of code signals from the outputs of counter 9 in the output mode.

Suppose, for example, that you need to enter an inverse ordered array in the same external device in the order of increasing, and

10 in the next L devices in order of increasing - ordered arrays, starting from the 1st to the Lth.

In this case, the reversible counter 9 is set to a single potential in

c is the summation mode and zero initial state (along the reset circuit) and in accordance with Table. 1 provides the following option for setting register codes: 22-1 - 000 ... 0 ... 001, 22-2-000 ... 0 ... 001, 22-3- 000 ... 1 ... 001.

20 With the clock pulses fed to the input 7, the reversible counter 9 provides a linear reading of the unitary signs of the presence of numbers written in the block 12 in the previously entered arrays. In the event that when writing an array, the number was present at the number deduction, information inputs 2 during block 12, a logical 6-1-6-N, clock input 7, register 8, one is set, but if not, a logical zero,

reversible counter 9, elements 10 and 11 for-Thus, at the outputs 18-1 -18-N

support, memory block 12, logic device block 13 is allocated linearly by the growth processing, element 14, a group of L sequence of possible variants AND 15-1 -15-L, strobe JQ tov N bits codes, and at the outputs (L + 1) -and output 16, gating outputs 17, block 12, the information about the presence of the first L-th information outputs 18-1 - 18- / V

Block 13 logical processing contains the inputs "Write registers 19-1 - 19-3,

of each number in the previously entered array, which allows to obtain from the sequence of clock pulses at input 7 the corresponding gate signal on

inputs 20-1-20- (L + 1) mode setting 35 output elements And 15-1 -15-L, with the option block, inputs 21 - 1-21-L, information registers 22-1-22-3 elements AND 23- 1-23-L and 24-1-24-L, element OR 25, element AND 26, switch 27, elements AND-NOT 28-1, 28-2, 28-3, exits 29-1, 29 -2,

the power of which you can restore from the codes at the output of the counter 9 of each of the numbers. This is implemented on the input registers of external devices for the processor, in which, in accordance with the construction of functions, the output-OR or OR-NOT, AND-AND-NOT and output codes of the counter 9 are written with 40 signals.

dividing one of the 12 arrays recorded in the block.

A device for processing arrays of numbers works as follows.

Register 8 is used to set the operation mode of memory block 12 in accordance with Table. 2

Changing the processor's operating modes is performed by writing the required code into the register 8.50 of the signal to the input. Recording, for example, input-reversible counter 9 uses an external register of the external device on D triggers, the information inputs of which are connected to the information outputs 18-1 -18-Л of the device as in the previous case, the array numbers are restored by gating signals.

Similarly, you can consider the operation of the device when implementing functions, as well as at the outputs of block 13 in accordance with the table. 1, the following meanings are distinguished: 29-1- "1; 29-2- "1; 45 29-3-X /, then at the output 16, the strobe signals are outputted in ms in accordance with the change in the inverse value of the unit features of the sequence previously recorded in the memory block.

When the output of the 16 strobe

as a buffer register when entering arrays into the processor and as a sweeping and restoring number of device arrays when displaying information.

The delay elements 10 and 11 are designed to match the device’s internal signals in time.

Elements 14 and 15-1 through 15-L are designed to receive gate signals, which are used to sample processing results from an increasing or decreasing sequence of code signals from the outputs of counter 9 in the output mode.

Suppose, for example, that you need to enter an inverse ordered array in the same external device in the order of increasing, and

0 to the next L devices in order of increasing - ordered arrays, starting from the 1st to the Lth.

In this case, the reversible counter 9 is set to a single potential in

c is the summation mode and zero initial state (along the reset circuit) and in accordance with Table. 1 provides the following option for setting register codes: 22-1 - 000 ... 0 ... 001, 22-2-000 ... 0 ... 001, 22-3- 000 ... 1 ... 001.

0 With clock feeds to the input 7, the reversible counter 9 provides linear reading of 12 single signs of numbers in the previously entered arrays recorded in the block. In the event that when writing an array, the number was present at you block 12, a logical one is set, if not, a logical zero,

of each number in the previously entered array, which allows to obtain from the sequence of clock pulses at input 7 the corresponding gate signal on

the outputs of the elements And 15-1 -15-L, with-

a signal to the input “Record, for example, the input register of an external device to DTak as at the outputs of block 13 in accordance with Table. 1, the following meanings are distinguished: 29-1- "1; 29-2- "1; 29-3-X /, then at the output 16, the strobe signals are sent in ms in accordance with the change in the inverse value of the unit features of the sequence previously recorded in the memory block.

When the output of the 16 strobe

in the table. 1. It is only necessary to take into account that the corresponding restrictions on the passage of the OR signals through the element OR, as well as a number of derivatives from the ones listed in Table 2, are introduced from the outputs UBU2, OU. 1 operations on sets of numbers represented by arrays entered into a device, for example operations on two sets shown in FIG. 3

more sets, their intersections, as well as additions to these operations. By entering the results of performing such operations as additional arrays, any operation on L sets of numbers can be implemented in the device.

When transferring counter 9 from the summation mode to the subtraction mode, it is possible to realize the output of the results of performing operations on sets in the order of loss. You need to find an addition to the number of numbers, and when using the counter 15

to the full set B (corresponds to all possible bit numbers, and in block 12 to all units 111 ... 1111) expressions that can be written g / L | 1D2 (Fig. 3).

In accordance with the table. 1 in the registers of block 13, it is necessary to write to RG 22-3- (000 ... 001), BRG 28-1 - (000 ... 001), (i.e., logical unit is set at output 29-1), RG 22-2- (110 ... 001), which corresponds to the supply to the inputs of the element AND 26 20 signals, depending on the state of the registration g-sequence of single features, and 22-1-22-3 (Л ° 2--4) . Change

memory blocks and the implementation of the inversion of the state of the registers 22-1 - 22--3 results of the execution of the operation AND on one is the supply of the corresponding (gab. 1,

No. 2-4) code on the inputs 20-1 -20 (L41)

ka 9 in the output mode as a buffer register it is possible to carry out the output of numbers not according to a linear, but according to an arbitrary law.

Consider (Fig. 2) the operation of the block 13 logical processing. In tab. 1, No. 8 is given a list of operations that block 13 performs when applying to its inputs 21 --- 1-21 - L input signals А Ь Xi Хз ..- Xt ... Xi .. In the table. I, no. 5-7 presents the state of the weekend

signs of arrays A and Ar, introduced earlier in the memory blocks.

As a result of the AND-NOT operation over all the numbers in the array, the required operation is realized:

25

device and pulse "Record for entry 19-1 -19-3. The output code signals of the registers 22-1, 22-2 control the passage of information signals from inputs 21 - 1-21-L through the elements And 23 1-23-L and 24-1-24-L, and the output signals of the register 22-3 - the passage of the same signals through the multiplexer 27. This allows you to select at the output of the element OR 25 any of the output signals or zero potential (Table 1. No. I), as well as to perform the OR operation on an arbitrary number of input signals (Tab 1 , K ° 2), PA element output And 26 - zero potential, any of the input signals (Table 1, L ° 5) or operation And over an arbitrary number of input signals (Table 1, LG9 6), and at the output of the NAND element, any of the input cm of trees (Table 1, No. 9). Since the outputs of the OR 25 and AND 26 elements and multiplexer 27 are connected to the outputs 29-1 , 29-2, 29-3 through the AND-HE 28 elements controlled from the L + I outputs of the registers 22-1, 22-2, 22-3, at the outputs 29-1, 29--2. 29-3 , Besides

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device and pulse "Record for entry 19-1 -19-3. The output code signals of the registers 22-1, 22-2 control the passage of information signals from inputs 21 - 1-21-L through the elements And 23 1-23-L and 24-1-24-L, and the output signals of the register 22-3 - the passage of the same signals through the multiplexer 27. This allows you to select at the output of the element OR 25 any of the output signals or zero potential (Table 1. No. I), as well as to perform the OR operation on an arbitrary number of input signals (Tab 1 , K ° 2), PA element output And 26 - zero potential, any of the input signals (Table 1, L ° 5) or operation And over an arbitrary number of input signals (Table 1, LG9 6), and at the output of the NAND element, any of the input cm of trees (Table 1, No. 9). Since the outputs of the OR 25 and AND 26 elements and multiplexer 27 are connected to the outputs 29-1 , 29-2, 29-3 through the AND-HE 28 elements controlled from the L + I outputs of the registers 22-1, 22-2, 22-3, at the outputs 29-1, 29--2. 29-3 , Besides

A and second Arg arrays use direct signals from the outputs of the elements OR

25 and 26 and multiplexer 27. can be obtained their inverse values (Table 1, No. 3, 4, 7, 8, 10). Since the writing of codes to registers 22-1, 22-2, 22-3 is carried out independently of any other factors besides the described factors, at outputs 29-1, 29-2, 29-3 can also be obtained possible combinations are given in table. 1, No. 5-7 operations.

to impose restrictions on the passage of gating signals. Similar to the one considered on the input registers of subsequent devices, numbers are recovered.

The same operation can be implemented for a larger number of arrays, which is realized by introducing the corresponding (Table 1) codes into the necessary registers 22.

You can also show the implementation of other operations on the sets A, Ar (Fig. 3) given by numeric arrays, as well as combining two, three or

more sets, their intersections, as well as additions to these operations. By entering the results of performing such operations as additional arrays, any operation on L sets of numbers can be implemented in the device.

When transferring counter 9 from the summation mode to the subtraction mode, it is possible to realize the output of the results of performing operations on sets in the order of decreasing numbers, and when using counting, and when using the counter

Signals depending on the state of registration of the 22-1-22-3 gates (L ° 2--4). Change

ka 9 in the output mode as a buffer register it is possible to carry out the output of numbers not according to a linear, but according to an arbitrary law.

Consider (Fig. 2) the operation of the block 13 logical processing. In tab. 1, No. 8 is given a list of operations that block 13 performs when applying to its inputs 21 --- 1-21 - L input signals А Ь Xi Хз ..- Xt ... Xi .. In the table. I, no. 5-7 presents the state of the weekend

device and pulse "Record for entry 19-1 -19-3. The output code signals of the registers 22-1, 22-2 control the passage of information signals from inputs 21 - 1-21-L through the elements And 23 1-23-L and 24-1-24-L, and the output signals of the register 22-3 - the passage of the same signals through the multiplexer 27. This allows you to select at the output of the element OR 25 any of the output signals or zero potential (Table 1. No. I), as well as to perform the OR operation on an arbitrary number of input signals (Tab 1 , K ° 2), PA element output And 26 - zero potential, any of the input signals (Table 1, L ° 5) or operation And over an arbitrary number of input signals (Table 1, LG9 6), and at the output of the NAND element, any of the input cm of trees (Table 1, No. 9). Since the outputs of the OR 25 and AND 26 elements and multiplexer 27 are connected to the outputs 29-1 , 29-2, 29-3 through the AND-HE 28 elements controlled from the L + I outputs of the registers 22-1, 22-2, 22-3, at the outputs 29-1, 29--2. 29-3 , Besides

direct signals from the outputs of the elements OR

direct signals from the outputs of the elements OR

25 and 26 and multiplexer 27. can be obtained their inverse values (Table 1, No. 3, 4, 7, 8, 10). Since the writing of codes to registers 22-1, 22-2, 22-3 is carried out independently of any other factors besides the described factors, at outputs 29-1, 29-2, 29-3 can also be obtained possible combinations are given in table. 1, No. 5-7 operations.

Claims (2)

1. A device for processing arrays of numbers containing a reversible counter, a memory block, a group of elements I, and the information inputs of the device are connected to the information input of the reversible counter, the counting input of which is connected to the clock input of the device, the input Record of the device connected to the input of the recording control of the reversing counter, the outputs of the bits of which are connected to the address inputs of the memory block These outputs, which are connected to the first inputs of elements AND groups, the second inputs of which are interconnected, the outputs of elements AND groups are the outputs of the device, characterized in that, with the purpose extending the functionality by performing the operation of combining, intersecting and adding over L-sets, a register, a logic processing unit, two delay elements and an AND element are entered into it, the inputs of the device’s mode recording inputs are connected to the corresponding inputs of the modes of the logical processing unit, the task inputs the modes of which are connected to the inputs of the device mode setting and to the information inputs of the register, the outputs of the bits of which are connected to the inputs of the memory block whose recording input is through the first The delay element is connected to the Device Record input, the memory block outputs are connected to the information inputs of the logic processing block, the outputs of which are respectively connected to the first three inputs of the AND element, the fourth input of which is connected to the second inputs of the AND elements of the group and through the second delay element is connected to the clock input of the device, the outputs of the elements And group b0 five These are the L-gating outputs of the device, the output of the AND element is the (L + 1) -m gating output of the device, the outputs of the reversible counter are the information outputs of the device. 2. The device according to claim 1, characterized in that the logical processing unit contains three (L + 1) -digit registers, the first and second group of elements AND each with L elements, L-input elements AND and OR, a switch and three of the NAND element, and the inputs of the recording modes of the block are connected respectively to the inputs of the Record of the first, second and third registers, the information inputs of which are bitwise connected to the corresponding inputs of the block modes, the information inputs of the block are respectively connected to the first inputs of the first and second elements UTP and to the information inputs of the switch, the first L-outputs of the first and second registers are connected to the second inputs of the elements of the first and second groups, respectively, the outputs of the third register from the first to the L-th are connected to the corresponding control inputs of the switch, (LH) -e outputs first, second and third registers are connected respectively to the first inputs of the first, second and third AND-NES elements, the second inputs of which are respectively connected to the outputs of the OR element, the AND element and the switch, the outputs of the first and second groups of el cops and are connected respectively to the element inputs of the AND and OR, the outputs of the first, second and third AND-NO elements are outputs logical processing unit. 0 five 000 1 ... 000 1 ... 1 ... 110 one.. P 011 .001 Xp m x, XtVX, x, uhguh3 X.VXj x, vx, v ... vx, 1 x, X x, P Xt n Xt x, vx, vx5 fl xTvx, x, Performing an OR operation on any combination of signals at inputs 21-1-21-L (Output 29-1) Obtaining an inversion of any of the signals applied to the inputs 21-1-21-L (Output 29-1) Performing an OR-NOT operation on any combination of signals at inputs 21-1-21-L (Output 29-1) Che & to vj s about 000 ... 000 100 ... 000 010 ... 000 001 ... 000 000, .. 1 ... 000 000 ... 010 110 ... 000 111 ... 000 0 x x ,. x 4 one Xf XL x, vx, X, VX} VX3 Connecting any of the signals from inputs X1, XtX3 ... XL) supplied to the inputs 21-1-21-L, to output 29-2 Performing operation And on any combinations of signals on inputs 21-1-21-L ten 000. 111. 000. 100. 010. 001. .001 .001 .001 .001 , 1 ... 000, 111 X (AXj X.AXjAXjA. .X X, X, - (Exit 29-2) -Getting any inversion Of signals from inputs 1 i X3 ... X exit 29-2 x, -. x, 110. 111. 000 111. .001 .001 L ... 001 X / .Hg.  four , Performing an NAND operation on any combination of signals at inputs 21-1-21-L (Output 29-2) & you cho about X, B X5 Connect any of the signals X1, Xg, X ,. XL to exit 29-3 000 ... 1 ... 000 eleven 000 ... 010 000 ... 001 100 ... 001 010, .. 001 001-001 Hs n X, Conduct an inversion of any of the signals l, l. at A ... A | exit 29-3 to xf m 13 Output information 000 ... 000 100 ... 000 010 ... 000 001 ... 000 000 ... 001 110 ... 000 111 ... 000 111 ... 111 1481739 14 table 2 Mode Conclusion of numbers from the block 12 Input of numbers of the first array Input of numbers of the second array Input of numbers of the third array Entering L-ro Array Numbers Entering numbers of one array at a time the first and second nodes of block 12 Entering numbers of one array at a time the first, second and third nodes of block 12 Entering numbers of one array at a time in all nodes of block 12 Well t to n t m P