SU1429107A1 - Device for sorting an array of numbers - Google Patents

Abstract

The invention relates to computing technology and can be used in building information collection and processing systems. The purpose of the invention is to expand its functionality by selecting sorted numbers for a given attribute. The device contains a switch 6, re

Description

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1429

Versive counter 9, memory block 8, group of N elements And 11, element I And 12, block of constraints 10, and element i of delay 7. When ordering the array of numbers, one-digit signs of the presence of the address given by the value of the number. The reading of the information jJ, Tfli is performed by a counter with a linear increase or decrease of all I possible values of the number. Functions

one

The invention relates to computing and can be used in the construction of systems for collecting and processing information.

The aim of the invention is to expand the functionality by selecting sorted numbers for given characteristics.

FIG. 1 shows a diagram of the proposed device for sorting an array of numbers; in fig. 2 and 3 are options for constructing a restriction block.

A device for sorting an array of numbers (Fig. 1) contains control input 1 Input / output of array J inputs 2-2, 2-3 assignments of signs, input 3 Overwrite, information inputs 4-1 to 4-N, control input 5 Increment-decrease, switch 6, delay element 7, memory block 8, reversible counter 9, block) 0 constraints, group of N elements 11-1-1, element 12, information outputs 13-1-13-N, synchronous output output 14.

Restriction unit 10 (the first version of Fig. 2) contains control input 15 Record, information inputs 15 and 16, control input 17 Record, input 18- Record, registers 19, comparison circuits 20, first 21-1 second 21-2 multiplexers , AND 22 element, AND-NO 23 element, OR element 24, OR-NOT 25 element, output multiplexer 26 and control output 27.

Restriction unit 10 (second variant, Fig. 3) contains information inputs 28 and 29, control inputs 30 and 31 Record, registers 32, circuit

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The treatments are defined by codes written to the constraint block. A restriction block (two options) allows a group of numbers belonging to a given interval to be output, a group of numbers not belonging to a given interval to be output, the exclusion of arbitrary numbers from an ordered array, and the determination of the belonging of arbitrary numbers to an ordered array. 2 hp f-ly, 3 ill., 6 tablets.

33 comparisons, multiplexer 34, EXCLUSIVE OR element 35 and control output 36.

A device for sorting an array of numbers works as follows.

Before each input of the numbers of the ordered information array, the memory block B is cleared (Table 1, p. 1) by feeding the zero code to the inputs 2-1 + 2-3 devices (columns 3-5) and one pulse to the input 3 (column 15). In this case, the switch 6 enters the signal transmission mode from input P to output A (column 7) and then to input 17 (Fig. 2) of block 8 (Fig. 1).

When performing this operation, the state of the inputs 1, 2, 4 and 5 of the device, as well as the state of the counter 9 and the register 19 can be any ..

The numbers of the ordered array are entered after setting a single potential at input I, which transforms unit 8 into recording mode, and input 2-3 devices (Table 1, p. 2) allowing the passage of pulses from input 3 of the device to output 8 of the switch 6 (column 8), which are then fed to the input Record counter 9 and through delay element 7 to the input Record of block 8. The impulse to input 3 of the device in this case must be supplied synchronously with the feed of the next number of the array to be ordered, which first records this the numbers in counter 9, and then, thanks to delay element 7, the writing of a logical unit to one of the triggers of block B, corresponding to

31A291

address given by the output code of the counter 9. In this case, the counter 9 serves as a buffer register.

The proposed device performs one of seven functions — when outputting the ordered information in order of increasing (logical unit at input 5) or decreasing (logical zero at input 5) of numbers (Table 2 and 1 - Table 2, p. 7) . The installation of the required output mode option is carried out by writing the codes indicated in columns 5-7 (Table 2) into registers 19 (Fig. 3) and setting the initial state of counter 9 (Fig.), Entered into J5 tab. 2, column 8. The required code values are written to the registers 19 by setting the required code on the inputs 4-1 4-N of the device and applying a write pulse 20 to the clock inputs 15, 17 and 18 of the registers 19. Switching the pulse Overwriting from the device 3 input to inputs Records 15, 17 and 18 are performed by switch 6 in accordance with Table 1 25 and 3.1 - 3.3.

Setting the operation modes of the sorting device is given in Table. 1. The same switch 6 likewise provides the ability to set a random initial state of the counter 9 on the buses. Set to zero (Table 1, p. 3, 4), Record (Table 1, p. 2) and supply clock pulses on it (pl. i, p. 3, 5). five

Installation options output mode is presented in Table. 2

Schemes 20-1, 20-2 of comparison block 10 Limitations (Fig. 2) operate in accordance with Table. 3.40

Multiplexers 21-1, 21-2 provide information transfer from inputs A to output B, depending on the state of the control signals W 1, W 2 presented in Table. four.

Let, for example, in the register 19-3 the zero code is written, allowing the passage of signals from the inputs A of the multiplexers 20-1, 20-2, 26 to. output B (tab. 4, p. 1). Since the inputs A1 50 of the multiplexers 20-1, 20-2 are connected to the bus Logical unit, a unit potential will be installed at their outputs B and, therefore, at the output of the element And 22, which is transmitted by the multiplexer 26 to the output 27 of the limiting unit 10 . Thus, in any condition, the codes at the information inputs 16-1 - 16-N and 15-1 074

 - 5-N block 10 of the restriction provides the presence of a signal of a logical unit at the first inputs of the elements 11-1-1 11-N and 12, which allows for the output of the entire ordered array (Table 2, p. 1). Suppose, for example, that the initial state of the counter 9 was previously established, and at the control input 5 there was a unit potential ensuring the operation of the counter 9 in the summation mode. With the delivery of each clock pulse to the input 3, the overwriting of the device, which due to the installation of the software code (table- (1, p. 3, 5) on its control inputs 2-1 to 2-3, is allocated at the output G of the KONtMyTaTopa 6 and enters on TaKTOBbrfi the input of the counter 9 and on the third input of the element 12, the output code of the counter 9 increases by 1. Since unit 1 signs of the presence of numbers in the input array were previously recorded in block 8, when a zero potential is installed at the input 1 of the device (Fig. 1) A sign is read at the address of the corresponding counter output code ka 9.

If during the processing of the array, the number at the output of counter 9 was present in the data stream, then the memory block 8 outputs a single potential, which, when it arrives at the first inputs of And 11-1 elements - I1-N, And 12, opens them and the code from the counter 9 outputs enters the outputs 13-1 - 13-N, 14 devices. If there is no such number, then block 8 outputs a zero potential and prohibits the output of a code from the output of counter 9 to the output of the device.

A linear increase in the counter code 9 allows an ordered output of the array fixed in block 8 in order of increasing (Table 2, item 1, upper line).

Similarly, we can consider the operation of the device when outputting in order of decreasing numbers, i.e. at zero potential at the input 5 of the device and the maximum value of the counter (Table 2, p. I, bottom line).

Let in the register 19-3 (Fig. 2) the code 001110 (the least significant bit is rightmost) is recorded, allowing the transfer of information: multiplexer 21-1 from input A2 to output 8, multiplexer 21-2 from input A4 to output 8, multiplexer 26 from entrance A1 to exit B.

8register 19-1, 19-2 recorded mi

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minimum and maximum numbers of some interval. In accordance with the table. 3, the block 10 of the limit in this case provides a zero potential at the output 27, if the number supplied to the information inputs 15-1 to 15-N lies outside the interval specified by its minimum and maximum numbers. If the number lies within the specified interval, then on output 27 (Fig. 2) of the limiting unit 10 there is a single potential. This is provided by connecting the output of the comparison circuit 20-1 through multiplexer 21-1 to the first input of the element. AND 22, and the output of the comparison circuit 20-2 through multiplexer 21-2 to the second input of the And 22 element, as well as the output of the And 22 element via input A1 multiplexer 26 to output B and then to output 27 of block 10 of limitation.

In this case, and when increasing (table. 2, p. 2, first row) and decreasing (table. 2, p. 2, third row) counter code 9 with corresponding codes (table. 2, p. 2) in registers and 19-2, the initial states of the counter 9 and the states of the signal at the input b are used to issue a resolution signal from the output of the block 10 to the third inputs of the elements I I1 - - - 11-N, And 12, which allows output numbers of an ordered array belonging to a given interval.

Similarly, we can consider the operation of the device in the derivation of ordered numbers belonging to a given interval in other versions of the installation of this mode, noted in Table. 2, p. 2, second and fourth lines.

The next (tab. 2, p. 3, first: line) mode of operation of the device when outputting information differs from the previous one in that multiplexer 26 switches to the output 27 of the signal from input A2, which is connected to the output of the element AND-NOT 23, the inputs of which are connected to the outputs of the multiplexers 21-1, 21-2. The multiplexers switch the same signals as in the previous case. This is ensured by setting the codes in registers 19-1 to 19 and counter 9 (Table 2, item 3, columns 5-7) and allows to obtain a single potential at the output of unit 10 in the case of

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0

five

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0

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0

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0

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In addition, if the number at the inputs L (FIG.) of block 10 is outside the specified interval. The operation of the entire device in this case can be considered by analogy with the previous case.

It is possible to implement the mode of outputting the numbers of an array larger or smaller than a given number when writing zero or one codes to registers 19-1 and 19-2.

A variant of the output mode (Table 2, p. 4) is set by writing to the register 19-3 a code 011010 (ml. Bit to the right), which provides connection of the outputs of the comparison circuits 20-1, 20-2 through the multiplexers 21-1, 21- 2 to the inputs of the AND-HAND elements 23 and its output through the multiplexer 26 (input A2) to the output 27 of the limiting unit 10. In this case, both the register 19-1 and the register 19-2 record the number that must be excluded from the output from the ordered array.

Thus, as soon as the outputs of the counter 9 is set recorded in the registers 19-1, 19-2 number, the signal; The level of the logical unit from the output of the comparison circuits 20-1, 20-2, through multiplexers 21-1, 21-2, goes to the inputs of the NAND element 23, setting it to the zero state. Through multiplexer 26, this zero level enters the output 27 of block 10 of limitation.

This leads to the fact that as in the case of table. 2, p. 1, the numbers of the array can be output in the order of increase and decrease, but the bus from output 27 (Fig. 2) of restriction unit 10 prohibits the origin of the number, namely, recorded in registers 19-1, 19-2 through elements And - - 11-N, and the synchronizing pulse through the element And 12.

The output mode option (Table 2, p. 5) is characterized in that the signals from the outputs of the comparison circuits 20-1, 20-2 are fed to the inputs of the OR-NOT 25 AND element through multiplexers 21-1, 21-2 and its output through multiplexer 26 is connected to output 27 of limiter 10. In this case, the prohibition signal prohibits the passage of numbers from the counter output through the element 12 to the sync output of the device.

Verify that the number of the ordered array (Table 2,

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6) is carried out by setting in the register the code 011010, which provides the connection in accordance with the table. And the outputs of the circuits 20-1, 20 in comparison to the inputs of the element AND 22 through multiplexers 21-1, 21-2 and its output through the multiplexer 16 to the output of the limiting unit 10. In this case, the number, the verification of which belonging to the ordered array is carried out, must be written to registers 19-1, 18, and the counter is set to the zero state (input 5 - the unit potential) when checking the increase in numbers and to the unit one (on input 5 is a logical zero) when checked in order of decreasing numbers. These actions lead to the fact that when deploying the output codes of counter 9, for example, from zero to maximum elements, I-12 will be closed by zero potential from the output of element 22, which is set by zero potentials at the inputs of circuits 20-1, 20- 2 comparisons until the number at the output of counter 9 compares with the number written in registers 19-1, 19-2. At the same time, a single potential is established at the outputs of the comparison circuits 20-1, 20-2, at the inputs of the element 22, at its output and at the output of the block 10, and if this number is present in the ordered array, i.e. at the address specified by the counter 9, in block 8 a logical unit is written, elements 11 and 12 are opened by a single potential from the output of block 8 and the outputs of the counter are opened through open elements 11 11 - and 11-N to 13-1 - 13-n device, allocate the specified number and confirm that it belongs to the ordered array by the presence of the output code and synchronization pulse at the output 14 of the device. If there is no such number, then at the output of block 8 there is a level of logical zero and the elements AND P-1 - - AND 11-N, I-12 will be closed for transferring information to the output of the device.

The last mode of operation of the device (Table 2, clause 7) differs from the previous one in that the registers 19-1, 19-2 add two checked numbers, multiplexers 21-1, 21 provide the connection of the outputs of circuits 20-1 , 20-2 versus inputs

078

element 1-SHI 24, and its output through a helicopter kop 26 is connected to the output 27 of the unit 10 restrictions. Such a connection leads to the fact that the unity of the Potential at the output 27 of the block 10 of the restriction appears as when the counter code of one or another number is reached. The initial stages of the device operation are to sort the array of numbers with restriction block 10 (Fig. 3 can be considered in the same way. After clearing block 8, inputting numbers of the Maccirea being ordered and switching the device to output mode, the required output mode is set. For In this case, counter 3 is used to record the minimum or maximum number of intervals when deriving numbers belonging to or lying outside the specified interval and checking membership or excluding one number and the emphasis of the finished array. page 32-1 is used to record the second interval number, register 32-2 is required to store the selected operating mode. Comparison circuit 33 compares the numbers on the code of counter 9 and added to register 32-1, multiplexer 34 switches the outputs of comparison circuit 33 at the output of the device, the EXCLUSIVE OR 35 element is used as a controlled inverter (Table 5).

Table 6 shows the installation options for the output numbers.

. The first option (Table 6, p. 1) of the output mode is provided by setting the corresponding (Table 6, column 7) states of the counter and the state of the signal at the output 5 of the device (Table 6, column 4). Register 32-2 (tab. 6, column 4) controls the operation of the multiplexer FOR, connecting the logical unit from input A1 of multiplexer 34 to output 3, and direct signal transmission from its output through controlled inverter 35 to unit 10 restrictions (Fig. 3).

 Thus, the limiting unit is practically disabled and permits the output of all the numbers in the array, since a single potential is established at its output regardless of the state of the signals at inputs 28 and 29. Next, the device operation when outputting all the numbers of the ordered array is similar to the one discussed above.

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The second option (Table 6, p. 2) is set by recording the maximum and minimum interval numbers, either b counter 9, or in register 32-1 | (table 6, column 5, table 6, column 7) and connecting the outputs or, and to the output of block 10, restriction 1IA.

The operation of the device in this case differs from that considered in that the counter 9 begins its operation not from the zero or single codes, but from the minimum or maximum number, starting immediately from the numbers of the given interval. At the same time, in comparison with the above described analogous case, the response speed is increased in deriving the numbers of a given interval. i The third and fourth options Kabbl. 6, p. 3, tab. 6, p. 4) are provided by recording in register RG, 32-1, corresponding to the setting of the initial code of the counter 9 (Table 6, columns 4, 7) and input 5 of the device

; and connecting the outputs or

comparison circuits 33 through multiplexer 34 and an EXCLUSIVE OR circuit to the output of the limiting unit 10, which is done by installing the corresponding state of register 32-2 (Table 6, column 6). In this case, the comparison circuit, depending on the state of the signals at inputs 28 and 29, either permits or prohibits the output of array numbers.

The installation of the following two variants of the device operation is provided by connecting the output of the circuit 33 to the output 36 of the limiting unit 10, either through an inverter or directly, which is done by setting the codes of the corresponding tab. 6, columns 4-7, p. 5, 6..

In this case, in the case of (tab. 6, p. 5), the controlled inverter 35 operates in the inversion mode, prohibiting the passage of the code from the output of the counter 9 through the elements 11-1 - 11-N to the outputs 13 of the device.

Claims (3)

1. A device for sorting an array of numbers containing a switch, 50 five 0 0 five 0 5 10710 reversible counter, memory block, group of N elements AND, (N is the size of the binary numbers being sorted), element AND, the information inputs of the device are connected to information ifliOHOHMMH inputs of the reversible counter, the control input device I / O is connected to the selection input the mode of the memory block, the outputs of the bits of the reversible counter are connected to the address inputs of the memory block and the first inputs of the corresponding elements AND groups, the second inputs of which are connected to the output of the memory block and connected to the first input of the element AND whose output is a synchronization device input, the outputs of elements AND groups are information outputs of the device, characterized in that, in order to expand the functionality by selecting sorted numbers according to given characteristics, a restriction block and a delay element are introduced, and the inputs for specifying the device characteristics are connected to information the inputs of the switch, the control input of which is connected to the input Record of the device, the input Increment-Slamming of the device is connected to the input of the selection of the reversing mode About the counter whose information inputs are combined with the corresponding inputs of the first group and information inputs of the limiting unit, the information inputs of the second group of which are connected to the corresponding outputs of the bits of the reversible counter, the first output of the switch is connected to the installation input in O of the memory unit, the second output of the switch is connected to Record reversible counter and through the delay element - with the input Record of the memory block, the third, fourth and fifth outputs of the switch are connected respectively to the first, second and third The control inputs of the limiting unit, the switch output are connected to the installation input of the reversible counter in O, and the seventh output to the clock input of the reversible counter and the second input of the And element, the third input of which is connected to the output of the restriction unit and . 2. The device according to claim 1, about tl and which is so that the block limit ei1 The instructions contain pinned, second and third registers, the first and second 4JI comparison circuit, the first, second and third multiplexers, the AND element, the AND-NOT element and the SH-NOT element, the first group of information inputs of the restriction block is connected to the corresponding combined i-inputs (i 1.,. N) of the first, second registers and k-inputs (k I.,. 6) of the third register, the second group of information inputs of the limiting unit is connected to the inputs of the first groups of the first and second comparison circuits, the groups of inputs of which are connected with outputs of the corresponding ne bits The first and second registers, the first, second and third control inputs of the restriction block are connected respectively to the inputs of the first, second and third registers; the outputs of the first and second comparison circuits are connected respectively to the first, second and third information inputs of the first and second multiplexers; the fourth inputs which are connected to the input of a logical unit of the device, the first and second, third and fourth, fifth and sixth outputs of the third register are connected respectively to the control inputs of the first, second and the third multiplexers, the outputs of the first and second multiplexers are connected to the corresponding combined first and second inputs of the AND elements, the OR element and the OR-NOT element, the outputs of which are connected to the corresponding 07 .12 Pukimyi JI phocons and p inputs of the third multiplexer, the output of which is the output of the limiting unit, 3. The device according to claim 1, characterized in that the restriction block contains the first and second registers, the comparison circuit, the multiplexer, the EXCLUSIVE OR element, the first group of information inputs of the restriction block is connected to the corresponding i-th inputs of the first register (i 1 , 2 ... N) and 1 inputs (1 1,2,3) of the second register, the first and second control inputs of the control unit are connected respectively to the recording inputs of the first and second registers, the second group of information inputs of the restriction unit are connected respectively to the first group The input of the comparison circuit, the second group of inputs of which are connected respectively to the outputs of the first register bits, the outputs of the comparison circuit are connected to the first, second and three TbeNfy information inputs of the multiplexer, the input of the logical unit of the device is connected to the fourth information input of the multiplexer first and second outputs of the second register connected to the first and second control inputs of the multiplexer, the output of which is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the third you during the second register, the output of the EXCLUSIVE OR element is the output of the limiting unit. 4O ti u o a "7 and fО ex s to and X with about about 1 about oh oh TaVlipa 2 “Yr.