SU1462425A1 - Arrangement for controlling regeneration of dynamic memory with free zones - Google Patents

Abstract

The invention relates to computing and can be used in the construction of storage devices based on semiconductor dynamic memory elements. The purpose of the invention is to increase the speed of the device. The device contains a zone counter 1, a memory block 8, an address counter 2, a synchronization block 3, a record 4 input, a confirmation signal output 5, a regeneration pulse output 6, 7 least significant address outputs, trigger 9, mode input 10, output 11 regeneration requests, address inputs 12, address outputs of the 13 highest bits. In the external memory access mode, the upper boundaries of each of the dynamic memory zones are recorded in the memory block 8. In the regeneration mode, the lower bits of the address of the zone boundary defined by the counter 1 are transferred from the memory block 8 to the counter 2. addresses to the zero state in which the loan signal is generated, which enters block 3. The state of the counter 1 is changed, and the device proceeds to a similar search of the addresses of the following zones. Upon completion of the regeneration of the last zone, the counter 1 generates a loan signal, resetting the flip-flop 9 and transferring the device to the call-in mode. 4 il. (L

Description

ABOUT)

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The invention relates to computing and can be used in the construction of storage devices based on the elements of a semiconductor dynamic memory.

The purpose of the invention is to increase the speed of the device.

Fig, I presents the function

laziness at input 1; 2, the switching sequence of the counter 17; a-; k - signals at the first to third outputs of the decoder 18 § o.- confirmation signal at the direct output of the trigger 19; C - the signal of the reverse transfer counter 2 at the input of 3.2; k is the output state of trigger 20; l - signal installation

nal device diagram; in FIG. 2, the function of counter 2 is at output 3.9; m - signal

pioneer sync block

in reapizovanny version of the device;

Fig, 3, 4 - timing charts l

work respectively device and

block sync.

15

decrement counter 1 output 3.7.

The device is implemented to control the regeneration of a dynamic memory with a seven-bit line regeneration address divided into 8 zones. The transition from zone to zone is determined by switching the three most significant bits on the second output of the address memory block 8. Enumerating line addresses inside a zone — by switching the four bits of counter 2,

The device contains (FIG. 1) a zone counter 1, an address counter 2, a synchronization unit 3, an input 4 records, a confirmation signal output 5, an output 6 for regeneration pulses, 7 least significant address outputs, a memory block 8, a trigger 9, an input 10 mode, output 11 of the regeneration request, and, the crack inputs 12 and the address outputs of the 13 most significant bits,

The synchronization unit 3 (FIG. 2) contains a generator 14, elements 15 and 16, a counter 17, a decoder 18, triggers 19. and 20, switches 21 and 22,

In FIG. 3, the following is indicated: a - signals for recording the address of the upper boundary of the zone, coming from the processor at input 4. j S - signals of the increment counter 1 from output 3.4 of the synchronization unit 3; L- signals to write to block 8 of memory a, the CPUs from the output 3.8 of block 3; g - sequence of postings: and addresses to input 12; - signal to set the regeneration mode at the input 10 ;. e - trigger output 9 - regeneration request signal at output 11; W - signals of the regeneration and decrement of the counter 2 addresses at the output of 3.6 block 3; —sequence of enumeration of the lower-order bits of the regeneration line addresses by the counter 2; , C -. The signal of reverse transfer of counter 2; K - signal to install counter 2 from output 3.9 of block 3; l signal decrement of counter 1 from the output of 3.7 block 3.; m is the sequence of over-switching the states of counter 1; n is the loan signal of counter 1, o is the determination of the information set at the output of the address memory block 8,

 FIG. 4 denotes: q — the signals of the synchronous generator 14 of the synchronization unit 3; 5 - regeneration request signal at input 3.3; B - control signal

decrement counter 1 output 3.7.

The device is implemented to control the regeneration of a dynamic memory with a seven-bit line regeneration address divided into 8 zones. The transition from zone to zone is determined by switching the three most significant bits on the second output of the address memory block 8. Enumerating line addresses inside a zone — by switching the four bits of counter 2,

The device works in the following way.

In the mode of external calls to the dynamic memory at the input 4 of the device, the zone boundaries are recorded (Fig. 3a). According to them, the synchronization unit 3 generates at the output 3,4 an increment of the zone counter 1 (Fig, BZ) and at the output 3, 8 is the write signal to the memory block 8 of FIG. 36; For the first of the increment signals, counter 1 is from the state n (All units code), where n + 1 is ko

five

0

The number of zones in which it was installed at the end of the regeneration mode is set to the zero state (fig. 3m). At the address specified by the state of the counter 1 after the increment, the addresses of the upper boundaries of the zones are recorded in memory block 8 (fig 32, o), which at input 12 is accompanied by a control signal at input 4,

The lower boundaries of the zones are determined by 5 for the three most significant bits of the line regeneration address in the zero state of its four lower bits, Tp igger 9 in the external access mode is set to the zero state (Fig, i 39), the regeneration address counter 2 generates a transfer signal (fig, zi).

After recording the addresses of the zone boundaries, the device is transferred to the regeneration mode of the signals from the input W (Fig. 3a), according to which the trigger 9 is set to one (Fig. 3e). The synchronization unit starts to generate regeneration pulses from its output 3.6 (Fig. ЗЖ), By the signal of transfer

0

five

counter 2, block 3, output 3.9, the signal of setting counter 2 (Fig. GC), coinciding in time with the first of the B decrement of counter 2 (fig, ZH), and the state of the four lower bits of the output information of block 8 is entered into counter 2 memory (Fig. 3). Then counter 2 decrements1462425

issues (fig.) a trigger 19 is set (fig. 4) - a confirmation signal is issued. He through the element And 15 sets the counter 17 to the zero state, and the generation of control signals is blocked. The confirmation signal removes the signal at input 3.1, which, in turn, resets

til before the transition to the zero state - IQ trigger 19.

in which it generates a reverse transfer signal, for which the synchronization unit 3 issues from its output 3.7 the decrement of the zone counter 1 (Fig. Zl). The switching of the counter I (fig. 3 / m) from the memory block 8 selects the address of the next zone boundary (.fig, 3o). The g-backed-off address bits are then rewritten into counter 2 and the search for the lower-level address zone begins.

Counter 1 is decremented to set to the zero state, by which a transfer signal is issued from

20 to the outputs of 3.7, 3.9 (Fig. 4l, l). with a single state of flip-flop 20 (FIG. 4k), flip-flop 20 is set by the transfer signal of counter 2 at output 3.2 and is reset by the falling edge

(Fig. Zn). This is the state of the corresponding 25 control signal from the first decipher of the last of the affected dynamic memory zones. After iterating through its lowercase addresses, the next decrement signal is issued, counter 1 is set to the n state, and its transfer signal is reset, and trigger 9 is reset by this reset (Fig, Ze, n). The further output of regeneration pulses and the signals of the installation and decrement of counters 1.2 is blocked, Counter 1 remains in the n state, and counter 2 is in the zero state and generates a transfer signal. The zero state of the trigger 9 is the request to perform the regeneration. It may give new boundaries of zones,

The synchronization unit 3 operates as follows.

The outputs from the generator 14 output (FIG, 4o () are fed to the counting input of the counter 17, If there is a request for regeneration (FIG, 45), and the control signal from output 3.1 of the block 3 (FIG, 4b) from the counter 17 is reset and the synchronizer recalculation starts (Fig. 4, k). By resetting the signal at the output 3.3, the counter 1 7 is reset and the signals from the outputs of the switch 2 and the element are blocked

30 i 16.

Thus, the device, over the specified boundaries of the involved dynamic memory zones, conducts its line-by-line regeneration without spending time on searching for unused addresses. In this case, a reduction in the time of memory storage by regeneration is achieved and thus more efficient use of computer time, Q. So, if at 128 line addresses only the last column of memory is used, then for its regeneration in the device it is determined in the first selection of address memory block.

45

P-rmula of the invention

A device for controlling the regeneration of a dynamic memory with free pulses (Fig. 4-2.). According to the state of the counter zones, which contains the memory block, the synchro 17 block, the decoder 18, gated by the sync pulse, produces control signals at its outputs (Fig. 4a-g). The control signals from the two first outputs of the decoder 18 (FIG. 34, e) through the switch 22 arrive at the outputs 3.4 and 3.8. The signal from the third output of the decoder 18

55

the synchronization clock, the address counter, the setup input and the transfer output of which are connected respectively to the first output and to the first input of the synchronization unit, the second input of which is the device recording input, the second output of the synchronization unit connected to the recording input of the memory unit, the reset from counter 17 is also removed on a signal from input 3.3 of operation in the regeneration mode. In this case, the flow of control signals to the outputs 3.4, 3.8 is blocked by the absence of a signal at input 3.1, and to the output 3.6, regeneration pulses are sent through the element 16 (Switchgear 4g), the switch 21 gives control signals

to the outputs of 3.7, 3.9 (Fig. 4l, l). in the case of the single state of the trigger 20 (FIG. 4k), the trigger 20 is set by the transfer signal of the counter 2 to the output 3.2 and is dropped by the falling edge

the control signal from the first decoder (Fig. 4, k). By resetting the output 3.3 signal, the counter 1 7 is reset and the signals from the outputs of the switch 2 and the element are blocked.

0 i 16.

Thus, the device, over the specified boundaries of the involved dynamic memory zones, conducts its line-by-line regeneration without spending time on searching for unused addresses. In this case, a reduction in the time of memory storage by regeneration is achieved and thus more efficient use of computer time, Q. So, if at 128 line addresses only the last column of memory is used, then for its regeneration in the device it is determined in the first selection of address memory block.

five

P-rmula of the invention

A device for controlling the regeneration of a dynamic memory with free zones, comprising a memory block, a syn

five

synchronization, the address counter, the setup input and the transfer output of which are connected respectively to the first output and to the first input of the synchronization unit, the second input of which is the recording input of the device, the second device for controlling the regeneration of the dynamic memory with free zones, containing the memory unit, block blue

The sync block output is connected to the memory block write input, the input (and} input inputs and outputs of the first group of which are respectively the address inputs and the high-order address outputs of the device; the third output of the synchronization block is the output s; About the fact that, in order to improve the speed, it contains a zone counter and a trigger, the installation input of which is the input of the device key, the output of the trigger and the third podyutyuchen

the input of the synchronization unit, the fourth output of which is the output of device regeneration pulses and connected to the counting input of the address counter, which inputs are connected to the information outputs of the second memory block group, the address inputs of which are connected to the information outputs of the zone counter, whose loan output connected to the reset input of the trigger; the fifth and sixth outputs of the synchronization unit are connected to the addition input and to the

input subtraction zone counter.

"W" about hell i "; Jt "s

Claims (1)

The claims are an address counter whose installation output transfer is corresponding to the first first input of the block, the second input of which is a device for controlling the regeneration of dynamic memory with free zones, containing a memory block, a synchronization block, a new input and connected to the output and synchronization, is a device recording input, swarm the output of the synchronization unit is connected to the recording input of the memory unit, the information inputs and outputs of the first group of which are respectively address inputs and address outputs of rshih discharge device? the third output of the synchronization block is the output of the signal confirming the recording of the address of the zone boundary, which means that, in order to improve performance, it contains a zone counter and a trigger, the installation input of which is the input of the device mode, the trigger output is the output of the device regeneration request and is connected to the third input of the synchronization unit, the fourth output of which is the output of the regeneration pulses of the device and, _{from the} keys, to the counting input of the address counter, the information inputs of which are connected to the information outputs of the second group of the memory block, whose address inputs are connected to the information outputs of the zone counter, the loan output of which is connected to the trigger reset input, the fifth and sixth outputs of the synchronization block are connected respectively to the addition input and to the 15th subtraction input of the eon counter. FIG 2 Wh "oh sh" b V "j y