SU1481851A1 - Unit for locating free memory areas - Google Patents

Abstract

The invention relates to computing and can be used in the construction of storage devices. The aim of the invention is to improve the speed of the device. The device comprises a memory block, an address converter, a register and an encoder for the group of upper address bits, an address converter, a register and an informer for the group of lower address bits, the first and second switches. The device works in the modes of reset, loading, exchange of cleaning, search and search with loading. The purpose of the invention is achieved in that, in the search modes in the device, only those feature bytes are analyzed that contain the attributes of the free zone. 1 Cpf-ly, 2 ill.

Description

The invention relates to computing and can be used in the construction of storage devices.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a functional diagram of a device for searching for free memory areas; in fig. 2 - functional scheme of the first address translator.

The device contains the first address converter 1, register 2 and encoder 3, memory block 4, second address converter 5, register 6 and encoder 7, switches 8 and 9, address outputs 10 and 11, synchronous inputs 12 and 13, reset input 14, address inputs 15, inputs 16 and 17, respectively, search and clean and exit 18 stop the device

The operation of the device is considered on the example of addressing memory zones on seven address buses (Ast - 4 bits, A Mill - 3 bits). For this case, the registers 2 and 6 are 8 and 16, respectively, the memory block 4 is an 8x16 matrix.

The device works as follows.

A set of control and sync signals sets the device operation in reset, load, exchange, clear, search, and search with load modes.

The reset mode is implemented to free all the memory areas and is set by the Reset signal. In this case, all the ASTs are successively entering the device at the input 15, followed by

ace

oo ate

by signal Strobe 2. By reset signal, all bits of registers 2 and 6 are set to the logical state O, and the outputs of the decoder 19 of the converter 1 are set to 1. With these levels present, the corresponding inputs of the equivalence elements 20 of the converter 1 establish O and JQ is recorded at all addresses of memory block 4. These addresses are given by signals Аст, which from input 15 through switch 8 arrive at the address input of block 4.

As a result, in all bits of the 15 all bytes stored in block 4, and in all bits of the second register 6, the size of which corresponds to the number of these bytes, the occupancy symptoms are reset.

In boot mode, the processor loads information into certain memory areas. The mode is set by the level O at the inputs 14, 16, and 17 of the reset, and ends up 1, the electronic and 1 are triggered through the switch 9 and the permitting input registers the entry into it on the back. Gate 2 of the output transducer of converter 5, which is similar to the operation of converter 1. Thus, with a full filled byte, signs, an additional sign is established in accordance with this bit of register and

When loading the last zones (code 1111111), additional recognition is established in the last of bit 6, the encoder 7 sets up a request, and a stop signal is output to output 18, with no free sockets stored in block 4, with signs busy zones, gist 6, bytes are marked,

Strobe 1, 25 and clock signals are occupied by these features. Gate 2, accompanying the arrival of Ast and Al. According to Ast from block 4, the corresponding feature byte is selected and the corresponding decoder 19 30 of the second converter 5 is set to O. The corresponding decoder 19 of the first converter 1 is set to O according to Am. By Strobe 1 byte,

In the mode of information exchange between the processor and the loaded zones, from the input 15 through the switch, outputs 10 and 11 are transmitted to the AMA. At the same time, they do not match the control signals.

In the cleaning mode, the process waits for the loading of a certain memory zone, and it is closed in the devices. The mode is set at the signal. The input signal is cleared at the output of the switch 9 of the request signal; the signal is connected to the request of request 3, formed according to the state of 2 of the command Ast, AM is given by the clock St Gate 2. By the Gate the corresponding bar is entered by Strobe 1 Installed in the resolution 19 of the converter 5 is current. Ast, and the discharge de desh converter 1, respectively Addl. If the level of the encoder coincides with the level of 1, the employment will be appropriate. sets O on his 55 and he is storing memory by strobe 2. The outputs of the other 20 preserve the previous one. If register 2 is completely

selected from block 4 by AGT, records

The first register 2 coincides with the sign of the free zone, also the level O and coming from the register, at the output of the element 20, the sign of the level 1 occupancy is formed, which is recorded in block 4 via Gate 2. Since the other bits of the decoder 19 are in state 1, when it coincides with the level O, the output of element 20 is set to O, and if it coincides with 1, it is 1, and in the other bits of the byte, the previously established features are confirmed.

When installed in the byte of the last sign for the zone address code, for example, 0000111 is set to O, the 8th bit of the decoder 19 of the converter 1. By Gate 1, register 2 is set to the state established by the previous load. As a result, the outputs of all elements of the 20 transducer 1 installed

1, the element And 21 and 1 is triggered through the switch 9 to the enable input of register 6, allowing writing to it on the falling edge. Gate 2 of the output state of converter 5, which is formed similarly to the operation of converter 1. Thus, when a certain byte is completely filled with signs of occupation, an additional sign of occupation is established in the corresponding byte of register bit 6.

When loading the last of the free zones (code 1111111), an additional employment condition is set in the last of the bits of register 6, the encoder 7 sets a request signal, and a stop signal is sent to the device output 18, indicating that there are no free signals. block 4, the signs of zones are fixed, and in register 6 bytes are marked,

occupied by these signs. 0

five

five

about

In the information exchange mode of the processor with loaded memory zones, from input 15, through switch 8, the codes Аст, АМА о are transmitted to the outputs 10 and 11. At the same time, they are not accompanied by control and synchronization signals T ;. of

In purge mode, the processor releases certain areas of memory from loading, and this is fixed in the device. The mode is set by setting the Purge on input 17 signal. Instead of the request signal from Converter 1, the output signal of encoder 3 is connected to the output of switch 9, which is generated according to the state of register 2 o Task Ast, AMA is accompanied by a synchronization signal Strobe 1, Strobe 2. According to Ast from block 4 the corresponding byte is selected, which is entered by Strobe 1 into register 2. They are set to 0 in the decoder section 19 of the converter 5, the corresponding one. Ast, and the decoder bit of converter 1, corresponding to Addl. If the level O from the decoder with the level 1 of the feature of coincidence coincides, the corresponding element 20. sets O on its output, 5 and it is entered by strobe 2 into memory block 4. At the outputs of the other elements 20, the previous state is maintained. If register 2 is fully occupied by

busy signs, the encoder 2 vtra-.batyvaet request, allowing writing to the register 6 back edge Gate 2 of the state of the converter 5 - the bit of register 6, corresponding to the byte in which the busy feature is removed, is set to O. After this is removed and Stop. The request signal of the converter 1 is in this mode at O, because when clearing one of the bits of the information output of the converter is necessarily reset.

The search mode of the free zone is specified by the Search at input signal 16. According to it, switch 8 connects information output of encoder 7 (Ast) to output 10, and encoder 3 (Am) connects output 11 to output 11. The Asg code is the first of the free zones defined by the encoder 7 according to the state of register 6. According to this

 ST

feature byte is selected from

block 4, and the Strobe 1 signal is written to register 2 by the signal, and according to its state, the encoder 3 determines the AML. Gate 2 is not issued in this mode.

In the free zones search mode with their subsequent loading, the search signal is accompanied by both sync signals. Attributes of an occupation are established similarly to work in a loading mode. The free zone address is determined by the Strobe 1 signal. By the falling edge of the Strobe 2, a new state of the converter 5 is entered into register 6 — the Act-next free zone is set, i.e. the duration of the issuance of the address of the free zone corresponds to the gap between the leading edge of Gate 1 and the back Gate 2.

Thus, the device records the addresses of free zones and for their search analyzes not all bytes of signs of another sequence, but only those that contain signs of a free zone. With an increase in the number of occupied zones, this allows, in comparison with the known device, to significantly speed up the search for a free zone.

Claims (2)

1. A device for searching for free memory areas containing a memory block whose information inputs are connected to the outputs of the address code of the first address converter, and the outputs are connected to the information inputs of the first register, the synchronous input and the reset input of which are respectively the first synchronous input and reset the device, the register outputs are connected to the inputs of the first encoder, the recording input of the memory block is the second synchronized input of the device, characterized in that, in order to improve speed, a second input is entered into the device th address transformer, second register, second encoder, first and second switches, the outputs of the address code of the first and second encoders are connected respectively with the high and low bits of the information inputs of the second group of the first switch, the information inputs of the first group of which are the high and low bits The device address addresses, the high-order outputs of the first switch are the high-address outputs of the device address, and are connected to the address inputs of the memory unit and the second converter the addresses whose information inputs are connected to the inputs of the second encoder and the outputs of the second register, whose information inputs are connected to the outputs of the second address converter, the low-order outputs of the first switch are the low-address outputs of the device address and connected to the address inputs of the first address converter, information inputs which are connected to the outputs of the first register, the control input and the output of the occupation attribute of the first address converter are connected respectively to the reset input The device itself and with the second information input of the second switch, the first information input and output of which are connected respectively to the output attribute of the request of the first encoder and to the control input of the second register, the reset input and synchronous input of which are connected respectively to the reset input and to the second synchronous input of the device, controlling the inputs of the first and second switches are respectively the inputs of the device search and cleanup modes, the output of the second encoder request feature is the output of the stop device. 2. The device according to claim 1, wherein the first address transformer comprises a decoder, the outputs of which are connected to the permissions of the inputs of the corresponding equivalence elements, the second inputs of which are information inputs of the converter, and the outputs are outputs of the address code of the converter and connected to the inputs of the element And, the output of which is the output of the attribute of the converter, the information and control inputs of the decoder are respectively the address and control inputs of the converters