SU1251183A1 - Device for controlling regeneration of information in dynamic memory - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-speed storage devices of large volume based on the elements of semiconductor dynamic memory. The purpose of the invention is to increase the speed of the device. The device contains a counter, an address multiplexer, an address code converter made from a decoder, OR elements and AND elements, a memory block, a register, and a priority encoder. The device operates in two modes: registration and external access. In the registration mode, the address multiplexer connects the outputs of the counter state to one output of the device and the information outputs of the priority encoder to the other outputs of the device. During the regeneration cycle, the dynamic memory is selected by line addresses that did not receive external access, and by addresses corresponding to the last bits of the sample signs, regardless of whether external access occurred on them or not. 1 hp f-ly, 4 ill., 1 tab. (C (L SL EO

Description

The invention relates to computing technology and can be used in the construction of high-speed mass storage devices based on the elements of semiconductor dynamic memory.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a device for controlling the regeneration of information in a dynamic memory; in fig. 2 is a block diagram of an address code converter; in fig. 3 and 4 are timing diagrams of the device operation in regeneration and external circulation modes.

The device contains (FIG. 1) a synchronization block I, an AND 2 element, a counter 3, an address multiplexer 4, an address code converter 5, a memory block 6, a register 7, a priority encoder 8 and a NOT element 9. In FIG. control 10 and address 11 device inputs and address outputs 12 and 13 of the device.

The Converter 5 address codes (figure 2) contains the decoder 14, the elements of the SLI 15 and the elements. And 16.

In Figures 3 and 4, the following notation is adopted: a, b, c, d are the outputs of block 1; d, e - lower bits, respectively, of outputs 12 and 13 of the device; g, 3, y — respectively, the outputs of the first, second, and seventh bits of the decoder 14 of the converter 5; l, m, n - respectively, the outputs of the first second and seventh bits of block 6; к - output of the eighth bit of the decoder 4; o - output request of the priority encoder 8; p is the output of the element And 2; p - output transfer counter 3.

In this case, a device for controlling the regeneration of information in a dynamic memory is implemented on elements of the 565 series type, in which 128 columns are polled for seven bits of address addresses for regeneration.

Block 1 is implemented according to the time diagrams of its operation and can be performed, in particular, on the basis of a standard ROM, and the encoder 8 on the 155IV circuit.

In the course of 10, signals are received for requesting external access, clocking, start and end of regeneration, at input 1 1 - lowercase addresses for external access. From outputs 12 are set

the upper bits of the dynamic memory address line addresses (AR7-AR4), from outputs 13, the lower ones (AR3-AR1).

The device works as follows.

. Block 6 is organized as a 16x8 matrix. By external reference, addresses AR3-AR1 are converted into data and written into block 6 at address AR7-AR4.

Thus, in block 6, the signs of external calls are remembered at addresses AR7- -ARI. In the regeneration mode, from block 6, information bytes are sequentially selected, according to the state

which, the priority encoder 8 sets the addresses of the AR3-AR1 to be regenerated by the dynamic memory columns. The addresses AR7-AR4 and the information bytes of block 6 are given by the counter 3,

The signal from the output of the block I (Fig. 3a) sets the level O of the regeneration mode, and the level i the mode of external access.

In the regeneration mode (FIG. 3), the address multiplexer 4 connects the outputs of the state of the counter 3 to the outputs 12 of the device, and the outputs of the priority encoder 8 to the outputs 13.

In the information bytes selected from block 6, 1 corresponds to the sign of external access, O - its absence (Fig. Zl-n). According to the clock signal (fig. 3) the state of the outputs

unit 6 is entered into register 7. According to the state of the outputs of register 7, the priority encoder 8 generates a code corresponding to the first of O at the outputs of the register 7. The decoder 14 of the converter 5 at its output corresponding to the state generated by AR3-AR1 sets 1. the records (FIG. 36) in block 6 are assigned the status of the outputs of converter 5 (FIG.

Зж-к). On the next sync signal

the state of register 7 is changed and the priority encoder 8 generates a code corresponding to the next of O in the bits of the 6 byte selected from the block.

The next column of the dynamic memory is regenerated by the code corresponding to this byte and its address in block 6. The levels O on the other outputs of the decoder 14 do not erase the sampling signs, since the outputs of the register 7 are connected to the outputs of the decoder 8 through the elements OR 15 of the converter 5

  S

at the outputs of the register 7 code I 1 1 I P i. Since code 111 at the output of the priority encoder 8 corresponds to both code 1 1 1 11P O and code 11111111 at its information inputs, and 1 at its request output is reset with input code 11111111, in block 6, only the first seven of each eight line addresses. By resetting the request signal of the priority encoder 8 (FIG. 3), the outputs of converter 5 are blocked by elements of type 16. At outputs of converter 5, O is set. On a recording signal, this signal 5 is also cast by the selected 6 bytes from the block. Then, by coincidence, O. at the output of the request and the signals at the output of block 1 (FIG. 3b), the element AND 2 generates a signal for the modification of counter 3 (FIG. 20 Zi) and the state AJR7-AR4 changes (FIG. 10). On the next clock signal, the state of the next byte selected from block 6 for the new AR7-AR4, js is entered into register 7 by this time, and the byte analysis starts again. The regeneration limit is determined by the transfer signal of counter 3 (Fig. 3). Thus, during the regeneration cycle, the dynamic memory is selected by Q line addresses, which were not externally referenced, and at addresses corresponding to the last bits of the sample signs, regardless of whether 2 external references occurred (in this case,

- for every eighth line address) or not. At the end of the regeneration cycle, all features of the sample are discarded. 40

When the supply voltage is supplied, the cells of the block 6 are set arbitrarily; for their reset requires one cycle of regeneration. This does not affect the performance of the system, since when the voltage is applied, the dynamic memory goes into working memory after 8–10 cycles.

Plot 1 in FIG. 3 displays the regeneration control process in the absence of $ 0, there are no sampling signs in all bits of the 6 bytes selected from the block.

Output states of device nodes

Tact

1111111 0001 001 00000010 1111111 1 SHIP 0001 111 10000000 0000000 O

I8-j4

Plot JI in FIG. 3 displays the regeneration control process in the absence of a sample feature only in the second byte. Switching the output states of the device blocks in this case is presented in the table

The Itl portion of FIG. 3 displays the regeneration control in previous outward appeals to all line addresses. Only AR7-AR4 is switched; AR3-AR1 is permanently in state 111. The request signal is constantly cleared and the regeneration counter 3 is modified by each signal from the output of block i1 (Fig. 3 I).

In the external access mode (Fig. 4), the address multiplexer 4 connects the high-order bits of the address input 11 to the device outputs 12, and its low-order bits to the outputs 13. The external address is set at input 11 by signals from the output of block 1 (Fig. 4c, d, e). By signal 1 at the other output of block 1, counter 3 is reset, and the output of the request of the priority encoder is set to 1. By external access from block 6 reset to zero during the regeneration cycle, a byte is selected for the line address addresses AR7-AR4 (Fig. 4n-n). Then, using the sync signal from the output of block 1 (Fig. 4d), the selected byte is entered into register 7. Transducer 5 transmits this byte to the information inputs of block 6, and the bit corresponding to the AR3-AR1 state is set to 1 (Fig. 4g ). According to the recording signal (Fig. 4b), the newly formed byte is entered into block 6, after which a byte is selected from it according to the following state AR7-AR4. So, the cells of the block 6 reset to zero during the regeneration cycle are set by line address external calls to 1.

When external calls are made to all line addresses, all cells of block 6 are set to 1, and in the regeneration mode, only the addresses of the information bytes of the block (AR7-AR4) are searched.

13

14

Claims (2)

Invention Formula 1, A device for controlling the regeneration of information in a dynamic am, containing a counter, an address multiplexer, a memory unit, an element and a synchronization unit, the first input of which is the control input of the device, the first output connected to the reset input of the counter and the control input of the address multiplexer , the second output of the synchronization block is connected to the recording input of the memory block, the third output is connected to the first input of the And element, the bypass of which is connected to the counter input of the counter, the transfer output of which is connected to the second input of the block The synchronization and the counter status outputs are connected to one of the information inputs of the address multiplexer, whose address inputs are the device address input, and the outputs are device address outputs, with one of the address multiplexer outputs being connected to the address inputs of the memory block, different so that, in order to increase the speed of the device, a register has been entered into it, a priority encoder, an NOT element and an address code converter, whose address inputs are connected to other outputs of the address multiplex litter and outputs - to the data inputs of the memory unit, the outputs which is connected to the information inputs of the register, the synchronous input cat6ro1 is connected to the fourth output of the synchronization unit, and the outputs are connected to the information inputs of the address code converter and the priority encoder, the control input of which is connected to the first output of the synchronization unit, the information outputs are connected to other information inputs of the address multiplexer and the request output is connected to the control input of the address code converter and is NOT connected to the second input of the element I. 2. The device according to claim 1, which is based on the fact that the address code converter contains elements SH, elements AND and a decoder, the outputs of which, except the last, are connected to the first inputs of the elements OR, the outputs of which are connected to the first inputs of elements AND The outputs of which are the outputs of the converter, whose inputs are the inputs of the decoder and the second inputs of the AND elements and the OR elements. srie.2. j Well, to -. I.-....- .Ill ... 1 and Ub X5W f co o 4 Editor A. Ogar Compiled by V. Rudakov Tehred I. Gaidosh Proofreader M. Maksimishinets Order 4419/51 Circulation 543. Subscription VNIIPI USSR State Committee for inventions and discoveries II3035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4