SU1238095A1 - Control device for selector channel - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the development of a computer I / O system with firmware I / O control. The aim of the invention is to increase the data rate of a channel when working with a data chain by prefetching the next channel control word. The device contains the first and second flag registers, the switch switch, the first and second buffer address counters, the buffer address switch counters, the first and second buffer bytes counters, the buffer byte counters switch, the modification node, the first and second byte counter registers, com. - a byte counting mutator, the first and second comparison nodes, the comparison signal switch, the first second zero nodes of the counter, the first and second zero switches of the counter, the switching unit, the recording node. 11 il. W with (X) 00 about ate

Description

The invention relates to digital computing and can be used in the development of a computer I / O system, in particular, to control the operation of the hardware to buffer the data in the selector channel.

Goal is scorched. - speed increase; per e, naii-H data when working with a chain of data. | ,

The set / goal is achieved by the fact that I during the change of the USK when working with {data transfer channel at the same time can work with two USK. One USK is used for operation by the interface, and the other for operation with RAM.

FIG. 1 is a block diagram of the control device for the selector channel; in fig. 2 - the functional scheme of the first register of features, the second register of features, the first switch {-. kazan switching checkbox software control south interrupt); in fig.3 switching switching flags of the command chain, data chain and suppressing the indication of incorrect length, as well as switching the checkboxes of the write lock and indirect addressing flag; in fig. 4 - .functional circuit of the first counter. Address, second address counter, first switch; in fig. 5 is a functional diagram of a first byte counter, a modification unit, a second byte counter, a second switch) in FIG. b - the first state register of the byte counter, the second state register of the byte counter, the first comparison circuit, the second comparison circuit, the third and quarter switches; in fig. 7 - the first decoder, the second decoder of the sixth and seventh commutator in FIG. 8 is a table of switching the outputs of the unit for setting the exchange modes; in fig. 9 - block assignment of exchange modes; in fig. 10 shows a signal shaper; FIG. 11 - distribution of local memory.

The control unit (Fig. 1) contains the first register 1 of signs, the second register 2 of signs, the first counter 3 addresses, the first counter 4 bytes, the modification block 5, the first register 6 of the byte counter state, the first comparison circuit 7, the first decoder 8, p the second switch 9 flags, the second counter 10 addresses, the first switch 11, the second counter 12 bytes, the second switch 13, the second state register 14 of the byte counter, the second comparison circuit 15, the third switch 16, the fourth switch 17, the second decoder 18, the sixth switch 19, seventh switch p 20, block 21 setting exchange modes, transducer 22, device data bus 23, device information bus 24, device control bus 25, device control input 26, device switching input 27, counter byte bus 28, device address bus 29 , the first control output device 30, the second control output device 31.

The exchange mode setting unit 21 (FIG. 9) contains triggers 32-36, modulo two element 37, AND-OR elements 38-40, first mode output .41, third mode output 42, second mode output 43, allowing output 44 ,

Shaper The 22 entry signals (FIG. 10) contain the triggers 45 and 46, the AND-OR elements 47 and 48, the AND 49 and 50 elements, the OR elements 51 and 52, the second output 53 of the imager, the third output 54 of the imager, the first output 55 of the imager .

The first register of 1 signs (FIG. 2) contains a group of triggers 56 and an AND-OR element 57. The second register of 2 signs contains a group of triggers 58 and an AND-OR element 59. The fifth switch 9 contains an AND-OR element 60, three elements AND-OR 61 (fig.Za) and two elements AND-OR 62 (Fig.36).

The first counter 3 addresses (figure 4) contains a reversible binary counter 63, the element AND-OR 64 ,. element 1 shih 65-67. The second counter 10 of the address contains a reversible binary counter 68 and the element AND-OR 69..The first switch 11 consists of a group of elements AND-OR 70. The first counter 4 bytes (figure 5) contains the reversible binary counter 71, the element 72 ,. element AND-OR 73, elements OR 74-76. The modification block contains adder 77, a group of elements And 78. The second counter of 12 bytes contains a reversible binary counter 79, the element AND 80 of the element AND-OR 81. The second switch

13 consists of a group of elements AND-OR 82.

The first state register 6 of the byte counter (Fig. 6). contains a register 83, an AND-OR element 84. The second state register of the byte counter 14 contains a register 85, an AND-OR element 86. The first comparison circuit 7 contains a group of elements 87 modulo two, the AND element 88. The second comparison circuit 15 contains a group elements 89 add modulo two, the element And 90. The third switch t6 contains a group of elements I-STI 91, the element And 92. The fourth switch 17 contains the element I-IPI 93.

The first decoder 8 (FIG. 7) contains a trigger 94, an AND-OR element 95. The second decoder 18 contains a trigger 96, an AND-OR element 97. The sixth switch 19 contains an AND-OR element 98. The seventh switch 20 contains an AND element SHSh 99 ..

The information bus 24 of the device contains the following lines: 100 — the signal of the microprogram installation of the trigger 87 {101 -, the counter bus} -.

102- signal counter equals

103 — constant bus for modifying the byte counter in a split loop.

The control bus 25 of the device contains the following lines: 104 — channel reset signal, 105 and 106 — sync signals; 107 and 108 - entry signals - 109 - reverse input; 110 is the signal of modification of the buffer address counter, 111 is the signal of modification of the buffer byte counter, 112 is the signal of entry in the divided cycle, 1 13 is the input; 114 —flash data circuit firmware; 115 - signal USK ready; 116 - conclusion; 117 - split cycle is performed.

 The device control input 26 contains the following local memory addressing lines: 118 - write to the seventh local memory cell; 119 — record in the eighth cell of the local memory; 120 — write to the first local memory cell; 121 — write to the second local memory cell.

The first and second 2 registers of signs are intended for storing the flags of two consecutive UICs associated with the flag of the data chain. P nt switch 9 is intended to declare the valid flags from the first

or from the second register of attributes by signals from the outputs of the block 21 specifying exchange modes. The first 3 and second 10 address counters are designed to specify 5 bytes of the byte address in the buffer (more precisely, in the double word of the buffer, for which three bits are enough) when writing to the buffer a data byte from the BUS-A or when reading a data byte from the buffer to 0 SHIN-K. .

Inputs S1, S2 of binary reversible counters are used to set the operating mode of the counter. 00 - storage, .01 adding units by the signal at the 5th input C; 10 - subtraction of a unit by a signal at input C; 11 - entering information from input D by a signal at input C,. .

The first switch 11 is intended 0 to switch the outputs of the first 3 and second 10 address counters to the address bus 29 of the device and then to the buffer, where it determines the byte address of the buffer. The first 4 and the second 12 are five to five bit byte counters are used to count the bytes in the buffer. The second switch 13 serves to switch the outputs of the first 4 and second 12 byte counters to the input of the Q 5 modification unit. The latter serves to modify the first 4 and second 12 byte counters in divided cycles by a constant, which is fed to the information input of the modification block 5 via the bus 103. If the input S1 of the adder 77 (FIG. 5) is

a single signal, then the summation is performed, and if it is zero, then the subtraction. e ..

The first 6 and second 14 registers of the byte counter are intended to display the state of the byte counter located in the local memory on the channel hardware. The entry of information into the registers 6. And 14 is synchronized with entering it into the second cell of the local memory. When performing the input operations, the byte counter status register is compared with the buffer byte counter and their 50

constitution says that all yes.

data in USC are transferred to the channel ..

The size of the byte count register depends on the size of the buffer. For a buffer of sixteen bytes, the 55 byte register of the byte count must be five-byte (0-4). Bus 101 is made in such a way that in bits 0-4 registers

HZ-7 bits are stored in the low byte of the counter and bytes on the local memory, and the installation of bits 0–2 of the state register has resulted in the assembly of all the high byte bits and bits 0–2 of the low byte of the byte counter from local memory, this allows comparison of the byte count of the buffer with the status register of the byte count only after it begins to display the actual value of the byte count from the local one.

The third switch 16 is designed to switch to the bus 28 the byte counter of the outputs of the first 6 and second 14 registers of the byte counter status depending on the output state 41 of the exchange mode setting unit 21. If at the input of peripherals - 20 that in the channel there can be such a state device, the UPR-A signal is pressed, when the byte counter in the local memory is still exhausted, then the signal from the output of the interface control unit arrives, the signal to the switching input 27 of the device and in this case, the outputs of the first 4 or second 12 byte counters of the buffer are switched depending on the output state 41 of the exchange mode setting unit 21.

The channel manager uses information from the output of the third switch 16 to form a constant for modifying the address of the data and a byte counter to form a mask for the operational memory in separate cycles. This same / constant through the bus 103 is fed to the input of block 5.

The first comparison circuit 7 serves to compare the first counter 4 byte buffer with the first register 6 of the byte counter state. The comparison signal from the comparison node output indicates, when inputting, that all data bytes from the peripheral device are transmitted to the channel.

The second comparison circuit 15 serves to compare the second counter of 12 bytes of the buffer with the second register 14 of the byte count.

 The fourth switch 17 serves to select the comparison signal from the outputs of the first 7 or second 15 comparison circuits, depending on the output state 43 of the exchange mode setting unit 21. The first 8 and second 18 decoders are designed to be fixed in

23.8095 .6

signal channel The byte counter is zero depending on the state of the outputs 41 and 43 of the block 21 of the assignment of exchange modes. This signal comes in

5 lines 102 from the channel manager when the second word of the USK with the zero byte counter is read from the main memory to the second cell of the local memory (signal 108),

 About when the second word of the USK with the zero byte counter is sent to the firmware prefetch (during input) in the second cell of the local memory as well as during the last

Section 15 of the cycle, in which the zero byte counter after modification is written into the second cell of the locale. memory (signal 112). The need for decoders caused by.

7

when it stores two signals simultaneously, the counter is zero,

For example, in the pre-sampling before entering the signal Counter is equal to zero for the first USK, this signal can be received for the second USK. The sixth 19 and seventh 20 switches are introduced due to the separation of the signal function. The counter is zero in time. The sixth switch 19 performs switching on the output 43 signal of the unit 21, and the seventh switch 20 performs the switching on the signal 41 from the output of the block 21. The exchange mode setting unit 21 is intended to control the operation of all these units.

All USKs associated with the data chain flag are renumbered, starting with the one in which the data chain flags are listed first, and are assigned the first number (1,2,3,4 ...). The state of the outputs of block 21 determines the following. About at output 41 - working with RAM is under the control of an ACS with an odd number, 1 at output 41.- working with RAM is under the control of an ACC with an even number; About at output 43 - work with the interface is controlled by the USK with an odd number; 1 at output 43 - work with the IDE interface running -USK with an even number

FIG. Figure 8 shows the switching sequence of the outputs of block 21. For input and output, if the channel executes three flagged UCK data chains. First position in the table

shows the initial state of the outputs of block 21, and block 21 enters this state after processing the interrupt in the channel. If more than three CSCs are associated with the data chain flag, then from position 6 the switch unit moves to position 3, etc.,

Shaper 22 shaper is used to generate flush signals at outputs 55 and 53 if the USK prefetch firmware is being executed during input or the data chain firmware is being output. The channel uses eight local memory cells for operation (FIG. 11). The first and second cells are used to store the current USCJ, a third cell — to store the USC address of the seventh and eighth cells — to store the pre-selected USC.

The operation of the control device in the embedded selector channel with firmware is considered. In this case, the bus 23 of the device is connected to the output bus of the device — 25 (FIG. 6).

35

The central processor, the information bus 24 of the device is connected to the output of the channel control device, the control bus 25 of the device is connected to the output of the channel control block 30, the control input 26 is connected to the output of the local block. Channel memory, the switching input 27 of the device is connected to the output of the interface control unit, the bus 28 of the byte counter is connected to the input of the channel control device, the address bus 29 of the device is connected to the data buffer control unit, the first and second control 40 output outputs 30 and 31 The devices are connected to the inputs of the interface control unit.

The channel works as follows.

In the initial state after resetting the channel 45 or after resetting at the start of executing the command chain (signal 104), outputs 41 and 43 of block 21 are in state 01, triggers 45 and 46 of driver 22 are reset. It is considered the execution of three UICs associated with the checkbox of the data chain. The first of them has an input operation.

An I / O operation (in this case, the microprogram starts the initial sampling in the channel and sets the trigger USK ready in the channel control block. The signal 115 is fed to the input of block 21. In block 21, the tenth signal coincides (there is no data chain execution signal 114 ) and the eleventh inputs of the AND-OR 38 signal, the signal from its output switches the trigger 32 to the opposite state (in this case, the O state) via the clock signal 105, and the new clock value 33,36 and the outputs are set via the clock signal 106. 41, 43 blo a switching transition into state 00.

While the channel hardware is performing. the initial firmware sample, if there is a data chain checkbox, proceeds to preselection of the second UIC. Microcommand G-1K7 analyzes the operation code and makes branching in three directions. Further, in the case of input or input, it performs an analysis on a self-defined chain. In the case of a self-defined chain, the prefetch is not performed. Microcommand MK9 reads the first word USK in the seventh

In addition, an input operation is initiated by the co-; local memory cell, MK10 using I / O vypolmandy Start input-nth analysis of the operation code, if the code

output (NVB) .. Firmware, real-operation 08 Transition.in the channel.

the command NVB reads from the operation, the analysis is again performed on a self-test

380958

memory of the first word of the first USK in the first cell of the local memory (figure 1). At the same time, a recording signal 107 is produced, according to which the operation code 5 is entered into the channel and the signal 113 is established. The input is on the control bus 25 of the device, the entry of three lower-order data address bits from the 23-D bus of the device into the first counter 3 addresses (Fig. A), a reset of the first counter of 4 bytes of the buffer is performed (Fig. 5) - zeros are being written into the binary reversal -. c-meter 71 from the output of block 5 of the modification, in which at the inputs of the group of elements And 78 there is no signal 117 split cycle. Then the microprogram reads the second word of the first UCS, at the same time, the entry code 108 will be generated, which is used to enter the first register of features and the first register 6 cf. one hundred bytes counter from bus 101 bus information counter 24

five

0

Next, the firmware starts the initial sampling in the channel and sets the trigger USK ready in the control unit of the channel. The signal 115 is fed to the input of block 21. In block 21, the signals coincide at the tenth (there is no data chain execution signal 114) and the eleventh inputs of the AND-38 element; the signal from its output switches the trigger 32 to the opposite state (in this in the state O) by the sync signal 105, and by the sync signal 106 a new value of rp-iggers 33.36 is set and the outputs 41, 43 of the switching unit are switched to the state 00.

While the channel hardware is performing. the initial firmware sample, if there is a data chain checkbox, proceeds to preselection of the second UIC. Microcommand G-1K7 analyzes the operation code and makes branching in three directions. Further, in the case of input or input, it performs an analysis on a self-defined chain. In the case of a self-defined chain, the prefetch is not performed. Microcommand MK9 reads the first word USK in the seventh

dividing and reading the first word of the USK and analyzing the code of the operative on 08. The MK11 microcommand reads the second word of the UIC into the eighth cell of the local memory, the MK13 sets the trigger 45 to fill the driver 22 with the signal of the microprogram installation 39. These channels and the reset pre-selection trigger 46 generate a signal from output 55, at which the lower three bits of the data address of the preselected USK are entered into the second counter 10 of the address and the second counter is reset to 12 bytes. as indicated for the first address and byte counters.

During the execution of the MK15, the localization block output signal 119c generates an insertion signal 53, which is used to record 2 byte counts in the second register 14 of the counter analysis and the second per gy. During the execution of Shch16, the firmware installation signal 100 from the output of the channel control unit sets the preselection trigger 46 of the driver 22, the signal from the output of which (there is a signal 113 input) through the element 50 and the element 51 or 51 is reset. The prefetch firmware then transfers control to the implementation of the NVB command, which analyzes the result of the initial sample and, if successful, ends the execution of the NVB with a zero result sign. The peripheral device with which the channel establishes communication in the initial sample, which come from the subscriber's buses to the channel and are written to the buffer according to the address that enters the input of the buffer control unit from the output of the first counter 3 of the buffer address via comm tator 1 1 buffer address counters. The first counter 3 of the buffer address is modified by +1 on the modification signal 110 from the channel control block, the first counter of 4 bytes of the buffer is modified by +1 on the modification signal 111. As data arrives, the Hbix from the interface buffer fills, and when the first register of the address is bu- er after the next modification of 5 with 10 from 15

t 20

 ,

23809510

It calls the double word boundary, the data from the first double word of the buffer is transferred to the memory in a so-called split loop, and the data from the interface is written to the second double word of the buffer. In a divided cycle, the double data word from the channel buffer is transferred to the RAM, the data address in the channel data address register is modified, the byte counter in the second local memory location. A split cycle is one micro-instruction instrumented in the micro-instruction register upon request from a channel, inserted into any sequence of micro-instructions executed by the central processor.

In a split loop, the byte count of the buffer and the byte count state register are modified. The first counter of 4 bytes of the buffer is reduced by a constant numerically equal to the number of bytes sent from the channel to the RAM. The modification is performed by the modification node 5, to the first input of which the modification constant is fed over the bus 103 from the output of the channel management device. The second input of node 5 receives a split cycle signal 1.17, the third input receives the output of the first counter of 4 bytes of the buffer through the switch 13. byte counters of the buffer (figure 5) ,. recording the modified value into the first counter 4 bytes from the output of the node 5 modification of the execution according to the recording signal 112 in a divided loop.

A byte counter from the local memory in a split cycle for modification is read to the input of the ALU, modified and the modified one is written to the second local memory cell. At the same time, the entry into the first register 6 of the analysis of the byte counter from the bus 101 of the counter from the output of the channel control device, at a split signal 112 in a split loop, goes.

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When the last byte of the first USK is sent to the buffer, a comparison signal is generated from the output of the first comparison circuit 7, which passes through the switch 17 to the input of block 21, and from the output 30 of the device to the interface control unit, where it determines the end of the data transfer when entering if there is no chain flag in the channel

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Editor S..Lisina

Compiled by T. Areshev

 L.Ser Yukova. Proofreader L. Pilipenko

Order 3293/50 Circulation 67t

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5

Production and printing plant, Uzhgorod, st. Project, 4

FIG. 77

Subscription

Claims (1)

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