SU1553984A1 - Microprogram processor - Google Patents

Abstract

The invention relates to computing and can be used in the development of microprogram processors for digital computers. The purpose of the invention is to increase the completeness of the control. This is achieved by counting the control signals issued to input / output devices (ACC), storing the information transmitted to the ACC, and programmatically analyzing the reliability of the transmitted control signals and information. The microprocessor processor contains the operation unit 1, the microprogram memory unit 2, the microinstruction register 3, the first multiplexer 4, the second multiplexer 5, the third multiplexer 6, the synchronization unit 7, the counter 8, the decoder for 9 operations, the register 10 for communication with the memory blocks, the input communication register 11 with input-output devices, output communication register 12 with input-output devices, a group of trigger triggers 13 for storing requests, a group of trigger trigger 14 for storing interrupt requests, a priority block 15, a control signal issuing block 16, UVB OR group of elements 17. In addition, the processor introduced the second and third groups of elements OR 24.25, the second and first elements AND 26, 27, the first and second elements OR 28, 29, the fourth multiplexer 30 and the trigger control 31. 6 Il .

Description

one

(21) 4342851 / 24-24

(22) D.12.87

(46) ZOO.OZEOO. Bul № 12

(72) L.I. Drill, I.S. Muginstein

and E.E. Schwartz

(53) 681.3 (088.8)

(56) USSR author's certificate

No. 985791, - cl. G Ob F 15/20, 1980.

USSR author's certificate №, cl. G 06 F 15/00; 1981

(54) FIRMWARE PROCESSOR (57) The invention relates to computing and can be used in the development of microprogrammed processors of digital computers. The purpose of the invention is to increase the completeness of the control. This is achieved by counting control signals emitted to input / output devices (VHF), storing information transmitted in the VHF, and programmatically analyzing the reliability of the transmitted control

to

signals and information. The microprocessor processor contains the operation unit 1, the microprogram memory unit 2, the microinstruction register 3, the first multiplexer 4, the second multiplexer 5, the third multiplexer 6, the synchronization unit 7, the counter 8, the decoder for 9 operations, the register 10 for communication with the memory blocks, the input register AND connection with input-output devices, output register 12 connection with input-output devices, group of trigger triggers 13 for storing requirements, group of trigger trigger 14 for storing interruptions, priority block 15, block 16 for issuing control signals in V BB, the first group of elements OR 17. In addition, the processor introduced the second and third groups of elements OR 24, 25, the second and first elements And 26,27, the first and second elements OR 28,29, the fourth multiplexer 30 and the trigger control 31. 6 Il.

(L

Step

The invention relates to computing and can be used in the development of microprogrammed processors for digital computers.

The purpose of the invention is to increase the completeness of the control.

FIG. Figure 1 shows the structural scheme of the proposed firmware processor; in fig. 2 - the flow chart of the operating unit; in fig. 3 block diagram of the synchronization unit; in fig. 4 is a block diagram of a control output unit of an input / output device; 15 | FIG. 5 timing diagram of the synchronization unit; in fig. 6 - timing diagrams of the formation of control signals of an output command, control signals of an input command, control signals in the modes of suspension of calculations and interruptions.

The microprogram processor (Fig. 1) contains an operation unit 1, a unit of 2 pbm of microprograms, a register of 3 microcommands, a first k, a second 5 and a third 6 multiplexers, a synchronization unit 7, a counter 8, a decoder of 9 operations, a register 10 of communication with storage devices (memory), input 1 1 and 0 output 12 communication registers with input-output devices (HVAC), group 13 of triggers for storing I / O shutdown requests, group 1 of triggers for storing interrupt requests, priority block 15 , block 16 of the issuance of control signals in the air-blast and the first group 17 OR elements, 18-21 processor outputs, 22 processor input, 23 processor output, 24 second and 25 third groups of OR elements, second 26 and first 27 elements, first 28 and second 29 OR elements, fourth multiplexer 30 control trigger 31, inputs 32 , 33 and 3 processors. 45

Operational unit 1 (FIG. 2) contains an adder 35 (M + 2) -display multiplexers 36 and 37, an M-bit demultiplexer 38 and a group of M registers 39.

The synchronization unit 7 (FIG. 3) comprises a pulse generator 40, a counting flip-flop 41, a circular shift register k2, elements And 43 and 44.

The control signal issuing unit 16 in the ACU (Fig. 4) contains input triggering 55 45, output 46, 47 address request, 48 interrupt code requests, AND 49 52 elements

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The firmware processor (figure 1) works as follows.

The outputs of the register of 3 microcommands correspond to certain fields of the microcommand: transition addresses, operation and functions of the operation unit, selection of sources for address branching, control of the operation of memory blocks (processor output 18), control of multiplexer 6 operation, control of the decoder 9 operations.

The next microcommand from block 2 of the microprogram memory to register 3 microcommands is received synchronously with the signals from the output of block 7, which determine the period of the microcommands, and coincides in time with the falling edge of these signals.

On the register 10 of communication with the memory blocks (MU), the control signal from the output of the decoder 9 is used to receive the command selected at the address located at the output 19 of the processor. The beginning of the selection of a command from the memory blocks determines the signal of a request for a command issued at the end of the previous command from the register output of 3 microcommands. At the same time, the multiplexer 6 with the signal from the register output 3 micro-instructions is switched in such a way that its output passes the information received from the memory blocks to the information input 22 of the processor.

The next step in the execution of a command is the formation of the address of the operand, and the actions performed in the firmware depend on the type of addressing (direct, relative, indirect), which is determined by the command addressing attribute field. The addressing bits are received from the output of communications register 10 with memory blocks (memory) for the lower bits of multiplexer 4, and control information from the output of microcommand register 3, which allows information to flow to the output of the first multiplexer 4, arrives at its input. from the outputs of multiplexer 4 is fed to the inputs of a group of 17 OR elements, and to their other inputs information is fed from the output of register 3 micro-instructions, which is the field of the transition address K to the next micro-command. Moreover, the lower bits of the transition address, by the number equal to the bits of the addressing attribute, should be O, for example, 00101101000 (with the number of bits

51553984

attribute addressing equal to three). from

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The result of the logical addition at the outputs of the elements OR of the group 17 of the elements OR, depending on the value of the bits of the addressing feature, determines one of the eight cells of block 2. Thus, the branch to the group of cells of block 2 is organized depending on the type of the addressing feature.

The address of the operand is formed in the operation unit 1 and represents the selection of the address part of the command and its transfer to the processor output (direct addressing) or the addition of the selected address part of the command to one of the index registers (with relative addressing) and the result is also output processor.

The selection of the address part of the command is carried out by logical multiplication of the constant with the number of single bits equal to the address part of the command, by the command itself. For example, with a 16-bit command, when the address part is the lower 10 bits, logical multiplication is effected by the constant 0000001111111111, with the result that the upper six bits are zeroed out. At the same time, the information at the output of register 3 micro-instructions determines the type of function performed by adder 35 (Fig. 2) (arithmetic addition, logical addition, etc.) the address of register 39 of the operational block in which the result and addresses of operands are recorded (control multiplexers 36 and 37)) involved in the implementation of this function.

The address of the operand obtained on the adder 35, is fed to the output 19 of the processor "

To perform the actions determined by the operation code of the command, the output of the firmware of the current command is issued at the beginning, for which the bits of the operation code stored on the communications register 10 with the memory blocks (RAM) are transmitted through the higher bits of the first multiplexer k to others the inputs of the elements OR of group 1 of the elements OR0 In this case, the other inputs of the elements OR 17 receive the address of the transition with zeroes in the higher bits, equal in number to the operation code. When a six-bit operation code at the outputs of the elements OR 17, information is obtained that determines depending on

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the value of the operation code is one of the cells of block 2. Each of the 6k cells indicated is the initial execution in the microprogram of the execution of one of the 6 commands that make up the instruction set.

When exchanging the processor with I / O devices using I / O commands (synchronous exchange, the formation of the address of the operand and the exit to the beginning of the firmware), the process is carried out as described above. The generated address from the output of the operation unit 1 is received by the signal from the output of the decoder 9 to the output register 12 of communication with the air-blast and accompanied by a control input signal (for input command) or output (for output command) generated in control output unit 16 signals in the UVV enters the UVV.

The synchronization of the operation of the processor nodes is carried out by block 7 (Fig. 3) generating a strobe signal on the element, controlling the reception of the microcommand to the microcommand register 3 and the operation of the operation unit 1. The ring shift register 42 and the element L3 generate the signal

the chronometers synchronizing the operation of the unit 16 for issuing control signals to the UVV and the unit 15 of priority. The time (the operation of the synchronization unit is shown in Fig. 5.

When executing the information output command, selected from the memory block cell to the address received from the processor output 19 is received to the communication register 10 with memory blocks (memory) via the input of the multiplexer 6 communication with memory blocks and through the operation unit 1, which performs the transfer function, is received at the output register 12 of the communication with the air-blast by a signal from the output of the decoder 9 and transmitted to the air-blast. The timing diagram of the formation of the control signals of the output command is shown in FIG. 6

When executing a command to input information from the air-blast through the input of the multiplexer 30, from the processor input is received to the input register 11 of communication with the air-blast via the gate coming from the output of the decoder 9. Received to the input register 11 of the communication with the UVB information In this mode, the transfer function is received by the communications register 10 with the memory blocks through the input of the multiplexer 6 and further through the input of the multiplexer 5, controlled by a signal from the output of the decoder 9, enters the memory blocks for writing through the output 21. The timing diagram of the forms The control signals of the input command are shown in FIG.

a set of RS-flip-flops 45-48 and elements. Each RS-trigger records the presence and end of a certain exchange mode (exchange on input pause and input commands — trigger 45, exchange on output pause and output commands, trigger 46, presence of suspend mode. When exchanging the processor with the UVV on zap-jg trigger 47, interrupt - - to dews, arriving asynchronously from the UVWtrigger 48) by the signals coming in (suspend mode of the main program from the output of the decoder 9. Sync pulses or interrupt mode), the signals arriving at the inputs of the elements storing the RS-triggers I4 are generated. 9 52, determine the moment of issuing the 13 storing memorizing requirements of the pickup signals from the air-blast, I / O character or 14 interrupts for the exchange mode, which

The received request (or several is determined by the state of the triggers 45-48

Dews) enters the block 15 priority (inputs of elements I49-52). Temporary

the one that implements the sequence of processing diagrams (Fig. 6) are presented in

requests and issuing the exit code of the request received for processing, and a sign of the presence of the request. The priority block can be implemented on BIS 589IK14, 585IK14.

The priority block 15 carries out the internal request register under the control of the signal from the output of the ring shift register 42 from the output of block 7 and stored until the next reception. From the moment of receiving the request, the encrypted request code is found at the output of priority block 15. Under control of the signal from the output of the element I43, the priority unit 15 outputs a signal that determines the moment when the request is processed.

The microprogram for executing any command assumes the analysis of requests in the last microcommand, and if they are present, the firmware is branched by the request code from the output of the priority block with a transition to the beginning of the microprogram processing the corresponding request, while the next command is not executed, but The address is stored in one of the registers of the operation unit 1. After the processing of the input (output) request or group of requests is completed, the command that was read out the information from the memory cells is executed.

control if there is no request, or the control is transferred to the interrupt routine in case of an interrupt.

The formation of control signals for the air-blast in accordance with the timing diagram shown in FIG. 6 is carried out by the control signal-issuing unit 16 in the air-blast (FIG. 4). The pre-hardware control of the information transfer between the air-blast and the processor is performed by checking the evenness of the codes the control bit, 55 For the implementation of software control of communication equipment with external devices, the command system includes two control commands: Setting the control trigger and Reset

39848

a set of RS-flip-flops 45-48 and elements. Each RS-trigger records the presence and end of a certain exchange mode (exchange for input pause and input commands — trigger 45, exchange for output pause and output commands for trigger 46, the presence of the suspend mode of the 12-bit ring register 42 shift.

When exchanging with air-blast on demand input (output), the processor outputs to the air-blast signal from the control output

processor 23, initiating the issuance of the address of the cell to the processor, which through the input of multiplexer 30 is received to the input register 11 of communication with the air-blast (request signal of the address GSA) and through

the operation unit 1, which performs the transfer function, is received by the output communication register with the ACU. Further, the algorithm is similar to the algorithm for the execution of input (output) commands.

The exchange with the program interruption supposes the issuance of control signals to the UVV, by the number equal to the number of interrupt types initiating the issuance of the interrupt code (signals

interrogation code request (RFQ), which, through the input of multiplexer 30, is received at the communication input register 11 with the ACU and through the operation unit 1 that performs the transfer function, is received at the communication register 10 with memory blocks (RAM) to record it as

old words of the state of the program. A selection of new program state words is produced from memory cells analogous to

The hardware control of information transfer between the air-blast and the processor is carried out by checking the evenness of the codes by the control bit. To implement software control of communication equipment with external devices, two control commands are entered into the command system: Setting the control trigger and Reset

trigger trigger On the installation command, the signal from the output of the decoder 9 sets the trigger 31 of the control to 1, and also sets to

1 of all the triggers of the group of 13 triggers for storing the I / O pause requests and group 1 for the triggers for storing the interrupt requests. The signal from the output of the trigger 31 of the control enters the input of the element I26 and permits the passage of each control signal from the block 16 issuing the control signals to the UVV through the OR 28 element output to the UVV through the OR 29 element to the counting input of the counter 8. Installing the counter 8 in the initial state (carried out in each command through the input of the element E27), is prohibited by the signal from the inverse output of the control trigger 31, which enters the input of the element 27. Thus, the control signals emitted by the processor in the UVB are counted m passing program control. The output signal from the control trigger 31 switches the multiplexer 30 in such a way that the information output to the UVB from the output of the processor 20 enters its input (the input of the multiplexer 30) and is stored in one of the registers of the operation unit 1 for programmatically controlling

my uvv information. In addition, the information entry of the operating

40

From the output of the trigger 31, the control is fed to the input of multiplexer 4 in order to organize branching in the interrupt processing firmware. The branch is organized in order to prohibit the transfer of control to the interrupt processing routine and implement the transfer of control to a certain point in the monitoring program. During the execution of the monitoring program, the requirements stored on the triggers are sequentially processed in order of decreasing priority, until all the requirements have been processed, the information transmitted is compared with the reference, and the control signals issued to the UVB are compared. recording, the contents of counter 8 into the memory cell with subsequent comparison with the reference one with the sum. At the end of the program, the control is reset to the initial state by the command for resetting the trigger control. In this case, the countable

block, processor memory management output, first inputs of the OR elements of the first group, control input of the first multiplexer, control input of the second multiplexer, input of the operation decoder, first, second, third, fourth, fifth, sixth and seventh output connected, respectively, with 45 installation inputs to the Triggers for remembering the request to pause the group's I / O, the installation inputs for the Triggers for storing the group interrupt requirements, the input input register with devices I / O, synchronous output of the output register of communication with input-output devices, informational input of the control signal output unit to input-output devices that control the input of the third multiplexer, synchronous input register of communication with storage devices, whose output is connected to the information to the input of the counter, to watts

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the input of the counter 8 signals come only from the output of the decoder 9 through the input of the element OR 28, and the installation is performed by a signal from the output of the decoder 9 through the input of the element And 27.

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invention formula

A microprogram processor containing an operational block, microprogram memory block, microinstructions register, first, second and third multiplexers, synchronization block, counter, e-encoder of operations, communication register with memory devices, input and output registers with input devices output, group of trigger triggers for storing I / O requests, group of triggers for storing interrupt requests, priority block, control signal output unit to input / output devices and the first group of OR elements, output which are connected with the address inputs of the memory unit microprograms, outputs of which are connected to the data inputs of the microinstruction register fields outputs operation control memory devices, address transition, selecting branching source address, the control multiplexer, whose control decoder operations are respectively connected to the first

information entry operating

block, processor memory management output, first inputs of OR elements of the first group, control input of the first multiplexer, control input of the second multiplexer, input of the operation decoder, first, second, third, fourth, fifth, sixth and seventh outputs of which are connected respectively with the installation inputs in the About triggers of storing the request for suspending group I / O, the inputs of the installation in About the triggers of storing the interrupt group requirements, the synchronous input of the input communications register from the devices I / O, synchronous input output register of communication with input / output devices, information input of the control signal output unit to input / output devices, control input of the third multiplexer, synchronous inputs of communication register with memory devices, the output of which is connected to the information input counter to wto

ten

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To the information input of the operating unit, to the first information inputs of the first and third multiplexers, the output of the operating unit is connected to the output of addressing the memory of the processor, the first information input of the second multiplexer, the information input of the output communication register with input-output devices, the output of which is connected to the information output in the input-output devices of the processor, the output of the counter is connected to the second information inputs of the first and third multiplexers, the outputs of which are connected ootvetstvenno with the second inputs of OR elements of the first group and the output of information in memory devices

the processor, the outputs of the zalomi triggers, the requirements for suspending the group I / O, and the outputs of the trigger triggers for storing the interrupt requirements are connected to the first and second inputs of the priority block, the output of which is connected to the third information input of the first multiplexer, and the third input is connected synchronization, the second output of which is connected to the input 30 of the resolution of the control signal output unit to the input-output devices, and the third output is connected to the synchronous input of the register of micro-commands and with the synchronization of the operating unit, the third information input of which is connected to

the output of the input register of communication with input-output devices, the second information input of the second multiplexer is connected to the first information input of the processor, the output of the second multiplexer is connected to the information input of the communication register with memory devices output of the output of control signals to input-output devices connected to the control output, processor input / output devices, characterized in that. in order to increase the completeness of the 45

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It contains the second and third groups of OR elements, the backup and second elements AND, the first and second elements OR, the fourth multiplexer and the control trigger, the eighth, ninth, tenth outputs of the operation decoder are connected to the first input of the first element AND, first the input of the first element OR, the installation input into the control trigger, the eleventh output of the operation decoder is connected to the installation input of 1, the control trigger and the first inputs of the elements of the second and third groups whose outputs are connected but to the inputs of the installation into 1 triggers of storing the group I / O request requirements and the inputs of the installation into 1 triggers of storing the group interrupt requests, and the second inputs are connected respectively to the input of the pause request and the processor interrupt request input, the second information input of the processor the multiplexer, the output of which is connected to the information input of the input register of communication with input-output devices, the second information input of the fourth multiplex The litter is connected to the output of the output register of communication with input-output devices, the control input of the fourth /, multiplexer, the fourth information input of the first multiplexer, the first input of the second element And are connected to the forward output of the control trigger, the inverse output of which is connected to the second input of the first AND element, the output connected to the information input of the counter, the counting input of which is connected to the output of the first OR element, the second input connected to the output of the second AND element, the output of the control signal fishing in I / O devices is connected to the inputs of the second OR element, the output of which is connected to the second input of the second AND element,

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Claims (1)

Claim A microprogram processor containing an operating unit, a microprogram memory unit, a micro-register, first, second and third multiplexers, a synchronization unit, a counter, an operation encoder, a communication register with memory devices, input and output communication registers with input-output devices, a group of triggers for storing requirements I / O suspension, a group of triggers for storing interrupt requirements, a priority block, a block for issuing control signals to I / O devices, and a first group of OR elements, the outputs of which x are connected to the address inputs of the microprogram memory block, the outputs of which are connected to the information inputs of the microcommand register, the outputs of the operation fields, memory management, transition addresses, selection of address branching sources, multiplexer operation control, operation decoder controls of which are connected respectively to the first information input of the operation unit , the control output of the processor’s storage devices, the first ¹ inputs of the OB'OR element of the first group, the control input of the first the multiplexer, the control input of the second multiplexer, the input of the operation decoder, the first, second, third, fourth, fifth, sixth and seventh outputs of which are connected respectively to the inputs of the installation of 0 triggers to remember the requirements of the suspension of input-output. group, setting inputs to 0 triggers for memorizing group interrupt requirements, sync input of the input communication register with input / output devices, sync input of the output communication register with input / output devices., information input of the control signals output unit to input / output devices, control input of the third multiplexer, register sync inputs communication with storage devices, the output of which is connected to the information input of the counter, to the second information input of the operating unit, to the first information the inputs of the first and third multiplexers, the output of the operating unit is connected to the output of the addressing of the processor's memory devices, the first information input of the second multiplexer, the information input of the output register of communication with input / output devices jq, the output of which is connected to the information output to the processor input-output devices, the counter output connected to the second information inputs of the first and third multiplex 75 (typlexers, the outputs of which are connected respectively to the second inputs of the OR elements of the first group and the output the information house to the processor’s storage devices, the outputs of the triggers for remembering the requirements of the suspension of group I / O and the outputs of the triggers for remembering the requirements for interrupting the group are connected respectively to the first and (second inputs of the priority block, the output of which 25 is connected to the third information input of the first multiplexer, and the third input is connected to the first output of the synchronization unit, the second output of which is connected to the input 30 of the resolution of the block issuing control signals to input-output devices, and the third output is Inonii microinstruction register with clock terminal and a clock terminal of the operation unit, the third infor mation ss-input of which is connected to the output of the input register an input-output devices, a second data input of the second multiplexer connected to the first information processor ⁴⁰ vho- house, the second multiplexer output connected to the information input of the communication register with the storage devices, the output of the control signal issuing unit to the input-output devices is connected to the control output, the process input-output devices ra, characterized in that, in order to increase the completeness of control, it contains the second and third groups of OR elements, the first and second elements of AND, the first and second elements of OR, the fourth multiplexer and trigger control, and the eighth, ninth, tenth outputs of the operation decoder connected respectively to the first input of the first AND element, the first input of the first OR element, the input of the control trigger setting O, the eleventh output of the operation decoder is connected to the installation input 1, the control trigger, and the first inputs of the OR elements of the second the third group, the outputs of which are connected respectively to the installation inputs of 1 triggers for storing the group I / O suspension requirements and the installation inputs for 1 triggers for storing the group interruption requirements, and the second inputs are connected respectively to the suspension request input and the processor interrupt request input, the second information processor input connected to the first information input of the fourth multiplexer, the output of which is connected to the information input of the input communication register with input-output devices, information Torah fourth multiplexer input connected to the output register output due to input-output devices, a control input of the fourth /. '' multiplexer, fourth information input of the first multiplexer, first input of the second AND element connected to the direct output of the control trigger, the inverse output of which is connected to the second input of the first AND element, the output of the counter connected to the input of information reception, the counting input of which is connected to the output of the first OR element the second input connected to the output of the second AND element, the output of the output of control signals to the input-output devices is connected to the inputs of the second OR element, the output of which is connected to the second input second element AND " FIG. 4 1 553984 Generator ^ J-l, nJ'TrU1 „rLJn.J'-LrULrmT'LrTrLJ ~ L. Evil .and h! F Mj -) cut V—— -------— ~ -—— Jeu? L ————- g —____—---- J7 / 7p- / I —-------——... -icUP I -----------_____- -—----- ifz / P + f K-ii FIG. 5 Sign Take to Airborne Command you8edv Address 6 UVV Information g UVV Feature SMa 8 At Bl Address 8 Ш Information from 9'86 Input Team _to Output Priostons . .G ----- 1 ......... T “~ i GT > ...... G ~ L. ..... Fig s RraostoivoV Input I • Interruption