SU1527641A1 - Device for formation of route of message - Google Patents

Abstract

The invention relates to computing and can be used in digital communication networks, including computer networks, to calculate the optimal message transmission paths. The aim of the invention is to improve the accuracy of the formation of the route. In order to ensure the operation of the device, a minimum expenditure of bandwidth of the communication channels and an insignificant performance expense of the computing device are required to receive service information about the current state of the network load. Essential features of the invention in comparison with the known devices are the presence of a shift register, a group of elements AND, OR, delay elements, an encoder, a control trigger, new functional connections that together with known blocks and functional connections ensure the achievement of a positive effect. Characteristic features of the proposed device are its high efficiency in the consumption of network resources and the accounting of complete information on the loading of all network nodes. 1 il.

Description

The invention relates to computing and is intended for use in devices for switching messages and packets in computer networks.

The aim of the invention is to improve the accuracy of the formation of the route.

The drawing shows the block diagram of the device.

The device contains an input register 1, a buffer register 2, a block of 3 groups of elements AND, a decoder 4, a comparison circuit 5, a group of 6 elements AND, a state register 7, groups of 8 and 9 elements AND, a group of 10 elements OR, a block of 11 groups of elements AND , element OR 12, element AND 13, shift register 14, delay elements 15-17, element OR 18, trigger 19, element AND 20, pulse generator 21, memory block 22, device message output 23, device node status inputs 24 , informational input 25 of the device, output 26 of the end, input 27 of the installation, input 28 of the start, input 29 of the output of devices but.

The number of buffer registers of block 2 and groups of elements And block 3 corresponds to the number of neighboring switching nodes for a given node. The number of bits in the register of 7 nodes is n-1, where n is the total number of switching nodes in the data network.

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3 The number of groups of elements And block 11 is M, and the number of bits of the shift register 14 is, where M is the number of fixed routes for each destination node address. The device works as follows.

A message on input 25 is fed to register 1. At the same time, a control pulse is applied to the input, which translates trigger 19 into a single state. The address of the destination node of the received message arrives at the address input of memory block 22. The number of rows is (n-l) xM, and the number of columns is n-1. For each destination node, there are M fixed routes (M lines), the first of which is optimal, and the rest is suboptimal. When generating route codes, units are written into the appropriate columns for each route if messages are transmitted through these switching nodes. Known algorithms are used to calculate fixed routes.

At the destination node address, from the memory block 22, the corresponding M lines with route codes are selected and 11 groups of elements I are fed to the block.

The clock pulse through the element AND 20, entering the input of the register 14, moves the unit from the zero bit to the first bit, and the code of the first route through the first i-pynny elements AND block P, group 10 elements OR is applied to group 6 elements AND

At the same time, from the state register 7, a binary code (a network status word) characterizing the state of the buffer accumulators of the network nodes is fed into a group of 6 elements. Each bit of the network status word corresponds to a network switching node. If the number of messages in the buffer node of the switching node is less than the set threshold, then the unit in this bit is one, otherwise zero. The network status word is generated and periodically updated with the help of positki to the network of special corrective messages. In register 7, the network status word enters informational inputs 24.

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From the outputs of the AND elements of group 6, the Loose code is fed to the comparison circuit 5, where it is checked for a match with the route code that enters through the group of 9 elements AND by the first clock pulse delayed by the delay element 17 for the execution time of the logical operations.

If for the given route all switching nodes are available (units in the corresponding bits of register 7), then the output of the comparison circuit 5 is

15 pulse, by which the route code through the group of 8 elements And goes to the decoder 4. At one of its outputs, a signal is generated, according to which the message from register I is rewritten into

20 corresponding rows of buffer register 2 for further transfer to the neighboring node. The pulse from the output of the comparison circuit 5 through the element OR 12 and the delay element 15 enters

5 to output 26, informing you that the route selection has been completed, and through the OR element 18 sets register 1, shift register 14 and trigger 19 to the initial state.

30 If the codes do not match, a pulse is not generated at the output of the comparison circuit 5, the next clock pulse from the clock generator moves the unit in the shift register to the next bit and the next route code goes to group 6 elements I.

Again, the next route is checked in the same way.

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The process continues until

An optimal route is selected for this network condition. After checking the last route, the clock pulse through delay elements 17 and 16, AND element 13, OR element 2, delay element 15, and OR element 18 sets the device to its initial state.

Claims (1)

Invention Formula A device for generating a message route containing an input register, a memory block, first and second blocks of groups of elements I, a status register, a comparison circuit, a pulse generator and a buffer register, the device message input being connected to the information input of the input register, the output of which is connected to address input of the memory block. the outputs of the bits of the K-th group of which (, 2, ..., M, where M is the number of fixed routes for each address of the destination node) are connected to the first inputs of the corresponding elements of the K-th group of the first block, the outputs of the bits of the input register are connected with the first inputs of the corresponding elements AND of each group of the second block, the outputs of which are connected to the information inputs of the corresponding bits of the same name group of the buffer register, the output and synchronization input of which are connected respectively to the message output and the clock input and a device whose state input is connected to an information input of a state register, characterized in that, in order to increase the accuracy of the route formation, three groups of AND elements are entered into it, a group of OR elements, a decoder, a shift register, a trigger, two AND elements , two OR elements and three delay elements, with the outputs of the shift register bits connected to the second inputs of the AND elements of the corresponding groups of the first block, the outputs of which are connected to the corresponding inputs of the same elements of the OR group, the outputs which are connected to the first inputs of the corresponding elements And from the first to third groups, the outputs of the bits of the register of the state are connected to the second inputs of the corresponding elements AND of the first group, the outputs of which are connected to the first inputs of the corresponding 5276416 the secondary bits of the comparison circuit, the second inputs of the bits of which are connected to the outputs of the corresponding elements of the second group, the output of the comparison circuit is connected to the second inputs of the elements of the third group, the outputs of which are connected to the input of the decoder, the outputs of the bits of which are connected the corresponding groups of the second block, the output of the pulse generator is connected to the first input of the first element I, the second input of which is connected to the output of the trigger, the installation input of which is connected to the start input of the devices the reset input of which is connected to the first input of the first OR element, the output of which is connected to the installation input on the trigger, the input setting of the input register and the installation of the shift register, the shift input of which is connected to the output of the first element AND and the input of the first delay element whose output is connected with the second inputs of the elements of the second group and through the second delay element with the first input of the second element And, the second input and output of which are connected respectively to the output of the higher bit of the shift register and the first The second input of the second OR element, the second input of which is connected to the output of the comparison circuit, the output of the second OR element is connected via the third delay element to the second input of the first OR element and the device termination output. 15 0 25 thirty 35 W WELL "J I'm 21