SU1381668A1 - Digital device for controlling mains-guided converter - Google Patents

Abstract

This invention relates to electrical engineering and can be used in static converters. The purpose of the invention is to improve the dynamic performance and increase reliability. By introducing a zero value into the device for controlling the latch converter, the phase shift code registers 21i-21, the phase shift code 17 multiplexer, the base address register 18, the adder 19, and the phase shift code 22 delay blocks of the device in a dynamic modes, when the phase delay of the pulses changes significantly during a single cycle of the mains frequency. 2 Il. S (L 00 00 O5 a oo /

Description

The invention relates to electrical engineering, in particular, to control systems of thyristor 11) eo6-time. 1M, and can be used as a control unit for converters driven by a network.

The purpose of the invention; the development of dynamic characteristics and the improvement of the reliability of the workplace.

On fi1. I presents a block diagram of the device; on i) Hi 2 - zero h (H to heratinny remember) of the block,

The device contains in numbers; | at the phases of the power supply, ibTpiii 1,1 liri, the inputs of which are designed for 1K) and the phases of the mains voltage, and the outputs are connected in phase to the inputs of the ball-bodies 2.1 ... 2ni, the outputs of the sci: Yuchenny and informational inputs of muliplexo | 1a 3, the output of which is connected to the multivibrator 4 and the first input of the element OR 5, waiting for o and 1) and 4 is connected to the input of the counter of the transformer 6 phase number 6, the output of KOTcjpoi o the node is addressable; pnp multip: 1exor i, shift register) Liin ({) radio 7, the input Koropoio is connected to the output jack l-body br-polar phase 2 and the output to the yoke rum I.CH input AND gate 5, to groom. who is connected to the information input of the operative () of the storage unit 8, the paiop gene of the tactics of the ilia ov 9, the output of Koiopocc; ) dk11chem to gkho, iibi6 iK; i () iie | i; iTHRHori) “aiJOMHHaioiiit ll) of block 8 and. skchchik entrance; HoMeiia ty) 1and r. Jinoro 1 reproach1 AGC: and I), NUMBER I irg i o poi; -; ly forms jjui ;; I and I days off and I 11, containing r.d / K- i; i MriiBbie registers, 1пИИ | {) ratsig 12, -ls to- | Г1Ы I. : counter of the number | q1) of the source 14 n iji (;) i: i | i j4a rt, ii double imi ly. ibcoB 1G); L11d sdi1; gov | o reg reg grad .-- pyrification i 2 oh 1 1-din1. 11 with the second mi lemepga I 13 and the counting input of the counter H1: ms) a i iris mountain 14 and about |) and it is the input of the node 1 mn | 1g; ani i1) 1new impulses II, n: x ;; l, ciiuiioHoio |) his registrar 4 - rapine 12 h1kdiiep with the first input of the element And 13. libixc.i, a cat, | the 1st is connected to the reset input of the counter nnvupa tiri (.to) and 14. the output of which is soy is 1nnow with the input of the formation | S.: | i ,,. i; os4iiibix pulses 15. Device-C 1 in 1OPO.iiin telpo 1 is equipped with a latch T1erv (.11 (; .I1chapi 16, multHiiJieKC (jpoM phazovsi o (.DAY a 17. address address 18, sum 1ator; 19, lemul1 / type peksog om 20, according to the number of nipnc t (1) l; registers of phase codes of shift 1 and 21 p 1) .1ade) jkn za1: nsi code 22, nrcssiu iu, s 1: m tshka tiristorny number (.) P () p; 1 i4ii; i 11,1 1,1) unit with a fixed input |) and with its own., p, acheni Ui and a-repami njnii.aViii demu. i.thilexor 20 and multiplexer fa.K WHAT c; iBHia 17. infoch1) 1e in (.). :) To | ui; o connected15 | iyhopere pst;) with the code ij) a30Boi () shift. a 2, which inputs) pre.dia 111chapy d: 1, podkl - than ,. And (; then || pkku ijia iOBoro codes with; 1VI1-a, i1

five

0

five

0

,

0

five

0

five

latch stroke ny. The iBoio value is connected to the lock input of the multiplexer phase codes, to the write input of the address register 18, to the write enable resolution of the operational storage unit 8 and the transfer input of the adder 19, the input of which is connected to the output of the multiplexer phase shift codes 17, and the input to the address 1 and the operational memory - nieix.i of the VIS unit with the input bus of the register |) and address 18, the output of the operational reserve. The terminal of its unit 8 is connected to the information input of the demultiplexer 20 n outputs of which but the number of thyristor converters correspondence with the inputs of the nodes: 1ov forming the output pulses 11, and the input of each node forming the output pulses 1 1 combined with the corresponding block delay write code Phase Shift 22 and the outputs of which are respectively connected to the control inputs of the code phase

WITH; 1VI; a - 21

Usg) the realm of the slave thaws in the next way.

The voltages of the fa.z network are fed to the 1.1 l.ni input filters, and then to the null-1 2 2 2.t, which fix the positive momentum at their outputs of the moment of the passage through zero (for example) 1) corresponding to the (w) common phase. These impulses come in and (i) P) food, in the village, | e; | .oia-1, on info 0 (1 laiponnye ni and / nplexer 3, and on yn) pl.11) 1ci: e it comes from the output of the CMevHK.y number (} i; i zi ti code, ensure that the klux klyu klyu nis one of the pnformacionchk logged in with. mue; 1yti11,: | ec grade 3 to zh. stinging multivibratch ru 4 with Hpev.eHk M ass (. rzhkn T). The impulse from the output, -kD ineio mules n, iH j | ia О |) and 4 fails to talk through nr (m Td counts: 1k 6, with this m multi-hyp. 3 crossing, 1K) reads on waiting im- |; w. || ka; () next () on the order of well, t-or-laii.i, after which the process is repeated.

D.1KIM way, at one of the inputs of the element OR 5 f (form one) u) channel, the succession of synchronizing names. TbC (jB. Immediately from the output of the first zero- 2 is delayed by the shift register) () M 7 one stroke and the second element comes in. The input is OR 5, this is at its output and one-channel.) 1n the sequence of pulses, the first of the group is doubled, which is necessary in each of the phases to belong to each ) 1st impulse.

The operating cycle of the device consists of p + 1 clock cycles of the clock clock pulse 9, which determines the output state of the thyristor number counter of the converter 10, here is the number of controlled thyristors (Jthe expander.) Zero state () iksi) With the bullet value i (j (L1e)), the active memory unit 8 is switched to the recording mode and simultaneously

by blocking multiplexer 17 no, the input C is set to the zero state of the bus) S In adder 19, as a result of which the code from the output of the register of address 18 is increased by 1, because the transfer input P of the adder 19 receives a positive impulse. In the same case, if the synchronization signal appears in the information input D of the operational storage unit 8, it will be written as "1 in the cell with the address AJ (Fig. 2a), in the opposite case it is written to 0. At the end of the zero clock cycle, address 18 by dropping the zero state signal, a new value of the base address is fixed (Fig. 2a).

During the following cycles, the phase shift codes of the control pulses of the corresponding thyristor converters are alternately connected via multiplexer 17 to the bar B of adder 19, and the cell address from which the information is read is outputted from the adder

Ak (AS-TK) mod 2, (l)

where TK is the phase shift (delay) code;

S. is the size of the HZB and adder;

K is the number of the thyristor converter served in this clock (K 1, 2, ... G1).

The transfer output of the adder is ignored, i.e. the addition operation is performed modulo 2 (since the output UIH- on multiplexer 17 contains inverse signals, in fact, the operation of subtracting the phase shift code from the base address code is performed).

Thus, during the next cycles of the cycle, the operational storage unit 8 switches to the read mode, and the inverted phase shift codes alternately arrive at in) Inu B of the adder 1-9, and the relative address AC is generated at its output. The base address, moving in the field of OZB 8 cells, activates one of them at the moment of arrival of the delayed pulse, and the read information from the carrier will be at the time for which the pulse in this channel is delayed (Fig. 2a).

The pulses from the output of the operational storage unit 8 are fed to the information input of the demultiplexer 20 corresponding to the channel number defined in this cycle, since the common input of the demultiplexer is fed the same code as the address input of the multiplexer 17.

In order to avoid disrupting the operation of the device due to the finite number of cells in the on-line storage unit 8, it is necessary to select the appropriate counter size 10 and OZB 8 so that the update of information in this cell can occur only after reading the previous information, i.e. to fulfill the condition

2

max {T ..

(2)

In this case, the situation resulting from the modulo 2 summation (i.e., without transferring from the senior bit of the adder) will not lead to a failure, since the cell with the base addressometer AR is interrogated again after a specified time, since after cell 2 -1 is selected cell O (FIG. 26).

The size of the SSS 8 and the adder 19 depends on the duration of the phase shift t, the accuracy of its installation eo and is determined by

15

1 ent (log2 | -) -f 1. t

(3)

The frequency of the clock generator is determined from condition 0

0

eo

(four)

0

where v logari.

Accordingly, the counter width of 10 - 1 + V.

The arrival of a new delayed pulse before the previous one is read is clearly not disrupting the operation of the device, since it is simply written to the appropriate cell and will be read with the same delay as the previous one.

The installation of the counter 14 is carried out by giving to its input a potential drop at the time of the arrival of the dual pulse, which is protected by the control pulse of the thyristor in the first phase of the converter. Each pulse arriving at the input of counter 11 is delayed per clock shift, within 1 decoding register 12, and received

5 I and the input element And 13i, therefore, on arrival (a dual pulse at the output of the element And 13 |, a positive potential is formed, which is fed to the reset input of the counter 4 |, thus deciphering it.

After doubling the pulses formed at the output of the counter 14 |, in the former 1o | they are supplied to the control inputs of the first thyristor converter. Block delay writing code phase

5, the shift 22i, to the input of which control pulses are also fed from the corresponding output of the demultiplexer 20, generates a pulse initiating writing to the corresponding register 211 delayed by a time interval, which is determined by the dynamics of the thyristor converters. This avoids the re-reading of information if at the input of the register 21i the phase shift code is increased immediately after the occurrence of the control pulse, which can lead to incorrect distribution of the control pulses across the channels.

In the following clock cycles, a similar sequence of operations is repeated with respect to the control pulses; 1 of the remaining thyristor converters.

Thus, the application of this device in comparison with the known new elements, namely, the zero value latch, the phase shift code registers 211-21p, the phase shift code multiplexer 17, the base address register 18, the adder 19 and the delay blocks of the phase code write 22 22 „, allows to increase the reliability of the digital device in dynamic modes, when the phase delay of the pulses varies significantly during one period of the network frequency.

Claims (1)

Invention Formula A digital device for controlling the slave network converter, which contains, by the number of phases of the picking network, filters whose inputs are intended to be connected to the phases of the network voltage, the outputs are phase-wise connected to the inputs of the zero-organs, the outputs connected to the multiplexer information inputs the waiting multivibrator and the first input of the OR element are connected, the output of the multivibrator waiting is connected to the input of the counter of the phase number of the converter, the output of which is connected to the address pin of the multi.chexor, shift p the hysterestation, the input of which is connected to the output of the zero-phase organ of the first phase, the output — to the second input of the OR element, the output of which is connected to the information input of the activity step 1 of the 1st storage unit, generator 1, p clock pulses samples of the operative storage unit and to the input of the counter of the thyristor converter number by the number of thyristor converters, the output pulse generation nodes, each of which contains a shift register register, e. tement I, thyristor number counter and dual pulse driver, input the decryption shift register is combined with the second input of the AND element and the counting input of the thyristor number counter and forms the input of the output pulse shaping unit; the output of the decryption shift register is connected to the first input of the AND element, the output of which is connected to the reset input of the thyristor number counter, the output of which is connected to the input a dual pulse generator, characterized in that, in order to improve the reliability of operation, it is provided with a zero-point lock, a multiplexer of phase shift codes, an address register, su by the matrix, demultiplexer, by the number of thyristor converters by the phase shift code registers and code recording delay blocks, the output of the thyristor converter number counter is connected to the latch input of zero value and the address buses of the phase multiplier and multiplexer, the data inputs of which are connected to the outputs of the phase code registers the shift, the inputs of which are intended to be connected to the input of the phase shift codes, the output of the latch of the first value is connected to the input of the lock and the multiplexer of phase shift codes, with the input of the register of the address register, with the input of the write resolution of the operational storage unit and with the transfer input of the adder, whose addition input is connected to the output of the multiplexer of the phase shift codes, and the output with the address bus of the operational storage unit and with the input width address register, the output of the operational storage unit is connected to the information input of the demultiplexer, n outputs of which, by the number of thyristor converters, are connected respectively to the inputs of the forms Hovhan input pulses and generating output pulses each input node is combined with the input of the respective recording code phase shift delay unit whose outputs are connected respectively to the control inputs of the phase shift code registers.