SU1180905A1 - Information exchange device - Google Patents

Abstract

1. DEVICE FOR EXCHANGE OF INFORMATION, containing a group of communication blocks with a subscriber, switching units of commands and information, a block for decrypting an address and commands, an interrupt block and a priority block, the inputs of the request signals of communication blocks with the subscriber of the group and interrupt unit, address inputs - with address inputs of priority block and interrupt unit and with address output of address and command decoder, the first output of which command code is connected to command inputs of communication units with subscriber groups, informational inputs and outputs of which are connected respectively to the first information outputs and input of the information switching unit, the control input of which is connected to the second output of the command code of the address decryption block and commands and the control inputs of the priority block and interrupt unit, the second information input of the information switching unit connected to the information output of communication with the processor of the device, and the third information input - with the information input of communication with the processor of the device, the input of the decryption unit addresses and commands and command inputs of the priority block and interrupt block, the output of the command switching unit is the output of the device request address, the first and second information inputs of the command switching unit are connected respectively to the output of the priority block and the first output of the interrupt unit, the second output of which is connected to the control the input of the command switching unit and the interrupt output of the device processor, characterized in that with ®, which, in order to show the performance of the device, a block has been entered into it (L information capacity, the information input of the information digitization block is connected to the information outputs of the communication blocks with the subscriber of the group and the third information output of the information switching block, the output 00 of the digitization block of the other circuit formation is connected to the information output of the communications with the processor of the device and the third information output of the information switching unit, and the input of the command code input and the control input of the modes of the information conversion unit of the information are connected but with the third and fourth outputs of the command code of the block for decoding the address and commands. 2. A device according to claim 1, characterized in that the information conversion unit comprises an input word switching node whose information input is the information input of the block,

Description

accumulation gist, output word switching node, the first output of which is the information output of the block, and the information input is connected to the information input of the zero state control node of the accumulation register and through the accumulation register to the output of the input word switching node, the information reception control node, the first control The output of which is connected to the control input of the switching node of the input words, and the control node of the higher information, the output group of which is connected to the input of the mode control of the control node zero of the accumulation register and the control input of the switching node of the output words, the output connected to the synchronization input of the control node receiving information, and the inputs

start and stop - respectively to the start and stop inputs of the control unit of the information and the second

and the third control outputs of the information reception control node, the start input of which is connected to the output of the information control node, the mode control inputs and the code entries of the command of the reception control and reception information nodes are respectively the mode control input and the block command code input, and the information inputs and exits form

respectively, the information input and output unit,

3. The device according to PP. 1 and 2, characterized in that the information reception control node comprises a register, a counter, three groups of AND elements, a decoder, the outputs of which form the first controlling output of the node, two triggers, a pulse generator, the HE element, seven AND elements and three OR elements, the output of the first element OR is connected to the first inputs of elements AND of the first group, the outputs of which are connected to the information input of the counter, the information input of the register is connected to the outputs of elements AND of the second group, the first inputs of which form the input of the command code of the node a, the second inputs of the second group elements and the first input of the first element OR are connected to the node mode control input, the first inputs of the third group elements are connected to the register and counter outputs, the outputs to the decoder inputs, and the second inputs to the output of the first element And, the outputs of the second and third elements And are connected respectively to the subtractive input of the counter and the start input of the pulse generator, the output of which is connected to the counting input of the first trigger and the first input of the first, second, fourth and fifth elements And, the outputs the sixth and seventh elements AND are connected respectively to the first input of the second trigger and to the second input of the first OR element, the counter outputs are connected to the inputs of the second OR element, the output of which is connected to the first input of the third AND element and through the NOT element to the second input of the fifth AND element , the inverse output of the trigger is connected to the second input of the second element I, and the direct output to the second inputs of the first and fourth elements I, the output of the fourth element I connected to the reset inputs of the register and the counter, and the third input to the output the second trigger and the first input of the sixth element AND, the second input of the third element OR connected to the output, the first input of which is the node synchronization input, and the second input connected to the output of the seventh AND element, the first and second inputs of which form the node start input, the second inputs of the elements And the first group is connected to the outputs of the register, the second inputs of the second trigger and the third element And form the information input of the node, the outputs of the fifth, sixth and first element, s, And are respectively the second and third control and information inputs of the node.

4. The device according to PP. 1 and 2, characterized in that the control information node contains a decoder, the outputs of which are an image of a JTOT group of outputs of a node, three groups of AND elements, a register, a counter, an NOT element, a delay element, three AND elements, a pulse generator, two OR elements and trigger, the counter inputs are connected to the outputs of elements And a pen group, the first inputs of which are connected to the outputs of the register, inputs connected to the outputs of elements AND of the second group, the first inputs of which form the input of the node command, and the second inputs are connected to the control input the node, the outputs of the register and the counter are connected to the first inputs of elements AND of the third group, the outputs of which are connected to the inputs of the decoder, and the second inputs to the output of the first AND element and the information output of the node, the outputs of the counter are connected to the inputs of the first element OR, the output of the pulse generator is connected with a counting trigger input and the first inputs of the first and second elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the trigger, the output of the first element OR is connected to the input of the element NOT and the first The third input is an AND input, the output of the pulse generator is connected to the start input, and the second input is with the output of the second OR element, the first input of which is the information input of the node, and the second input through the delay element connected to the second inputs of the AND elements of the first group and the start input of the node , the register and counter reset inputs are connected to the node's stop input.

one

The invention relates to computing and can be used in systems of exchange between computers and subscribers of different types.

The purpose of the invention is to improve the performance of the device for the exchange of information by implementing the function of ensuring the conversion of information word formats during the exchange between subscribers of different types by size.

Fig. 1 is a block diagram of a device for information exchange; in fig. 2 - block diagram of the block for decoding the address and commands; Fig, 3 is a functional diagram of the information switching unit; FIG. 4 is a block diagram of an information conversion block; Figs 5-9 are functional diagrams of an input switching node; words, output word switching node, accumulation register zero state monitoring node, information receiving control node and information output control node.

The device comprises a communication unit 1 with a subscriber that implements the subscriber interface,. performs logical, electrical and cable interfacing with subscribers, priority block 2, which realizes priority service of the applications received from blocks 1, block 3 interruption, designed to generate processor interrupt signals for satisfying subscribers of limited time

start of service, information conversion unit 4, information switching unit 5, address and command decryption unit 6, command switching unit 7, used to transmit 8 code codes for the incoming command from blocks 2 and 3, bus 9 for service rates, bus 10 address bus, bus 11 command bus, bus 12 and 13 input and output information lines, bus 14-22 links between blocks.

The block 6 for decoding the address and commands contains a command allocating node 23, an address generating node 24, a node 25

. vschachi commands, decoder 26,

The information switching unit 5 contains the first and second groups 27 and 28 of the elements AND, the register 29 and the third, fourth and fifth groups of 30-32 elements AND,

The information length conversion unit 4 comprises an input word switching node 33, an information reception control node 34, an accumulation register 35, an accumulation register zero state control node 36, output word switching node 37, an information control node 38, communications bus 39-51 between the nodes of block 4, the node 33 of the switching of the input words contains groups of 52-55 elements, and the node of 37 switching of the output words of the group of 56-59 elements, (Figures 5 and 6 in brackets show the numbers of bits of information words switched by nodes 33 and 37 ). The zero state control node 36 of the accumulation register contains the first group 60 elements OR, element OR 61, counters 62-64, the second group 65 elements OR, decoders 66-68, the first group 69 elements AND, the element OR-NOT 70, the third group 71 elements OR, the second group 72 elements AND, element OR-NOT 73, the fourth group 74 elements OR, the third group 75 elements AND, element OR-N 76, element AND 77, elements OR 78 and 79 and element 80. The control unit 34 receiving information contains the element And 81, the element OR 82, the counter 83, the first group of 84 elements AND, the register 85, the second g rup pu 86 elements And, element OR 87, elements And 88 and 89, trigger 90, element And 91, trigger 92, generator 93 pulses, element NOT 94, elements And 95 and 96, element OR 97, element And 98, decoder 99 and the third group 100 of elements AND, the Node 34 of control of the information contains the element AND 101, the counter 102, the first group 103 of the elements AND, the register 104, the second group 105 of the elements AND, the element OR 106, the element And 107 the element NOT 108, the element And 109, trigger 110, pulse generator 111, element OR 112, delay element 113, decoder 114 and the third group 115 elements The device operates as follows m For service requests from the blocks, they are received at the inputs of blocks 2 and 3. Each block 1 can place two applications: an application for receiving information and another for information. Applications at the inputs of blocks 2 and 3 may be masked by the instructions of processor 8. If processor 8 is free, i.e. The subscriber service is not occupied at the moment, and if there are no applications at the inputs of block 3 that require immediate service, then in block 2 it is the review of the service request. When the first application is found, its number is transmitted through block 7 to processor 54 of the sys- tem 8, after which the service of this application begins. During the service of the subscriber, the viewing of the requests in block 2 is stopped and resumed again after the end of the service of the preceding application. In block 3, the request is constantly scanned and, when the request is found, a processor interrupt (auto-break) signal is interrupted, which goes through bus 14 to the inputs of processor 8 and block 7. Upon receipt of this signal, processor 8 stops executing the program and executes the program. The number of which enters through block 7 from block 3. After the program is loaded, the processor 8 resumes execution of the interrupted program. In this way, the exchange of subscriber requests is initiated. The process of information exchange is carried out by the commands of processor 8. All subscribers of the system and blocks 1 are assigned numbers from 1 to M, where M is the number of subscribers in the system. If there is an exchange on the bus 21, the processor 8 outputs the code of the block number 1 (subscriber's address) and the command code. Block 6 selects commands addressed to blocks 1 and places an address on bus 10, and on bus 11 a command code to be executed. The address and command are received via bus 10 to all blocks 1. Each block 1 identifies the address present on buses 10. Block 1, which identifies the address, accepts the command for execution, connects to bus 12 or 13 and organizes the exchange of information between the subscriber and the processor. When transmitting information from the subscriber, the corresponding block 1 is connected to the buses 13, when transmitting information to the subscriber perceives information on the buses 12 and brings it to the subscriber. It is possible to exchange information between a pair of subscribers without bringing it to the processor. The device implements the following types of information exchange: subscriber-processor without information conversion. In this case, the information from the source subscriber through its block 1 enters the tires 13, then through the tires 19, 20, 17 enters the process; processor - subscriber without information conversion. The information from the processor via the busses 21 is fed to the buses 12 and through block 1 is communicated to the subscriber-receiver;

subscriber - processor with information conversion. In this case, the information from the subscriber-counter from the bus 13 comes through the block A, the bus 17 to the processor;

processor - subscriber with the conversion of information. Information from the processor via buses 21, 19, through block 4 enters the buses 20, 12 and through block 1 is communicated to the receiving subscriber;

subscriber - subscriber without information conversion. In this case, the information from the source subscriber from the tires 13 via the tires 19 enters the buses 12 and through the block 1 enters the subscriber-receiver;

subscriber - subscriber with information conversion. Information from the source subscriber from the bus 13 via block 4, bus 20, 12, block 1 arrives to the subscriber receiver.

Block 6 works as follows

From the processor 8, the following groups of exchange control commands come to the input of block 6 via buses 21:

Send information, Receive (receive information on the path: subscriber source - processor);

Send information, Receive information from the subscriber to the processor via K bits, Retrieve information from K bits, Receive (receive information on the path: subscriber - source - information conversion block 4 - processor 8);

Receive information, Vschatcha (delivery of information on the path: process 8 - subscriber-receiver);

Receive information, Receive information from the processor for the subscriber to K bits. Issue information on K bits, Issue issue of information on a path: processor 8 - unit 4 information conversion - subscriber-receiver);

Send information, Receive information, Mutual exchange (receiving information on the path: subscriber-source - subscriber-receiver);

Send information, Receive information, Receive information from the subscriber to the subscriber on K raer doe, Issue information on bits, Mutual exchange (receiving information on the path: subscriber-source unit 4 converting information of the subscriber-receiver).

Commands to block 6 come in the form of control words. The node 23 selects control words (chains of signs of control and information words are not shown).

The control word consists of two parts: the binary code of the command and the binary code of the address of the node to which the command is intended. The address code from the output of the node 23 post to the input of the node 24, and the command code to the inputs of the node 25 and the decoder 26. The node 24 converts the binary code of the address into a paraphase code, i.e. a code in which two tires correspond to each bit: for direct and inverse values. The paraphase address code is spread over all positions to install blocks 1 (bus 10), as well as block 2 and block 3. Tires 10 are supplied to the blocks listed in a strictly fixed manner according to the addresses of subscribers, so that when issuing the code to tires 10 addresses on the address inputs of only one of blocks 1, all units are present. Commands from processor 8 can be addressed to both subscribers (blocks 1) and internal nodes. Internal commands include control commands for block 2, block (Set mask commands, Continue search for orders, etc.), Block 5 (Receive — switching buses 19 and 20, Issue — switches 21, 12, Interchange - switching buses 19 12, Receive information from the subscriber for the processor in K bits - write a zero value to the switching register 29 of block 5 and set a block to process the Receive command; Receive information from the processor for the subscriber to the K bits of switching buses 21, 19 and 20, 12 and establishing a lock to test the command Vshchacha Receive information from the subscriber for the subscriber according to K bits - switching buses 20, 12 and establishing a block for testing the command Mutual exchange. Blocking the working of the above commands is made only in respect of block 5, Upon subsequent receipt of the commands 23 in the node 23 Receive the test consists in removing the blocking flag and forming the Start Exchange command for block 4. The block decoder 26 detects the internal commands and sends them to blocks 2-5 (bus 15 to block 4, bus 22 to blocks 2, 3 and 5 Node. 25 commands via bus 16 and decoder 26 through bus 15 transmitting commands to block 4. If bus 8, processor 8 issued a command addressed to block 1, then n are the signals on the outputs of the decoder 26, which allow passing the address and commands to buses 10 and 11, If at the output of processor 8 there is a command addressed to block 4, a signal appears at the output of decoder 26 that permits the passage of the command to bus 16. Command codes from control unit 6 to blocks 4 and 5 are given in tab. 1 and 2. The information switching unit 5 operates as follows. The command codes of the block 6 of the block 6 are transferred to the register 29 of the block 5, Block 5 opens, depending on the incoming command codes, the corresponding AND group of elements And performs the commutation of the information buses in accordance with the table. 2: 00000- tires 13, 17, all elements And are closed; 10,000 - tires 19, 2.0, open group of 28 elements And; . 01001 - tires 21, 19, 20, 12, elements AND groups 2 32 are open; 00010 - tires 21, 12, elements AND groups 31 are open; 00001- tires 20, 12, elements AND groups 32 are open; 00100 — buses 19, i2, open group AND 30 elements I. In block 4 of information width conversion, switching input node 33 is intended for switching receive buses in accordance with the source subscriber size, receiving control node 34 — for organizing and control information reception accumulation register 35 - to accumulate information from the source subscriber node-l 36- to control the accumulation register to zero value after outputting information from it, output word switching node 37 - for switching the output buses in accordance with the bit Tew subscriber receiver and control unit 38 vschachi - for organizing and controlling the output of information. From block 6, buses 15 and 16 send the command codes in nodes 34 and 38 in accordance with the table. 1. Depending on the command value, the nodes 34 and 38 send signals to the nodes 33 and 37. When the signal to the node 33 (bus 39) is received, information is received from the bus 13 to 40, to the register 35 in accordance with the source subscriber size. When signal is high at node 37 (bus 51); information is output on the buses 41 to the receiving subscriber in accordance with its size and to the output information control unit 36 when the corresponding commands are received from the node 38 via the tires 47-50. Node 34 generates and issues signals to nodes 36 and 38 of control 1e via buses 43 and 44. Nodes 36, when detecting the absence of information on register 35, generates an end of work signal and sends bus 34 to node 34. A group of 52 And elements is designed to receive information from subscribers sources on a register of 35 word for 8 bits, a group of 53 elements Received information from subscribers' sources on a register 35 word for 12 bits, a group of 54 I elements - to receive information from source subscribers to a register 35 word for word 16 times rows, the group 55 elements and - for receiving from subscribers information on the source register 35-word by 24 discharge. Their node 34 busses 39 receive the corresponding codes of signals, which sequentially open the elements of And the corresponding groups and compute, tires 13 and 40 mutate. The codes of the signals are given in Table. 3. In node 37, the computation of the output words of the group 56-59 of the And elements is intended to give information to the recipients in the register 35 word for words 8, 12, T6 or 24 bits. From node 38 via buses 51, the corresponding codes of the signals are inserted, which successively open the corresponding groups of AND circuits and commute the buses 41, 17 (20).

Node 36 operates as follows.

Depending on subscriber-receiver (receiving 8, 12, 16 or 24 bits) from node 38, buses 47, 48, 49, or 50 receive OR 60 signals, which are accumulated on counters 62, 63 or 64 and remotely on the decoder 66, 67 or 68. The decoder, for example 67, allows the passage of information from the bus 41 to the element SHI-NO 73.

When reading from the register 35 of the next word for the subscriber-receiver, the availability of information on the register 35 of the next (unread) words is checked.

If the remaining words are zero, then the elements OR 70, 73 or 76 generate a pulse signal, which via bus 42 enters node 34, where, in the presence of a KP signal (end of transmission), the latter is read and sent to the receiving subscriber, and the signals coming from the node 34 via the tires 43 and 44, set the block 4 to the initial state. If there is no KP signal, then zero words are read for the destination subscriber. Codes of input and output signals of the decoders 66-68 are given in table 4.

In the information receiving control unit 34, the decoder 99 is designed to generate codes for the control signals for receiving information, the OR 82 element is used to combine the launch busses of the node 34, the counter 83 is used to record the command code from the register 85 and the subsequent cyclic subtraction of the unit.

Elements 84 are intended to write the command code to counter 83, register 85 to store the command code received from block 6, trigger 92 to store the QP signal from the source subscriber until the end of the last information word to the receiving subscriber, pulse generator 93 to generate two pulses after the next start of the elements And 89, the element HE 94 - to control the element 95 and after setting the counter 83 to zero, the element 95, intended to start the node 38, after completing

the operation of the node 34 and the resetting of the node 36, the element AND 96 for issuing the KP signal to the subscriber-receiver and the resetting of the nodes 36 and 38.

From block 6, buses 15 and 16 receive a command code and a control write pulse. The command code through elements AND 86 is written to register 85, after which from block 6 bus 15 receives code 100 (Start exchange) on the element OR 82, as a result of which the command from register 85 is written to

counter 83 through elements AND 84. The command from the outputs of counter 83 goes to the element OR 87 and from the output of the element OR 87 to the input of the element And 89 and to the inputs of the element NOT 94. When the source signal comes from the subscriber-source to the other input of the element 89 And the UE signal ( receiver control) at the output of the And 89 element is generated by starting the 1st signal, which is fed to the input of the generator 93. The generator 93 produces a series of two pulses that arrive at the counting input of the trigger 20, to the inputs of the And elements 81, 88 and 91. The first pulse generator 93 opens the element And 88 and enters on with etchik 83, wherein the content is decremented by one. The second pulse of the generator 90 through the element And 81 is fed to

5 inputs of elements And 80 and to the subscriber source as a control signal UI (source control). Control information from register 85 and counter 83 via elements AND 100

0 enters the decoder 99. The control information from the decoder 99 enters via bus 39 to the node 33 of block 4. The control information codes received to the decoder 99 and from it,

5 are given in table. 3. The next cycle of control information generation for the node 33 begins after the arrival from the subscriber-source to the input of the control signal element 89

0 When resetting the counter 83 to the input

element 95 and through element NOT 94 receives a potential signal and the second

pulse generator 93 through the element And 95 enters the nodes 36 and 38 and transfers control to the node 38 (makes it start). The node 38 at the end of the control of the next part of the information to the subscriber-receiver starts up the node 34 through the AND element on buses 45 and 46. When a KP signal arrives from the subscriber-source signal to the trigger 92 from the output of the trigger 92, the potential signal is received from the And 91 and 96 elements . The second pulse of the generator 93 through the element And 91 sets the counter 83 and the register 85 to zero and through the element AND 95 enters the nodes 36 and 3 The next signal from the node 36 through the element OR 97 or from the node 38 through the elements AND 98. And OR 97 comes through element 96 of the subscriber to the receiver in the form of a KP signal and nodes 36 and 38 for setting the circuit elements to the initial state. In the information management control unit 38, a decoder 114 is designed to generate information reception control signal codes and a node 36, a counter 102 is used to record a command code from a register 104 and then cyclically subtract from the content of the unit, a register 104 to store the command code received from block 6 before the exchange is completed, the pulse generator 111 - to generate two pulses after the next start by the element 109, the delay element 113 - for the relative delay of the trigger pulse of the node 34 for the end of the read and a command register 104 to the counter 102. From block 6 -by buses 15 and 16 receives the control commands and recording pulse code. The command code through the elements 105 is written to the register 104. The triggering pulse from the node 34 after accumulating information from the source subscriber on the register 35 via the bus 43 is supplied to the elements 103 and the delay element 113. The information from register 104 is written to counter 102. After the information is written to counter 102, a pulse from delay element 113 is passed through the OR 112 and AND 109 elements to the first input of the generator 11, which produces two pulses, the first of them goes through AND 107 the counter 102, where the content is reduced by one, and the trigger 110 is triggered by one, the second impulse through the AND 101 element enters the inputs of the AND elements 115, the receiving subscriber in the 1st type of UE signal, and overturns the trigger, PU in the initial state. The qi information from the register 104 and the counter 102 through the elements 115 goes to the decoder 114. The information (command) from the decoder 114 via buses 47, 48, 49 or 50 and 51, depending on the format of the subscriber-receiver word (8, 12, 16 or 24 bits) enters the nodes 36 and 37. The next cycle of code formation on the decoder 114 is carried out after the next start of the generator 111 by the UE signal from the receiver receiver through the elements OR 112 and AND 109. When the counter 102 is zeroed through the elements OR 106, NOT 108 node 34 receives a potential signal. The second pulse of the generator 111 in parallel with the reading of the last word of the register 35 to the subscriber-receiver arrives through the bus 46 to the node 34 and performs the next launch of the node 34. The next launch of the node 38 is performed by the node 34 via the bus 43. When a signal comes from the node 34 via the bus 44 the elements of the assembly 38 are reset (the reristor 104 and the counter 102 are zeroed). Thus, the proposed device, having transformed the format with reference to the subscriber type by hardware, provides an increase in its performance.

131180905.

Continuation of the table 13, 17 00000 Reception of information by the processor from the subscriber of the source through the information conversion unit 19, 20 10000 Reception of information by the processor from the subscriber of the source directly 14 Continued table. 2 by the source channel through the information conversion unit Issuing information by the source subscriber to the receiving subscriber directly

Table 4

Z)

hch

I

and

fw

.BUT

 UTCHTTT, IZO

26

V

- - h / 4 27 I

 i

22/75

/ b

12

Fig.Z

I I

 to i

15 46

Fy

(ff8) (} 7) (Mlj

t (f (8) {1) (jf () msh1b)

(g5) h) {1)

(P8) (35) (IS) 1 (

/ V

AAJAHAAAFAAf

ss

7

/ Vm

 A /

/ V /

UE Ull3)

i

From a receiver receiver

I7f20j tf

S.-i-j

/

HI

L.

S2

 /

V

.

L

G

/ J

55

-CC

/ V -F /

31

96

ij

zg fA /

97

86

, Ц5 6

9S

KP

Ow aWonentaprennika

51

Jl

1 A / i I I I A j, 1 i I I I

 k

t

I. I

t

I n b

ry

5} .Jff

45

m

From the subscriber. receiver

Figz

Claims (4)

1. DEVICE FOR INFORMATION EXCHANGE, comprising a group of communication blocks with a subscriber, switching blocks of commands and information, a decryption block of an address and commands, an interrupt block and a priority block, wherein the outputs of the request signals of communication blocks with a subscriber of the group are connected to the group of request inputs of the priority block and block interrupts, address inputs - with the address inputs of the priority block and the interrupt block and with the address output of the address and command decryption block, the first output of the command code of which is connected to the command inputs of the communication blocks with the subscriber of the group, and information inputs and outputs of which are connected respectively to the first information outputs and the input of the information switching unit, the control input of which is connected to the second output of the command code of the address decryption unit and commands and the control inputs of the priority block and interrupt unit, the second information input of the information switching unit is connected to the information output communication with the device processor, and the third information input - with the information input of communication with the device processor, the input of the address decryption unit and commands and command inputs of the priority block and interrupt block, the output of the command switching block is the output of the device request address, the first and second information inputs of the command switching block are connected respectively to the output of the priority block and the first output of the interrupt block, the second output of which is connected to the control input of the command switching block and the processor interrupt output of the device, characterized in that, in order to improve the performance of the device, a block for converting the bit depth of information is introduced into it, moreover the information input of the information bit conversion unit is connected to the information outputs of the communication units with the group subscriber and the third information output of the information switching unit, the output of the information bit conversion unit is connected to the information output of communication with the device processor and the third information output of the information switching unit, and the command code input and input control modes of the unit for converting bit depth information are connected respectively with the third and fourth outputs of the command code block and decrypt addresses and commands. 2. The device according to π. 1, characterized in that the information bit conversion unit contains an input word switching unit, the information input of which is an information input of the unit, an accumulation register, an output word switching unit, the first output of which is an information output of the unit, and the information input is connected to the information input of the monitoring unit the zero state of the accumulation register and through the accumulation register - with the output of the input word switching node, the information reception control node, the first control output of which is connected nen with the control input of the input word switching node, and the information output control node, the group of outputs of which is connected to the control mode input of the zero state register of the accumulation register and the control input of the output word switching node, the output connected to the synchronizing input of the information reception control node, and the start inputs and stop - respectively, to the start and stop inputs of the information delivery control unit and to the second and third control outputs of the information reception control unit, start input coupled to an output node control issuance information input mode control inputs and commands code reception control units and output of information are respectively input mode and the control input of the instruction code, and data inputs and outputs form, respectively * information input and output unit, 3. The device according to paragraphs. 1 and 2, characterized in that the control unit for receiving information contains a register, counter, three groups of AND elements, a decoder, the outputs of which form the first control output of the node, two triggers, a pulse generator, an element NOT, seven AND elements and three OR elements, the output of the first OR element is connected to the first inputs of the AND elements of the first group, the outputs of which are connected to the information input of the counter, the information input of the register is connected to the outputs of the AND elements of the second group, the first inputs of which form the input of the node command code, w the first inputs of the AND elements of the second group and the first input of the first: OR element are connected to the node mode control input, the first inputs of the AND elements of the third group are connected to the outputs of the register and counter, the outputs to the inputs of the decoder, and the second inputs to the output of the first element And, the outputs of the second and third elements And are connected respectively to the subtracting input of the counter and the start input of the pulse generator, the output of which is connected to the counting input of the first trigger and the first input of the first, second, fourth and fifth elements And, the outputs are six o and the seventh AND element are connected respectively to the first input of the second trigger and to the second input of the first OR element, the outputs of the counter are connected to the inputs of the second OR element, the output of which is connected to the first input of the third AND element and through the NOT element to the second input of the fifth AND element, the inverse trigger output is connected to the second input of the second AND element, and the direct output is to the second inputs of the first and fourth AND elements, the output of the fourth AND element is connected to the reset inputs of the register and counter, and the third input is connected to the output of the second trigger ger and the first input of the sixth AND element, the second input connected to the output of the third OR element, the first input of which is the synchronization input of the node, and the second input is connected to the output of the seventh AND element, the first and second inputs of which form the node start input, the second inputs of the AND elements of the first groups are connected to the outputs of the register, the second inputs of the second trigger and the third element And form the information input of the node, the outputs of the fifth, sixth and first elements And are respectively the second and third control and information in odes node. 4. The device according to paragraphs. 1 and 2, characterized in that the control unit for issuing information contains a decoder, the outputs of which form a group of outputs of the node, three groups of AND elements, a register, a counter, an element NOT, a delay element, three AND elements, a pulse generator, two. an OR element and a trigger, and the counter inputs are connected to the outputs of the And elements of the first group, the first inputs of which are connected to the outputs of the register, the inputs connected to the outputs of the And elements of the second group, the first inputs of which form the node command input, and the second inputs are connected to the mode control input the node, the outputs of the register and counter are connected to the first inputs of the AND elements of the third group, the outputs of which are connected to the inputs of the decoder, and the second inputs to the output of the first AND element and the information output of the node, the outputs of the counter are connected are connected to the inputs of the first OR element, the output of the pulse generator is connected to the counting input of the trigger and the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the direct and inverse outputs of the trigger, the output of the first OR element is connected to the input of the element NOT and the first input of the third And element, the output of the pulse generator connected to the start input, and the second input - with the output of the second OR element, the first input of which is the information input of the node, and the second input through the delay element is connected to w rymi inputs of AND gates of the first group and the input of the start node, the register reset inputs of the counter and connected to the stop input node.