SU1141436A1 - Device for transmission of digital information - Google Patents

Abstract

. 1. DEVICE FOR TRANSFER OF DIGITAL INPUT 1Аtion, containing sources of information, the first outputs of which are connected to the corresponding information inputs of the switch, blocks of the buffer memory and the generator of clock pulses, characterized in that, in order to improve the speed of the device, a time-program block is entered into it , keys, trigger, address decoder, delay element, comparison unit, address generators and counters, information source outputs are connected to the information input through the corresponding address generators the first key, the output of which is connected to the address of the address decoder and through the delay element to the information input of the second key, the output of the second key is connected to the information source passes and the first control input of the switch, the outputs of which are connected to the inputs of the corresponding buffer memory blocks, the first outputs of which are The outputs of the device, the second outputs of the blocks of the buffer memory are connected to the first inputs of the corresponding counters, the outputs of which are connected by the first input of the block. comparison, the output of which is connected to the second control input of the switch, the output of the clock pulse generator is connected to the second input of the comparison unit and the first input of the program-time block, the information and control outputs of which are connected respectively to the second inputs of the counters and combined with the third input of the comparison unit and the first trigger input, the outputs of the address decoder are connected to the second inputs of the prog (L-block-time block and the trigger, the outputs of which are connected to the control inputs of keys. 2. Device in clause 1, stating that the soft-time block contains a switch, address generator and shift registers, the first outputs of which are connected to the corresponding inputs of the switch, the outputs of which are connected to the corresponding inputs of the address generator , the combined first inputs and the second inputs of the shift registers are respectively the first and second inputs of the program-time block, the output of the address generator and the combined second outputs of the shift registers are information and control, respectively moves the program-timing unit. 3. The device according to claim 1, stating that the address decoder is made on the signal conditioners, limiters and filters, the filter outputs through the corresponding limiters are connected to the inputs of the corresponding formulas

Description

Signal senders whose outputs are outputs of an address decoder, inputs

the filters are combined and are the input of the address decoder.

The invention relates to automation, in particular to the transmission of information and can be used to transmit digital messages from geographically distant or a large number of low-level localized sources, information,.  from which can be transmitted on any of a given set of output channels.  A device for transmitting digital information is known, comprising two data processing units, whose information buses are connected to a system memory block for programs and data, I / O blocks that are controlled by addresses transmitted via the address bus, and special control signals, a state memory block connected to the information bus, logic circuits, two blocks of buffer memory, the output of each of which is connected to the information bus of the data processing unit connected to it, the input from the information Drew a second data processing unit, the address deshi frator, rpjoiny switches 1.  However, the device is characterized by high complexity of control and the impossibility of its use in structures containing more than two data processing units (processors, transmitting units, etc. d. ) The closest technical solution to the present invention is a device for transmitting digital information containing information sources, the first outputs of which are connected to the corresponding information input of the switch, blocks of the buffer memory, clock generator, the output of which is connected to the control input of the switch, input blocks - view of information connected via corresponding peripheral processors with inputs of the main memory unit connected to the central processor 2.  The disadvantage of the device is the low speed, due to the rigid attachment to each source of the corresponding channel.  Therefore, if there are several queues of messages in a single shsh buffer memory, waiting for transmission through the corresponding channels, and one or several free (or less loaded) channels, it is impossible to use the latter for transmitting in other output message blocks.  The aim of the invention is to improve the speed of the device due to the flexible redistribution of source messages between channels, taking into account their current workload.  The goal is achieved in that the device for transmitting digital information containing sources of information, the first outputs of which are connected to the corresponding information inputs of the switch, blocks of the buffer memory and the clock generator, has been introduced a program-time block, keys, trigger, address decoder, element delays, block comparisons, address generators and counters, the outputs of information sources through the corresponding address generators are connected to the information input of the first key, the output of which is connected With the address of the address decoder and through the delay element with the information input of the second key, the output of the second key is connected to the inputs of information sources and the first control input of the switch, the outputs of which are connected to the inputs of the corresponding buffer memory blocks, the first outputs of which are device outputs, the second the outputs of the buffer memory blocks are connected to the first inputs of the respective counters, the outputs of which are connected to the first input of the comparator unit, the output of which is connected to the second control input of the switch Pa, the clock pulse output is connected to the second input of the comparison unit. And the first input of the program-time block, whose information and control outputs are connected respectively to the second inputs of the counters are combined with the third input of the comparison unit and the first trigger input, are connected to the second the inputs of the program-temporary block and the trigger, the outputs of which are connected to the control inputs of the keys.  At the same time, the soft-time unit contains a switch, an address generator and shift registers, the first outputs of which are connected to the corresponding inputs of the switch, the outputs of which are connected to the corresponding inputs of the address generator, the combined first inputs and the second inputs of the shift registers are respectively the first and second inputs the gram-time block, the output of the address generator and the combined second outputs of the shift registers are respectively the information and control outputs of the software-time block.  In addition, the address decoder is made on signal conditioners, limiters and filters, the filter outputs are connected to the inputs of the corresponding signal conditioners, the outputs of which are the outputs of the address decoder, the filter inputs are combined and are the address decoder input.  FIG.  1 shows an internal circuit diagram of a device for transmitting digital information; in fig.  2 is the same as the address allocation block; in fig.  3 - the same, program-temporary block.  A device for transmitting digital information (FIG.  1) contains n sources of information 1, generators 2 addresses, switch 3, G (1 blocks 4 buffer memory, counters 5, keys 6 and 7, element 8 eksderki, trigger 9, decoder 10 addresses, software-temporary bl. ca. 11, comparison unit 12, clock generator 13, common pshnu 14, and in the general case m 4t p.  Each unit 4 is connected with a corresponding output channel by means of a modulator and a transmitter (not shown).  The device implements the principle of free access of address signals generated by generators 2 to a common bus (link).  The principle of free access is used in cases where it is possible to arrange access of sources to the common path n (when sources are geographically remote from each other) or impractical (with a large number of low-level localized sources).  Along with many advantages - simplicity of hardware implementation, high utilization of the common path, efficiency, etc. d.  free access has such a significant disadvantage as a distortion of cischals due to their imposition and, as a consequence, the need for their re-transmission.  The frequency of signal overlap with free access is determined by the PM-e-1 ratio. where f is the common path loading; I - the intensity of the appearance of requests; T - the time of transmission of the request on the common path.  In the proposed device, the loading of the common path is no more than 1-3%, since it is not the informational messages that are transmitted by it, but their addresses, which are of several orders of magnitude smaller.  Moreover, the probability of address overlapping, as is easily seen, is a fraction of a percent.  Protection against false triggering of the device in case of address distortion is performed by the address decoder 10.  The device works as follows.  The source 1, if there is information to be transmitted, from the control output, supplies a sending signal (for example, a logical unit) to the input of the address generator 2, which counts the source address 1 to the common bus 14.  If key 6 is open, this address is fed to the input of the address decoder 10 and delay element 8.  The address decoder 10 serves to identify the addresses arriving at its input and can be implemented by various means.  FIG.  2 shows one of the possible implementations of the dustfrater 10 on the basis of the limiter 15 and the imaging unit 16 of the pulse (logical unit), and the binary filter 17.  Binary filter 17 (or otherwise matched filter for a binary signal) is characterized in that the signal at its output repeats the shape of the input autocorrelation function (matched with the filter). signal.  There are two possible binary fiyotra schemes: on the delay element, inverters and adders, and the multichannel correlator circuit 3.  Binary filter 17 i -th branch (, 2,. . . , p) the decoder 10 is constructed in such a way that when the address from the i -th source 1 arrives, the output voltage at the moment of the address termination exceeds the threshold level specified by the limiter 15.  In this case, if the input of the binary filter 17 receives the address of another source 1 or the address distorted due to overlaying, its output voltage is less than the threshold one, and there will not be any pulse (logical unit) on any of the outputs of the decoder 10.  Thus, the address decoder 10 is organized against the device’s false positives upon receipt of corrupted addresses.  Thus, if there is an undistorted address at the input of the encoder 10, its total number equal to the number of sources 1, an impulse (logical unit) appears at its corresponding output.  This pulse arrives at the corresponding input of the software-time unit 11 and at the first input of the trigger 9, which closes the key 6, thereby preventing addresses from other sources 1 from passing through, and opens the key 7, through which the address after passing the element 8 delays are fed to the first control input of the switch and to the inputs of sources 1.  Element 8 serves to delay the address by the time required to trigger the decoder 10, the trigger 9 and the key 7. Upon receiving its address, which is resolution for subsequent transmission, source 1 blocks the operation of address generator 2 and after a predetermined period of time necessary for connection with the corresponding output channel, reads information into one of the blocks of the buffer memory.  If a distorted address arrives at the input of the decoder 10, then there will be no signal at one of its outputs and no control actions are generated, t. e.  No source 1 receives permission to transmit.  In this case, the operation of the address generator 2 is not blocked, and it is after a certain period of time.  (time interval) re-reads the address in the common bus 14.  The generation intervals of the various generators 2 are chosen in such a way as to avoid repeated overlaps.  It should be noted that the correct choice of the generation interval for different generators 2 can be achieved by the almost complete elimination of address overlap during transmission over the common bus: Software time block 11 can.  be implemented by various means.  In particular, in FIG.  3 shows one of the possible implementations of block 11 on the axis of the matrix switch 18, the address generator 19 and the shift register 20 (distributors).  The number of shift registers 20 is equal to the number of sources 1, and the number of information outputs of the K-th (, 2,. . . , h) register 17 is equal to the number of channels (blocks 4) through which a message from K-th source 1 can be transmitted, t. e.  less than or equal to m  In addition to the informational outputs, each register 20 contains another control output.  Switch 18 is a standard element, n has n (m - number of output channels) of outputs and n n m n n inputs, each output of switch 18 connected to several of its inputs.  Which specific inputs and outputs of the switch 18 are interconnected is unambiguously determined by which output channels messages can be transmitted from each source 1.  So, for example, if p 3, and where information from the first source can be transmitted on the first and third channels, from the second to the second and fourth, from the third to the first, third and fourth, then the number of inputs of the switch 18 is 7.  Of these, the first two inputs are connected to the information outputs of the first register 20, the second two to the information outputs of the second register 20, the last three to the information outputs of the third register 17.  At the same time, the first output of the switch 18 is connected to the first and fifth of its input, the second to the third, the third to the second and sixth, the fourth to the fourth and seventh.  The presence of n (n is the number of sources 1) of registers 20 and switch 18 is due to the fact that in the general case, the messages of each source 1 can be transmitted not on all m channels, but only on several of them.  In the particular case when messages from any source 1 can be transmitted over any of m channels, instead of switch 18 and n registers 20, one register 20 is enough, and the number of its information codes must be equal to rm.  The impulse (logical unit) from the corresponding output of the decoder 10 enters the register 20 of the block 11 and is written into its first cell.  According to the signals of the generator 13, this pulse is successively sent from one register cell 20 to another, thus causing the appearance of discrete equal pulses at the information outputs of the register 20 at discrete equal times from each other.  These pulses alternately arrive at the corresponding.  the input input of the switch 18, and then from the corresponding output to the corresponding input of the generator 19, which (depending on which of its inputs received a pulse) generates a certain address.  Addresses from the output of the generator 19 in series with the clock set by the generator 13, are fed to the inputs of the counters 5.  Counters 5 monitor the current load of the corresponding, channels.  In the case when the degree of filling of the corresponding buffer memory block 4 is used as the current channel load, when a message arrives in block 4, a pulse is fed to the summing input (first control input of the counter 5), and on the message output from block 4 - to the subtracting (second control input of the counter 5).  Thus, in this case, the contents of counter 5 correspond to the length of the most pending messages in the corresponding block 4.  Having received your address, the counter 5 formuru-.  The response message is by adding its contents (numerically) to the address.  Response messages are received at comparison unit 12, whose function is to determine the address of counter 5 with minimal content.  Comparison unit 12 can be implemented by various methods, in particular, on two perHctpax and K564I112 digital comparator.  In this case, a sequential algorithm for determining the minimum binary number is used, the first register being used to store the result of the comparison, t. e.  the minimum number obtained at the previous comparison cycle is second. Register — to write a binary number to be compared with previous ones.  If, as a result of the comparison, it is determined that the binary number in the second register is less than the binary number in the first register, then it is rewritten to the first register, otherwise, the contents of the first register are preserved.  In that case.  Moreover, if the two binary numbers being compared are the same, the contents of the first register are also saved.  The operation of block 12 is synchronized with generator 13, and the time interval between adjacent clock pulses generated by it is such that it accommodates both the request and the response signals.  After the comparison of all response messages of the counters 5 received during the operation of the program-time block I is completed, a certain binary signal is recorded from the control signal from block 11 in the first register of block 12.  number with empty (zero address).  This binary number sets the upper threshold q) aB of binary numbers and is the largest allowable channel load.  After the end of the survey, the counters 5, which is specified by the sequence of addresses appearing on the information output of the block 11 (on the information 68 outputs of the register 20. pulses), at the jTtpaBlating output of block 11 (the control output of the corresponding register 20), a pulse arrives at the input of trigger 9, which generates control signals, for example, a logical one and zero.  These signals arrive.  respectively, the inputs of keys 6 and 7, opening the key 6 and thereby permitting the passage of addresses through it from the generators 2, as well as closing the key 7.  The control pulse from the output of the block 11 also enters the input of the comparison block 12, on receipt of which the block 12 reads the channel address with the minimum current load to the second control input of the switch 3.  In the event that the current load of all polled channels is greater than or equal to a predetermined threshold (contained at the initial moment of the comparison cycle in the first register of block 12), the comparison block 12 reads empty (zero) when a control pulse arrives from the software-time block 11 address.  In this case, the switch 3 does not connect this source to any of the outputs of the device (communication channels).  Thus, the proposed device for transmitting digital information provides automatic redistribution of source messages between output channels, taking into account their current workload.  At the same time, the free access of active sources to the common switch, which connects the Active sources to the least loaded communication channels, is used.  In the case when the channel load reaches the limit value, the device provides an automatic delay in the beginning of the transfer of information by sources, thereby preventing the sources from accessing these channels and overloading them.  All this allows to increase the efficiency of information delivery to consumers, t. e.  the speed of the device, as well as more fully utilize the capacity of the existing communication channels.  During the operation of the known device, a rigid distribution of data streams over communication channels is ensured.  When channels are evenly loaded (this mode is most beneficial for the known), the average message delay time is determined by the ratio known from the theory of mass service

where p is the load factor of the Channels

connection; f - length information

messages; R - channel capacity

connection.

In the proposed technical solution, the redistribution of information flows is carried out on the basis of current information about the degree of congestion of output communication channels. For this reason, the following formula 4 is obtained for calculating the average delay time of a gagallic system: g - h

, .

From the above relations it can be seen that in this case the proposed technical solution allows c.

1 + p

 reduce the average message delay time, i.e., () increase

onepaijiBHocTb (speed) compared with the known. Since in the normal mode, the load factor of the communication channel is 0.8–0.9, with equal technical characteristics of the channels, we offer.

My device provides almost two-fold increase in efficiency compared to the known.

 If the number of channels, then, as shown by the simulation results on a computer, the potential gain of the proposed device compared with the known; proportional to the number fn, i.e. increases with the number of channels.

i

i

FIG.

Claims (3)

. 1. DEVICE FOR TRANSFER OF DIGITAL INFORMATION, containing information sources, the first outputs of which are connected to the corresponding information inputs of the switch, buffer memory units and a clock pulse generator, characterized in that, in order to increase the speed of the device, a program-time block and keys are introduced into it , trigger, address decoder, delay element, comparison unit, address generators and counters, information source outputs through the corresponding address generators are connected to the information input of the first of the key whose output is connected to the input of the address decoder and through the delay element with the information input of the second key, the output of the second key is connected to the inputs of the information sources and the first control input of the switch, the outputs of which are connected to the inputs of the corresponding blocks of buffer memory, the first outputs of which are the outputs of the device , the second outputs of the buffer memory blocks are connected to the first inputs of the corresponding counters, the outputs of which are connected to the first input of the comparison unit ι, the output of which is connected to the second the control switch input, the output of the clock generator is connected to the second input of the comparison unit and the first input of the program-time unit, the information and control outputs of which are connected respectively to the second inputs of the counters and combined with the third input of the comparison unit and the first input of the trigger, the outputs of the address decoder are connected with the second inputs of the program-time block and the trigger, the outputs of which are connected to the control inputs of the keys. 2. The device according to π. 1, the fact that the program-time block contains a switch, a generator. addresses and shift registers, the first outputs of which are connected to the corresponding inputs of the switch, the outputs of which are connected to the corresponding inputs of the address generator, the combined first inputs and second inputs of the shift registers are the first and second inputs of the program-time block, the output of the address generator and the combined second outputs of the registers shift are respectively the information and control inputs of the program-time block. 3. The device according to π. 1, the fact that the address decoder is made on signal conditioners, limiters and filters, the filter outputs through the corresponding limiters are connected to the inputs of the corresponding formors SU „, 1141436 signal generators, the outputs of which are the outputs of the address decoder, the inputs of the filters are combined and are the input of the address decoder.