SU1437864A1 - Device for servicing requests - Google Patents

Abstract

The invention relates to automation and computing, in particular to devices for priority service. The purpose of the invention is to expand the functionality by calculating priority query codes and organizing rational priority service based on using the values of the regression equations as priority codes. The goal is achieved by using a group of microcomputers, in which the values of the regression equations are calculated according to a given program, which are then used as priority codes received for servicing queries. For this, the device for servicing requests, containing the elements H, OR, OR-NOT, the priority code registers, the buffer register and the request register, the counter, the comparison node, the decoder block, the trigger trigger and the inhibit elements, are entered group of priority setting blocks, three groups of registers of i factors, element / delay, two groups of OR blocks of elements, two groups of OR elements, two groups of OR-NOT elements, group of NOT blocks of elements, control trigger, trigger of microcomputer start modes, elements t NOT, an element OR, two elements AND and a group of elements OR. 2 h.p.f. 4 il. and w 4 od h 00

Description

The invention relates to computer technology and automation, in particular, to priority service devices, and can advantageously be used in multi-computer computing systems for the purpose of promptly restoring computer software included in the computer system.

The purpose of the invention is to enhance the functionality by calculating priority query codes and organizing rational priority service based on using regression values as priority codes.

Fig, 1 shows a diagram of the device; figure 2 - block diagram of the decoders; FIG. 3 is a diagram of a comparison node; on figa block diagram of the algorithm of the microcomputer

The device contains a register 1 of the order, a group of inputs 2 for a wokJ group of elements AND 3, a buffer register 4, a group of priority registers 5, a group of blocks of elements AND 6, a group of outputs 7 of the device, a block of decoders 8j a group of elements OR 9, a group of elements AND 10 prohibition, register P of the number of free channels, a group of information inputs 12 devices a group of elements OR NOT 13, a counter 14, an element OR 15, a generator of 16 pulses, elements OR-NOT 17 and 18, a trigger 19, a group of blocks of elements OR 20, groups of factor inputs 21, 22 and 23 devices, groups of power units And 24, 25 and 26 elements 27 delay elements 27; 28; 29 and 30 factors; And 31, 32 and 33 block groups; OR 34 block groups; 35, 36 and 37 receive control groups; information inputs Z B, a group of output outputs 39 for managing the output of a cut; tatatae groups of information outputs 40, a group of priority setting blocks 41 (microcomputers), g a group of element blocks AND 42, a group of block elements HE 43p a group of elements OR NOT HE 44, a group of blocks of elements AND 43 and 46, a group of inputs 47 setting the operation mode, start input 48, trigger 49 re microcomputer start-up press, control trigger 50, elements AND 51 and 52, element NO 53, element OR 54, inputs 55 and 56 of the command input of the start signal of the microcomputer of the device, inputs 57 and 58 of setting the device priority maintenance discipline, group of elements OR 59, input 60 device start-up, inputs 61 of the decoder unit, outputs 62 of the decoder unit, comparison node 63, groups of comparison node 64 and 65, comparison node output 66.

The unit 8 of the device decoders contains the inputs 61 of the block, the outputs 62 of the block, the decoders 67, the bitwise analysis nodes 68, the elements of the HE 69 group, the elements of AND 70 of the group, the elements of And 71 of the group, the elements of ShSh 72.

The device comparison node 63 comprises the first 64 and second 65 groups of inputs, the output 66J decoders 73 and 74, the elements AND 75 of the group, the element OR 76.

The operation of the device is based on the use of well-known methods of predicting possible values of various indicators of the performance of technical systems, as well as processes and phenomena, proceeding in these technical systems, in particular in computers and in computing facilities. Prediction is performed using regression equations of a constant structure. In the proposed device, the numerical values of the priority codes received for servicing queries are formed from regression equations.

Forming the priority of codes is carried out taking into account values from one to three factors, the most influencing the reliability of computer software, a complex of computing facilities.

The calculation of the value of the regression equation for specific values of factors in the device is implemented programmatically in the microcomputer of group 41 (see Fig. 1). In the future, the value of the analyzed characteristic (indicator) of the efficiency of the functioning of a computer, calculated from the regression equation, acts as the priority code of the incoming code for servicing the application from the computer. Following this, in accordance with the values of the generated priority codes, the order of assignment of the available free resource, overwriting channels of the operating system of the computer, is restored to restore the normal course of the computational process. The device implements the calculation of the total third order regressive polynomial using one to three inclusive independent factors x ,,,

2,

view:

BUT

U eo

 +

a, x + + a,) xs

“+ A, + + +

+ agXjX, + a. + +

+

+

a, 5x | x

a (bH

Where

4 +

+ a ,, x | xs + + a "x | x, j, +

a, x |

a "gx | +, (1)

the predicted value of the variable y characterizing the process of functioning of a computer;

and - parameters of the regression equation.

The priority codes of incoming requests are determined by software by calculating the values of out of generation (1) using a microcomputer of group 41. The operation of the microcomputer is organized in accordance with the algorithm shown in FIG. 4. In FIG. 4 the following notation is accepted: in block 77, the formation at the output of 35 micro computers 41 of the control signal for receiving the 1st operand (values

35

The first factor XO, in block 78 of orga-ZO of computed values, the reception and recording of this operand is stored in the microcomputer memory, in block 79, the output of 36 micro-computers 41 of the control signal of the 2nd operand is received (the second jporo factor xd) , in block 80, this operative is received and recorded in the microcomputer memory, in block 81, the microprogram 41 produces the formation of the 3rd operand receive signal (value of the third factor Xj) at block 37 The reception and recording of this operand is organized in preeptive codes by means of equations (1), as well as analysis of the physical essence of x, x, xd, x, xg, xj, and y, can be zero or positive values in the regression equation can be numbers as well as negative, but known in advance, zi can be made in advance about a known number of necessary operations for adding, multiplying tani. This will allow

The microcomputer, in block 83, the calculation of the value of y is organized in accordance with the microcomputer work. In addition, according to expression (1), in the calculation block of the calculation program y 84, the generation of priority codes by means of the equation equation (1) is organized, and the result of the analysis of the physical essence of the possible values x, x, Xd can be seen Xg, Xj and y can be zero or positive numbers. The dimensions in the regression equation (1 can be numbers both positive and negative, but all are known in advance. In connection with the floor, you can make a program in advance with a known number of necessary addition, multiplication, and draw operators. This will determine

The expression (1) will be required only for the subtraction operation. It will be present at the final calculation of this and will be determined by the difference between the sums of positive and negative polar terms (1

In the course 39 of the microcomputer 41 of the control signal for outputting the calculation result (the value of y corresponding to the incoming request), in block 85, the calculation result of the microcomputer is output to the outputs 40.

As microcomputers of group 41, microcomputers can be used, which include at least three input / output channels with data fixation or at least one input channel and one output channel with fixation

data. In the latter case, the microcomputer must have at least three outputs, each of which controls the flow of data from one direction and one output that controls the output of the result of calculations in one direction. In addition, the microcomputer must have a launch input for solving a program stored in the program memory (PC) and an input for setting the operation mode.

The micro computers of the group 41 are intended for calculating the values of PC- (, ..., n, n - the number of device subscribers) by solving the regressive equation, (1). In this case, before the start of the device operation in nahiJiTb microelectronics, the parameters of the equation of regression are entered - and the program calculates the y values; input 47 signals high or low level sets the operation mode of the microcomputer.

The operation of the microcomputer in accordance with the algorithm begins at the signal received at the input 48 of the start of the microcomputer. Nodes for recording initial data and programs in the memory of the microcomputer are not shown in FIG. Nz analysis of physical sush, calculated values

u hjni

five

O computed values o

in the works of microcomputers. In addition, when calculating the calculation program

0

five

priority codes by solving equation (1), as well as from the analysis of the physical essence of the possible values of x, x, xd, that x, Xg, Xj and y can be zero or positive numbers. The parameters in the regression equation (1) can be numbers, both positive and negative, but always known in advance. In this connection, it is possible to pre-compile a program with a known number of necessary addition, multiplication, and subtraction operators. This will determine the cycle

suis

Expression (1) will require only one subtraction operation. It will be carried out at the final stage of the calculation of y and determined by the difference between the sums of the positive and i negative terms of the polychrom (1).

As an example of a microcomputer of group 41, a microcomputer of the K 1816, 1Sh1816BE49 / 9 series can be used.

The principle of operation of the block of decoders 8 is based on the use of decoders to search for the smallest of n pixels.

51

Especially {: and the build ability of block 8 is that the first outputs of the de scramblers are not used. At the first outputs of the decoders, unit signal levels will be formed only in cases where the zero code arrives at their inputs. Thus, the block 8 of decoders produced the selection of the smallest of the numbers received at its inputs, the values of which are different from zero. If on all inputs of block 8 5y, zero codes are present, then no signals will be generated at the outputs of block 8.

The principle of operation of the device 63 for comparing the device, as well as the block 8 of the decoders, is based on using the decoder outputs of the same name to determine whether two two villages are equal. In case of equality of the two numbers received at the inputs of the corresponding decoder in 5, the unit signal levels will be formed at the inputs of the same name.

Before starting the operation of the computer for the CWS computer, the regression equations (l) s were synthesized; in addition, a program for calculating the values of the regression equation (1) and the parameters a ,,,,, and this regression equation was recorded in the microcomputer memory. All registers 28j 29 and 30 factors, the register of registers and the buffer register 4 are reset. Trigger trigger 19 is set to zero. The trigger 50 ynpaBJ i.e. is set to the state corresponding to the selected priority service discipline. Let the trigger 50 be set on input 58 to the zero state. In this case, the priority codes computed in the microhigma 41J groups will be inverted in the NOT groups 43 blocks and the priority registers 5 will write the reverse codes of numbers received from the micro-computers 41 outputs. Trigger 49 is set to the state corresponding to the required type of micro-computers 4 trigger signal Let trigger 49 be set on input 56 to the zero state. Then the high level start signal, unavailable at the device input 60, will be inverted on the element HE 51 and will go through the elements AND 52 and OR 54 to the start input 48 of the microcomputer 41, in this case the microcircuit of group 41 will start to work on the zero signal

646

level In addition, the counter 14 is set to one. The 1I register is a free number code.

channels that can be used to restore the FAC computer programs, the pulse generator 16 generates clock frequency signals that are not available at the inputs of the AND elements

10 zalreta.

The operation of the device begins with the arrival of signals from requests for inputs 2 to write to the corresponding bits of register i and the buffer register 4o. Since at the initial moment of time the registers I and 4 are zero, there are zero signal levels at the inputs of the ISh1-11E 13 elements at the outputs of elements 1SHI-NOT 3

form a high level signal. A high level from the output of elements W1NE 13 at the control input blocks of elements AND 24, 25 and 26 groups, allowing passage through the inputs 21,

22 and 23 factors of the values of factors x / t 5 XQS Xj to write to the corresponding registers 28, 29 and 30 factors. Along with the receipt of the next write request to the corresponding register register. 1 to the corresponding positionally to this request groups of inputs 22 and 23 factors of the group, the factor value codes are received. Since the blocks of elements And 28,

29 and 30 groups are open, the values of these factors enter the inputs of the corresponding factor registers and are written in them. After the incoming request is written to

bits of registers 1 and 4, at the output of the corresponding element 1LI-LE of group 13 will generate a signal of zero level. This zero-level signal will go to the control inputs of the corresponding blocks of elements of the 24, 25, and 26 groups and prohibit the passage of any values of factors through them to write to the corresponding registers 28, 29 and 30 groups of factors before

as long as the incoming request is not served by the device. Thus, when asynchronous requests are received by device 2 inputs, these requests are recorded into the corresponding bits of register 1 of the request, and the values of the factors causing the formation of these requests are received into the corresponding registers of 28, 29 and 30 group factors. Device operation

the priority service of incoming requests begins with a high level signal received at input 60. With this signal, all priority registers 5 are zeroed out and the input of request signals to inputs 2 of the device is blocked. The circuits for blocking incoming requests by inputs 2 are not shown in the block diagram of the device shown in Fig. 1.

In addition, since the control trigger 49 is set to the zero state before the device starts operation, the device start signal arriving at the input 60 is inverted on the HE 53 element. Thus, the low level of the signal comes from the HE 51 output through the AND 52 elements. and OR 54 to the inputs 48 of the micro-EBM group. Since at inputs 47 there is a constantly zero signal level setting the operation of microcomputers of group 41 with internal memory, when Lenin arrives at the inputs 48 of microcomputers of a low level signal, all microcomputers of group 41 are started to execute the program recorded in their memory. The operation of the microcomputer of group 41 is organized in accordance with the algorithm presented in FIG. In this case, the following actions will be performed in the microcomputer of group 41. When the algorithm block 77 is implemented, a set of commands is organized which organize the formation of the first operand reception signal at the outputs of 35 micro-computers. In this case, a single-level signal will be generated on the buses of 35 micro-computers of the group 41, which will allow the arrival of numbers from the outputs of the group 28 registers through blocks of elements AND 31 groups and OR 34 groups on information inputs 38 of the corresponding microcomputers of group 41. In block 78, commands are executed that organize reception of the signals received from the outputs of registers 28 PPA to the information inputs 38 of the microcomputer of the group of 41 numbers and their recording into fixed memory cells. In block 79, a set of commands are executed which organize the formation at the outputs 36 of the microcomputer of the group 41 of the reception signal of the second operand. In this case, on the tires 36 of the migpo computer 41 a single level signal will be generated, which will allow

the numbers from the outputs of the group 29 registers through the corresponding blocks of elements AND 32 groups and OR 34 groups to the information inputs 38 of the corresponding micro computers of group 41. In block 80, the execution of commands that organize the reception of the information from 38 micro computers of the group 41 numbers and writing them into fixed memory locations. In block 81 of the algorithm, a set of instructions are organized that organize the formation at output 37 of the microcomputer of the 4 signal group of the third operand reception signal. In this case, a unit level signal will be generated on tires 37 of the microcomputer of group 4, which will allow the arrival of numbers from the outputs of the registers of the group 30 through the appropriate blocks of elements AND 33 of the group and OR 34 groups to the information inputs 38 of the corresponding micro computers of group 41, In block 82 execution of commands that organize reception of received 1–1 sec, outputs of registers of the 30 group to 1 E1 life-saving inputs of 38 micro computers of a group of 41 numbers and writing them to fixed memory cells. In block 83, the value of y is calculated from the expression

(one).

In block 84, the commands are organized that organize the output of the calculation result (the value of y calculated from expression (1)) to the outputs of the microcomputer 40. In block 85 of the algorithm, the commands that organize the formation of a single level on the control unit shtskh tires 39 groups of microcomputers of group

.41. This single signal level will allow the passage of numbers from the outputs of 40 micro-computers of group 41 through the corresponding blocks of elements AND 42 groups Further, the numbers from the outputs of blocks of elements AND 42 groups are fed to the inputs of the corresponding blocks of elements HE 43 groups and 45 groups On the codes of the elements 43 groups form the inverse codes of the numbers formed at the outputs 40 of the microcomputer of group 41, which are fed to the inputs of the corresponding blocks of elements AND 46 of the group and to the inputs of the corresponding elements OR-NOT 44 groups. Since the trigger 50 is set to the zero state, the blocks of elements of the And 45 groups will be closed by the zero level.

the signal coming from the direct output of trigger 50 to the first control inputs of the And elements of this group. The Element And Block units of the 46 group will be opened at the first control input with a single signal level, coming from the inverse output of the trigger 50, All elements of And 45 and 46 groups will be closed at the second control input with a zero signal level coming from the output of the delay element 27. In this case, if on all tires of the group of codes of 40 microelectronics of group 41 single levels of signals are formed, the outputs of the corresponding blocks of elements of HE 43 groups will form massive levels of signals that go to the inputs of the corresponding elements of OR-NOT 44 groups and form on them -exit single level oi napov. These unit signal levels go through the corresponding OR elements 59 of the group to the installation inputs in O of the corresponding bits of registers I and 4; In addition, the unit signal levels from the outputs of the elements OR-EI 44 groups through the elements OR 9 of the group are set to O according to registers of the first, second, third factors 28, 29, 30 groups, respectively, will deregister those requests for which the values of the priority codes are zero. This is necessary so that there is no accumulation of unserved stroystvom requests. Since the decoder unit 8 analyzes only those priority

values are reset to zero. If requests for maintenance from individual FAC computers have not arrived at the device by the time the device triggered signal is received by the driver 60, then zero outputs will be generated at the outputs 40 of the corresponding microcomputers of group 41, which will form at the outputs

blocks of elements NOT 43 groups of high levels of signals. Thus, from the outputs of these blocks of elements is NOT 43 groups in this case to all the inputs of the corresponding blocks of elements And 46

groups - single signal levels arrive,

In the future, the device works as follows. After the values of the priority codes are formed at the inputs of the blocks And of the group 46, the output signal of the element 27 delays the start signal received by the device bus 60 and delayed by the element 27 for a while.

The delay time of the start signal element 27 is determined by the operation time of the microcomputer of group 41, the response time of the HE 53 AND 52, OR 54f blocks of the AND 46 groups of cells,

blocks of elements of HE 43 groups of elements of ITS-HE 44 groups of 1 SH 59 groups and time, are not necessary for setting registers 4 and 1 into a register. Signal from the output of delay element 27

enters the second control inputs of the AND blocks 45 and 46 of the groups, allowing the receipt of the values of the priority codes through the blocks of the elements AND 46 of the group and OR of the 20 groups for writing

codes | which are non-zero, then -3 registers 5 priority and will set

Requests with zero priority codes are not serviced by the device; -, .- give “Emergence of requests with zero BbJMH priority codes is possible in the device only when the codes of numbers that are generated at the output of 40 microeV computers of group 41 are entered into registers 5 priority through the blocks of elements NOT 43 groups AND 46 groups and IL1 1 20 groups, while on all buses of the group 40 outputs of the microcomputer high level signals must be formed. Otherwise, the zero values of the priority codes

trigger 19 in one state. In addition, after the time iT, the blocking of the arrival of the request signals through the inputs 2 of the device is released. On

 an inverse output of the flip-flop 9 generates a zero signal level, which closes the elements of the 3 groups on the control input. Thus, in this cycle of circulating in the buffer gQ, through register 4, only those prohibitions that are received by the device are fixed until the start signal on the bus 60 of the device. Single signal level from the direct output

They will be formed only when the trigger 19 opens, by the first control of the corresponding signals to the intercepting inputs, the blocks of H-groups of the H groups for servicing the KWS computer on the device 6. Elements of the group 10 prohibition. those. registers 28, 29, 30 group factors, respectively.

Since register 11 contains the code of the number of freedoms of the 1-1th ropes, they are not equal to

trigger 19 in one state. In addition, after the time iT, the blocking of the arrival of the request signals through the inputs 2 of the device is released. On

an inverse output of the flip-flop 9 generates a zero signal level, which closes the elements of the 3 groups on the control input. Thus, in this round of looping in the buffer register 4, only those prohibitions that are received by the device are fixed until the start signal on the bus 60 of the device is received. Single signal level from the direct output

the trigger 19 will open the first control inputs of the blocks of the elbows of the 6 group and the elements of the prohibition of group 10.

Since register 11 contains the code of the number of freedoms of the 1-1th ropes, they are not equal to

zero, the output of the OR-ilE 17 element will form a zero level (the signal that opens the AND AND prohibition elements of the group 10 on the inverse input. The output of the OR-NO element 18 will also generate a zero signal level, since its inputs receive a single level of signals

15

20

thirty

from those bits of register 4, in which IQ is near register 4. In this case, the unit

the signal will occur at another output of block 8 and the next pulse from generator 16 is transmitted. through the corresponding output of the device 7 groups. In the future, the work on priority servicing of incoming requests will be similar until the contents of counter 14 become equal to the code on the inverse outputs of register 11. In this case, at the output of comparison node 63, the unit signal level sets registers 11 and 4 to zero. this, at the output of the element OR NOT 17, a single signal level is formed, which will close the elements of the AND of the prohibition 10 of the group to the inverse input. At the output of the element OR NOT 1, a single signal level arises, which ycTaiiOBHT to the zero state trigger 19, and subtractive counter 14 to the single state.

When installed in O register 4 with a single signal level, coming from the output of node 63 of comparison, the loss of requests not served by the device due to the lack of free channel resources does not occur. Since only register 4 is zeroed, in register 1 there remain those requests that were not served in this cycle, and when trigger 19 is set to O, these requests are again sent to register 4. After counter 14 is set to one and the register is 11 in O, a zero signal level is generated at the output of the comparison node 63. The device operation cycle for priority service requests ends after the register 1 register with a single signal from the zero output of the trigger 19 is transmitted to the register 4. The next cycle of the device operation is possible after receiving the number of free channels in register 11 and starts with the input 60 unit start signal device. If at the time of the beginning of the priority service of requests, register 11 is set

Recorded signals received requests. If no request signals have been received, a single signal level is generated at the output of the OR-NOT element, which sets trigger 19 to O. In this case, a new cycle of device operation will begin when the start signal is received over bus 60. If at the output of the element OR NOT 18 there is a zero level of the signal, i.e. Register 4 contains requests for servicing the KVS computer; the device organizes their priority service. In this case, only the priority codes from priority registers 5 for which the requests in register 4 are fixed are transmitted to the inputs 61 of block 8 through the blocks of elements of the 6th group. On the remaining outputs of block 8 there will be zero codes. Unit 8 performs decoding of the most priority code (the most priority is the minimum code other than zero) and a single signal level is fixed at its corresponding output 62, which will allow the pulse from the generator of 16 pulses to pass through the corresponding Inhibit element of group 10 to the corresponding output of the group 7. In addition, this signal will set the corresponding bits of registers 1 and 4 and registers 28, 29 and 30 of the group factors to the zero state, thus excluding the selected request from the queue, and through the element OR 15 will go to the counting input of the counter 14, reducing its content by one. When the same bits of registers 1 and 4 are installed, a single signal level will be formed at the output of the corresponding element OR NOT of group 13, which will open the corresponding blocks of elements AND 24, 25 and 26 of the groups at the control input, thereby allowing the input of factor values to the inputs 21 , 22 and 23 groups to write to the corresponding registers of 28, 29 and 30 group factors when entering the next35

40

45

50

55

request for priority service. At the same time, in block 8, the most priority code out of all the remaining ones that arrived at the block inputs is deciphered, since the transmission of the previously selected code is blocked to zero in the previous step 15.

25

20

25

thirty

25

35

40

45

50

55

3

In O, the unit signal level from the output of the element OR-HE i 7 blocks the flow of pulses from the generator 16 to the outputs 7 of the device. In this case, the priority service of the requests will not be performed until register 11 receives a code for the number of free channels other than zero.

Work subtractive counter 14 for the next pulse of the generator 16 is combined in time with the cycles of selection of the priority code in block 8.

The reception of requests to register 1 and the factors to the corresponding registers 28, 29 and 30 of the group factors is blocked only during the device operation time interval from the moment the start signal arrives at input 60 until the arrival of priority codes to registers 5. register 4 requests and values of priority codes generated for them.

Claims (3)

Invention Formula 1 a Device for servicing requests, containing a group of priority registers.; - register, wake, counter, comparison node 3 start trigger, first element OR, group of elements AND, buffer register, register of the number of free channels, two elements OR NOT, first group And blocks, a block of decoders, a group of elements And a ban, a generator of pulses, with a group of inputs for the device's connection connected to a group of inputs for the register, a bit of discharge: 1 for the register of the same element And groups, g A group of information inputs of the device is connected to a group of inputs of the free ka1-1al5 register of which the inverse output group of which is connected to the first group of inputs of the comparison node, the output of which is connected to the general reset inputs of the buffer register and the free channel register, is connected with the group of inputs of the first element OR NOT, the code of which is connected to the reverse inputs of the elements AND the prohibition of the group whose outputs are the outputs of the device and are connected to the inputs first element 14 0 0 5 five OR, the outputs of the buffer register are connected to the inputs of the second element OR — NOT., And to the first inputs of the same-named blocks of the AND elements of the first group, the second inputs of which are connected to the direct output of the trigger trigger and the first direct inputs of the AND-inhibit elements of the group, the second direct the inputs of which are connected to the output of the pulse generator, the third direct output of each element And the prohibition of the group is connected to the same output of the decoder unit, the output groups of which are connected to the output groups of the same name blocks of the elements And the first groups The outputs of the elements AND of the group are connected to the corresponding inputs of the buffer: register 5, the group of inputs of the blocks of the elements AND of the first group are connected to the output groups of the same name priority register registers, the second inputs of the elements of the AND group are connected to the zero output of the trigger trigger The 5th bullet input of which is connected to the installation input of 1 counter, with the input of the second element OR NOT, the counter input of the counter is connected to the output of the first element I-lTDi, the group of outputs 0 counting connection with the second group of inputs of the comparison node, characterized in that, in order to expand the functionality of the possibilities by calculating the priority 5 request codes and the organization of rational priority service based on the use of significant regression codes as priority codes, the device contains from the second to 0 tenth group of blocks of elements AND, group of blocks of formation of priorities, three groups of registers of factors, delay element, two groups of blocks of elements OR, two groups of elements 5 OR-NOT, a group of blocks of elements NOT, a control trigger, a trigger of start modes, an element NOT, a second element OR, two elements AND and three, groups of elements OR, and the output of the i-element OR OR NOT of the first group (i 1, 2, p., And, p - the number of serviced computers) is connected to the first inputs ix of the OR elements: the first, second and third groups, the second inputs of which are connected to the device’s iM output, the output of the OR element of the first group is connected to the installation input O The i-ro bit of the register of the order, the output of the i-ro element ItTDi of the second group is connected with the installation input in О i-ro of the buffer register, the i-ro outputs of the block of NOT elements of the group are connected to the inputs of the i-ro element OR-NOT of the first group, ie the outputs of the buffer register and the register of the order are connected respectively to the first to the second inputs i -ro element OR NOT second. the group whose output is connected to the y inputs of the i-ro block of the elements of the second, third and fourth groups, i.e. the groups of inputs of the first, second, third factors of the device are connected respectively to the inputs of the i-ro block of the elements of the second, third and fourth groups, the outputs of the i-ro block of elements And the second, third and fourth groups are connected respectively to the information inputs ix of the factor registers of the first, second and third groups, the installation inputs in О of which are interconnected and with the output of the i-ro element OR of the third group, the outputs i -ro regis The factors of the first, second and third groups are respectively connected with the inputs of the i-ro block of elements And the fifth, sixth and seventh groups, the outputs of the i-ro block of the elements And the fifth, sixth and seventh groups are connected to the corresponding inputs of the i-ro block of elements OR of the first group, the output of which is connected to the information input of the i-ro group of the formation of priorities of the group, the first second and third-party 1 outputs of the data reception of which are connected respectively to the control inputs of the i-ro block of elements And the fifth, sixth and seventh groups, output issue management The result of the i-ro group priority formation block is connected to the control input of the i-ro block of elements And the eighth group, the information output of the i-ro block prioritization group is connected to the input of the i-ro block of elements And the eighth group, the output of which is connected to the i input ro block of NOT elements of the group and information input of the i-ro block of elements AND the ninth group, the output of the i-ro block of elements of the NOT group is connected to the information input of the i-ro block of elements And the tenth group, the direct output of the control trigger is connected to the first control input to ex block elements and nine of the group control flip-flop inverse output is connected to first inputs of the gate w of all units of elements of the tenth group, direct input and input of the control trigger setting are connected respectively to the first and second inputs of the device priority maintenance system set, the outputs of the ix blocks of the elements of the ninth and tenth groups are connected respectively to the first and second inputs of ix blocks of OR elements of the second group, the output of which is connected to the information inputs of the i-ro priority register of the group, the first and second inputs of setting the type of the start signal of the device are connected to the direct and inverse respectively The trigger start modes, the direct and inverse outputs of which are connected respectively to the first inputs of the first and second elements AND, the outputs of which are connected respectively to the first and second inputs of the second SHS element, the output of which is connected to the start inputs of all priority grouping units, the device start input connected to the second input of the first element And, with the inputs of the element NOT and the delay element and with the input of the setting in the priority group registers, the output of the delay element is connected to the input of the installation in 1 trigger and start and second by the control inputs of all elements of the blocks and the ninth and tenth groups, the input setting mode i-ro priorities forming unit group is connected with i-M input mode of the device, the element output is coupled to the second input of the second element I. 2. A device according to Claim 1, characterized in that the comparison node consists of two decoders, an OR element and a group of elements AND, each G-th output of the first and second decoders. (G 1,2, ..., C-1 ,, С - the number of outputs of the node decoder) is connected respectively to the first and second inputs of the G-ro element And, the outputs of elements AND groups are connected to the corresponding 1G (by their inputs of the element OR, whose output is the output of the node, the groups of the first and second decoders are connected respectively to the first and second groups of inputs of the node. 3. The device according to claim 1, characterized in that the block is decrypted, 47, 25 fV f / 4 / Dt m 0as.1 The rathors contain n decoders, n OR elements, and (t-1) -th bit unit of analysis (t is the number of outputs of the block decoder), each pth bitwise bit analysis unit (p 2,3,., ..., t-2) contains a group of n items NOT, an element And and a group of n elements And, a (t-1) th bit unit of the analysis contains a group of n elements And and a group of n-1 elements NOT, the first bit This analysis node contains a group of (nl) -ro element NOT, a group of (n-1) -th element AND and element I, with the i- group of block inputs connected to the input group of the i-ro decoder (i I, ... , n), each jth (j 3, ... , ml) the output of the i-th decoder is connected to the input of the i-ro element of the NOT group and the first input of the i-ro element AND of the group (jl) -ro of the bit analysis node, the second input of the first decoder is connected to the input of the first element of the HE group of the first of the first node of the first element OR, the nth input of the nth decoder is connected to the first input of the nth element of the AND group (ml) -ro of the bitwise node of analysis, output i-ro (i, ... , n-1) element 50 0 five NOT groups of each bit-by-bit analysis node, except for (ra-l) -ro, is connected to the (i + 2) -M input with (i + l) -ro by the nth element of AND group and with the iM input of element AND its porach the single analysis node, the output of the nth element of the NOT group of each bitwise analysis node, except for (ml) -ro, is connected to the nth input of the element AND its own bit analysis node, the output of the i-ro element of the NOT group (m-T) i-th bit of the analysis node is connected to (i + 2) -M input from (i + O-ro to (n-1) -th element AND of the group of its bit-side analysis node, the output of the element And i-ro (i 1, ..., m-3) of the unit analysis node is connected to the corresponding the input inputs of all elements of the AND group and the AND (i + l) -ro of the bit analysis node, the code of the AND (t-2) -th bit of the analysis node is connected to the corresponding inputs of all AND elements of the (ml) -ro of the bit analysis node, i-ro output (il, ..., ii) of the AND element of the j-ro group (j 1, ..., m-1) of the parity analysis node is connected to the JM input of the i-ro element OR group, the output which is the i-th output of the block. .65t bor03f X "X  | v v irjr- /. . . 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