SU1254485A1 - Device for distributing group requests among processors - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessing computing. ,, I yo yo | telny systems. The purpose of the invention is to increase the efficiency of the device. A new device is the use of two triggers, a pulse generator, three delay elements, a buffer register, t -1 groups of storage registers (P is the number of orders in a group), two OR-NOT elements, two groups of AND elements, and a group the OR elements, the encoder, the group of comparison circuits, the three groups of AND blocks, the three AND elements, and the links of the indicated elements and nodes, which ensures the achievement of the objective of the invention. 1 кп. (Ls

Description

The invention relates to computing and can be used in multiprocessor computing systems.

The purpose of the invention is to increase speed.

The drawing shows a block diagram of the device.

The device contains a group of storage registers 1, a group of elements 2, a buffer register 3, a group of decoders 4, a group of elements OR 5, a group of elements AND 6, an encoder 7, a group of comparison circuits 8, blocks of elements AND 9 of a group, a shift register 10 blocks of elements 11 groups, element IPI-NOT 12, element OR-NOT 13, group of elements OR 14, group of elements AND 15, blocks of elements AND 16 groups, register 17 readiness of processors, generator 18 pulses, element And 19 trigger 20 trigger, group of elements

And 21, delay element 22, delay element 23, delay element 24, shift control trigger 25, AND element 26, AND element 27, AND element 28, device start input 29, device reset input 30, device 31 input group, device group information outputs 32 devices and a group of information inputs 33 devices.

The device works as follows

The initial state of the device is characterized by the fact that registers 1, 3, 10, triggers 20 and 25 are set to O (not shown).

The operation of the device consists of three stages and starts at the start signal, arriving at input 29 and setting the trigger 20 to the state ti 11 I "

At the first stage, a queue of applications is formed, which enters input 31 and fills storage registers 1, ndica application from the last register 1 is not overwritten into buffer register 3,

At the second stage, the priority application is selected from the group accepted in register 3, and the code of the number of required processors of the priority application is transferred to shift register 10

At the third stage, the processors are assigned to the priority application and the code for the number is transferred to the free processors. After the allocation of the processor of the priority application, the discharge is quenched.

distributed application, and then the choice of the next priority application from the group in register 3 and the distribution of free processors. This stage continues until the group's applications are discussed. Its completion is the zero state of register 3. After that, the device proceeds to the first stage, in which register 1 is accepted as input 31. From the last register 1, the next application is transferred to register 3, which begins the second stage. In the future, the device works similarly.

The formation of the queue in the first stage is carried out in the following manner.

According to the first pulse of the generator 18 through the element And 19, the last element And 21 of the group, the element 22 of the delay and the first element And 21 of the group, input 31 is received in the first register 1. Elements And 21 are opened by the first inputs with a single signal from the output of the elements SH-NOT 12, since register 3 is in the state O.

The storage registers 1 and buffer register 3 have the same structure. Each of these registers for each

The applications in the group contain 4 groups of bits. In turn, the group of bits provides storage of the code of the number of required processors for solving the problem of this application, the priority code of the application in the group, and the CODE of the task number. Thus, the group application at input 31 contains codes for the number of processors required, priority codes and task number codes.

Received in register 1, the application with a continuous flow on the clock signal of the generator 18, coming through the elements 21 to control the inputs of registers 4, advances on registers 1. On the corresponding clock signal, the first application appears in the last register 1, and on the next signal it from the last register 1 is rewritten to the buffer register 3. The delay element 22 is necessary to ensure recording of the application in register 3 before the next application appears at the inputs of register 1. As soon as the application is in register 3 at the output of the element W-NOT 12, a single signal is lowered.

mats,

3

and the element 21 is closed, which prohibits the supply of clock pulses.

Thus, at the beginning of the transition of the device to the second stage, it is characterized by the following state.

In registers 1, an ocher for group orders is formed, the next group application is saved at input 31, in register 3 there is a first request for registration.

Since the shift register is in the state O, the output of the element OR NOT 13 has a single signal, which opens element 27 on the second input, and element 26 is closed in the inverse. Since trigger 25 is in the state O, then the single signal from its zero output open And on the second inputs elements And 9.

At the second stage, by means of decoders, 4 binary priority codes of the applications are converted into one-position ones. The highest priority corresponds to the minimum, non-zero code. The same outputs of the decoders 4 are combined with the same-name elements OR 5. In this case, the number of the IL element corresponds to the value of the priority code. And 6, included in the priority scheme with the outputs of the elements OR 5, selects the most priority signal from the set of excited outputs of the elements OR 5 so that the inputs of the encoder 7 form a unitary code containing the unit in a certain position. The number of this position corresponds to the value of the priority code. The binary code signals from the output of the encoder 7 are compared with the binary priority codes for the requests in the group in the corresponding comparison circuits 8. Here, a single signal is generated by only one of the comparison circuits 8. With this signal, elements AND 9 of the corresponding group are opened, and the code of the number of required processors, the priority application, is transmitted to the shift register.

By means of the delay element 23, a pulse delay of the generator 18 at the single input of the trigger 25 is provided so that it is sent after the information has been set at the outputs of the register 10.

After receiving the information in the shift register 10, a single signal p of the output of the NL-HE 13 element is taken, and

I open the entrance.

element 26 on the inverse of the delayed pulse of the generator 18 is set to 1 trigger 25, this removes a single signal from the second inputs of the elements 9, thereby blocking the transmission of signals from their outputs to the shift register 10. The signal from the single output of the shift control trigger 25 opens element 28 at the first input, thus the device proceeds to the execution of the third stage.

Let in the buffer register 3 received a group application containing three requests that have the following binary priority codes set: 3,1,2, and for the first request it is required to solve the problem with the number on three processors, for the second - on one processor, and for the third, a task on two processors.

Under these conditions, the single signals of the priority code, after being converted by the decoder 4, arrive at the inputs of the elements OR 5 as follows: from the third output of the decoder 4 to the first input of the element OR 5e; from the first output of the decoder 4 J to the second input of the element ШШ.5 “; from the second output of the decoder 4 to

25 30 d 5

0 5

five

2nd input element OR 5

Thus, at the outputs of the elements OR 5, the following code is formed: 111 ..., 0. With a single signal from the output of the element OR 5, all elements AND 6 are closed on the nepBim inverse inputs, and the unitary code of the following form is fed to the inputs of the encoder 7: 10,000 ... O, i.e. having a single state on the first input. The encoder 7 converts it into a binary unit code, i.e. 0 .... 1, arriving at the first inputs of all circuits 8 of the comparison. In this case, the comparison takes place in the circuit 8, a single signal from the output of which the code of the number of required processors for the second request through the elements 9 is written to the shift register 10. In addition, the AND signal and the I2 element at the first input are opened with a single signal from the output of the comparison circuit 8.

At the third stage, by means of pulses of the generator, coming through the open element I 28 to the input of the shift of the register 10, the search and

allocation of free processors in the demand for fz

Suppose that there are four processors in the system for this example, and a readiness signal is received from the second processor in the second discharge register register 17 of the processors.

Since the number of required processors in the shift register 10 is indicated by the presence of units in the adjacent lower bits, the units coincide in the AND 15 element. This occurs on the first impulse of the generator 18, and a single signal from the output of the 15.2 element is opened. elements AND IS, through which the task number code from buffer register 3 is transmitted to the group of outputs 32 of the device. A single signal from the output of the RSHI element 11 is set to the state O of the second bits of the registers 10 and 11. After this, the register 10 is in the state and, through the YLE-HE 13 element, the I 2 elements are delayed through the third inputs. the time of which is determined by the transient time in the register. 10 and the element OR-NOT 13, the register bit group 3 of the second request and the shift control trigger 25 are set to O.

After that, a selection is made. next priority of the third request in this way,

On verifying the distribution of the processors to all three requests, register 3 is in the state O, and at the output of the element OR NOT 12 a single signal is formed, which opens the elements 21. At the next clock signal of the generator 18, the group currents are shifted in registers 1 and the next applications for distributing processors. In the future, the operation of the device is similar.

Claims (1)

Invention Formula A device for distributing group orders across processors, containing a shift register, a group of storage registers, two groups of elements AND a nepBjTO group of elements OR, the first element Hj of a processor readiness register, which is connected to the first inputs of the elements AND the first rpynnbis whose second inputs are connected to group, the outputs of the shift register whose reset inputs are connected to the corresponding B:., - moves of the elements OR of the first group, with the corresponding reset inputs of the processor readiness register, a group of information inputs the first group's storage register is a group of device inputs for inputs, the clock input of each group's storage register, except the last one, is connected to the output of the corresponding AND element of the second group, the information output of each group's storage register, except the last one, is connected to the group of information inputs of the next storage register group, the input shift register shift is connected to the output of the first element And the first input of each element And the second group, except the first and last g connected to the output of the previous about an element AND of this group, the second input of each element And the second group is connected to the first input of each subsequent element AND of this group, about t -, l, and so that in order to increase speed, the third and fourth groups of elements AND are entered into it , three groups of AND blocks, the second group of OR elements, three delay elements, a group of decoders, an encoder, a group of comparison circuits. Two elements OR NOT, second, third and fourth elements AND, trigger trigger, shift control trigger, buffer register and pulse generator, the output of which is connected to the first input of the second AND element, the second input of which is connected to the single trigger trigger output and zero inputs which are the control inputs for starting and resetting the device, respectively, the output of the first element AND through the first delay element connected to the first direct input of the third element I, and to the first inputs of the AND elements of the third group, The output of the last element AND of the second group is connected to the clock input of the buffer register and through the second delay element to the second input of the first element AND of the second group and to the clock input of the last storage register of the group, the information output group of which is connected to the corresponding group of information inputs of the buffer register, output i -ro 712544858 n, n - the number of applications) of the AND-units of the first group are connected to the information inputs of the re-; shift register, the outputs of which are connected to the inputs of the second element OR NOT, the 5 output of which is connected to the third inputs of the AND elements of the third group, with the inverse input of the fourth element And and the second input of the third element And, the output of the third element And 10 connected to, zero input the shift control trigger, a single input of which is connected to the output of the fourth element AND, a single output of the shift control trigger is connected 15 to the first input of the first element AND, the output of each element AND of the third group of connection 1 to the reset input of the discharge Dov single rpymnj buffer register, code of all blocks of elements (1 1, ..., A number of the buffer register task number code is connected to the information input of the i-ro element block of the second group and the iM input of the first element OR NOT, the outputs of the i-th priority code bits and the code of the number of required processors of the buffer register are connected respectively to the i-ro inputs the group decoder, to the information inputs of the i-ro block of elements AND the first group, the same outputs of the group decoders are connected to the inputs of the same element OR of the second group, the output of the first element OR of the second group is connected to the first input of the encoder, you each od i-ro of the OR gate of the second group, starting with the second is connected to the straight nym the input of the j-th (J 1,2, ..., p) elements of the AND 2 of the second group are connected to the ON AND the fourth group, starting with the perforation (the memory inputs of the blocks of the same name, the outputs of the OR elements of the second group are connected with the corresponding inverse inputs of all subsequent elements of the fourth group, outputs 25 of the block of elements AND the third group of elements and the fourth group of a connection, the outputs of which are grouped with the inputs of the encoder, starting with the information outputs of the second device, outputs Ш1 of the controller are connected to the first inputs of the group comparison circuits to the inputs of like elements OR of the first group, outputs The second inputs of each circuit compared to the processor readiness register of the CPU are connected to the inputs of the group decoder of the same name, the output of each shelter is equal to the first control input of the block of the same name of the elements of the first group of controllers the inputs of blocks of elements of the second group and to the second input of the element of the same name of the third group, the output of the first element OR is NOT connected to the second input-40 ™ shift, the clock input of the last elements of the second rpyniai, the second register of the group and the first ry control inputs of all blocks the input of the first element AND the second group the elements of the first group are connected via the third electr to the zero output of the trigger control- (the moment of delay with the output of the shift and to the first direct input of the ice element of the second element and the second gruffly fourth element And, the outputs of all types. elements of the third group, the output of each element of the first group is connected to the control input of the block of the same name of the elements of the third group, the outputs of which are the group of information outputs of the device and connected to the inputs of the elements of the same name OR of the first group, the outputs A group of information inputs of the device, the output of the second element I is connected to the first input of the last element I of the second group, to the second input of the first element I and through the second delay element to the first direct W1F1 input of the fourth element I, the second direct input of which is connected to the inverse output trigger trigger23 Editor I. Casarda Compiled by M. Kudr Shev Tehred I.Popovich Proofreader L. Patay Order 4722/53 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4